Changeset c16c8c6 in rtems-docs

Timestamp:

05/04/22 11:03:38 (2 months ago)

Author:

Sebastian Huber <sebastian.huber@…>

Branches:

master

Children:

9ba26e7

Parents:

5475c9c

git-author:

Sebastian Huber <sebastian.huber@…> (05/04/22 11:03:38)

git-committer:

Sebastian Huber <sebastian.huber@…> (05/04/22 11:04:15)

Message:

user: Update architectures supporting TLS

File:

• user/overview/index.rst (modified) (1 diff)

user/overview/index.rst

@@ -356 +356 @@
 .. [#] Thread-local storage requires some support by the tool chain and the
        RTEMS architecture support, e.g. context-switch code.  It is supported
-       at least on ARM, PowerPC, RISC-V, SPARC and m68k.  Check the
-       `RTEMS CPU Architecture Supplement <https://docs.rtems.org/branches/master/cpu-supplement.pdf>`_
-       if it is supported.
+       at least on ARM, AArch64, PowerPC, RISC-V, SPARC, MicroBlaze, Nios II,
+       and m68k.  Check the `RTEMS CPU Architecture Supplement
+       <https://docs.rtems.org/branches/master/cpu-supplement.pdf>`_ if it is
+       supported.