Changeset c16c8c6 in rtems-docs


Ignore:
Timestamp:
05/04/22 11:03:38 (2 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
9ba26e7
Parents:
5475c9c
git-author:
Sebastian Huber <sebastian.huber@…> (05/04/22 11:03:38)
git-committer:
Sebastian Huber <sebastian.huber@…> (05/04/22 11:04:15)
Message:

user: Update architectures supporting TLS

File:
1 edited

Legend:

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  • user/overview/index.rst

    r5475c9c rc16c8c6  
    356356.. [#] Thread-local storage requires some support by the tool chain and the
    357357       RTEMS architecture support, e.g. context-switch code.  It is supported
    358        at least on ARM, PowerPC, RISC-V, SPARC and m68k.  Check the
    359        `RTEMS CPU Architecture Supplement <https://docs.rtems.org/branches/master/cpu-supplement.pdf>`_
    360        if it is supported.
     358       at least on ARM, AArch64, PowerPC, RISC-V, SPARC, MicroBlaze, Nios II,
     359       and m68k.  Check the `RTEMS CPU Architecture Supplement
     360       <https://docs.rtems.org/branches/master/cpu-supplement.pdf>`_ if it is
     361       supported.
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