Index: ps/m32c/m32cbsp/README
===================================================================
--- bsps/m32c/m32cbsp/README	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,4 +1,0 @@
-This BSP is designed to operate on a variety of M16C and M32C variants.
-It is expected that this BSP will also be able to support R8C variants.
-
-It currently only runs on the M32C simulator in GDB.
Index: ps/m32c/m32cbsp/btimer/btimer.c
===================================================================
--- bsps/m32c/m32cbsp/btimer/btimer.c	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,69 +1,0 @@
-/*
- *  This file implements a stub benchmark timer that is sufficient to
- *  satisfy linking the RTEMS Benchmarks.
- */
-
-/*
- *  COPYRIGHT (c) 1989-2001.
- *  On-Line Applications Research Corporation (OAR).
- */
-
-#include <bsp.h>
-#include <rtems/btimer.h>
-
-#include <varvects.h>
-
-bool benchmark_timer_find_average_overhead;
-uint32_t benchmark_timer_overhead = 10;
-
-#define TABSR *((uint8_t *)0x340)
-#define TA0MR *((uint8_t *)0x356)
-#define TA0   *((uint16_t *)0x346)
-#define TA0IC *((uint8_t *)0x6c)
-
-static int benchmark_timer_interrupts;
-
-static void __attribute__((interrupt)) timer_ra_interrupt(void);
-
-#define ivec_timer_a0 12
-
-void __attribute__((interrupt))
-timer_ra_interrupt(void)
-{
-  benchmark_timer_interrupts++;
-  TA0IC = 0x05;
-
-}
-
-void benchmark_timer_initialize(void)
-{
-  benchmark_timer_interrupts = 0;
-  _set_var_vect (timer_ra_interrupt, ivec_timer_a0);
-  TA0MR = 0x00;
-  TA0   = 0xffff;
-  TA0IC = 0x05;
-  TABSR = 0x55;
-}
-
-benchmark_timer_t benchmark_timer_read(void)
-{
-  uint32_t count;
-
-  count = 0xFFFF - TA0;
-  count += benchmark_timer_interrupts * 0xFFFFL;
-
-  if (!benchmark_timer_find_average_overhead) {
-    if ( count > benchmark_timer_overhead )
-      count -= benchmark_timer_overhead;
-    else
-      count = 0;
-  }
-  return count;
-}
-
-void benchmark_timer_disable_subtracting_average_overhead(
-  bool find_flag
-)
-{
-  benchmark_timer_find_average_overhead = find_flag;
-}
Index: ps/m32c/m32cbsp/config/m32csim-testsuite.tcfg
===================================================================
--- bsps/m32c/m32cbsp/config/m32csim-testsuite.tcfg	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,28 +1,0 @@
-#
-# The GDB M32C Simulator does not have a tick interrupt.
-#
-
-include: testdata/disable-iconv-tests.tcfg
-include: testdata/require-tick-isr.tcfg
-include: testdata/disable-jffs2-tests.tcfg
-include: testdata/disable-mrfs-tests.tcfg
-
-exclude: crypt01
-exclude: fileio
-exclude: flashdisk01
-exclude: fsbdpart01
-exclude: fsdosfsformat01
-exclude: fsdosfswrite01
-exclude: fsdosfsname01
-exclude: fsrfsbitmap01
-exclude: sha
-exclude: spstkalloc02
-exclude: sptls01
-exclude: sptls04
-exclude: tmcontext01
-exclude: utf8proc01
-
-#
-# Does not compile. See #3025.
-#
-exclude: linpack
Index: ps/m32c/m32cbsp/config/m32csim.cfg
===================================================================
--- bsps/m32c/m32cbsp/config/m32csim.cfg	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,16 +1,0 @@
-#
-#  Config file for the M32C GDB Simulator
-#
-
-include $(RTEMS_ROOT)/make/custom/default.cfg
-
-RTEMS_CPU=m32c
-
-CPU_CFLAGS = -mcpu=m32cm
-
-# Unreported GCC Bug results in ICE in cpu.c. Use -O0
-# CFLAGS_OPTIMIZE_V = -Os -g
-CFLAGS_OPTIMIZE_V = -O0 -g
-CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections
-
-LDFLAGS = -Wl,--gc-sections
Index: ps/m32c/m32cbsp/console/console-io.c
===================================================================
--- bsps/m32c/m32cbsp/console/console-io.c	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,65 +1,0 @@
-/*
- *  This file contains the hardware specific portions of the TTY driver
- *  for the serial ports on the m32c simulator in gdb.
- */
-
-/*
- *  COPYRIGHT (c) 1989-2008.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#include <bsp.h>
-#include <bsp/console-polled.h>
-#include <rtems/libio.h>
-#include <stdlib.h>
-#include <assert.h>
-
-/*
- *  console_initialize_hardware
- *
- *  This routine initializes the console hardware.
- *
- */
-
-void console_initialize_hardware(void)
-{
-  return;
-}
-
-/*
- *  console_outbyte_polled
- *
- *  This routine transmits a character using polling.
- */
-ssize_t sys_write(int fd, const void *buf, size_t count);
-void console_outbyte_polled(
-  int  port,
-  char ch
-)
-{
-  sys_write( 2, &ch, 1 );
-}
-
-/*
- *  console_inbyte_nonblocking
- *
- *  This routine polls for a character.
- */
-
-int console_inbyte_nonblocking(
-  int port
-)
-{
-  return -1;
-}
-
-#include <rtems/bspIo.h>
-
-static void M32CsimBSP_output_char(char c) { console_outbyte_polled( 0, c ); }
-
-BSP_output_char_function_type       BSP_output_char = M32CsimBSP_output_char;
-BSP_polling_getchar_function_type   BSP_poll_char = NULL;
Index: ps/m32c/m32cbsp/console/syscalls.S
===================================================================
--- bsps/m32c/m32cbsp/console/syscalls.S	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,43 +1,0 @@
-/*
- *  System call support for simulator in gdb.
- *  Adapted from newlib 1.16.0.
- */
-
-#define SYS_exit        1
-#define SYS_open        2
-#define SYS_close       3
-#define SYS_read        4
-#define SYS_write       5
-#define SYS_lseek       6
-#define SYS_unlink      7
-#define SYS_getpid      8
-#define SYS_kill        9
-#define SYS_fstat       10
-#define SYS_sbrk        11
-
-#define POUND #
-#define SYSCALL(N) mov.b POUND N,0x400
-
-#define S(n) _sys_##n: .global _sys_##n | SYSCALL(SYS_##n) | rts
-
-S(write)
-S(exit)
-S(sbrk)
-
-       .global _abort
-_abort:
-        /* This is for debuggers.  The simulator stops here too. */
-        brk
-
-        /* Else, fall back on the simulator's "kill me" option.  */
-#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
-        mov.w   #42,r1
-#else
-        mov.w   #42,r0
-#endif
-
-        SYSCALL(SYS_kill)
-
-        /* Else, exit. */
-        jmp.a   __exit
-
Index: ps/m32c/m32cbsp/doxygen.h
===================================================================
--- bsps/m32c/m32cbsp/doxygen.h	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,15 +1,0 @@
-/**
-  *  @defgroup bsp_m32c M32C
-  *
-  *  @ingroup bsp_kit
-  *
-  *  @brief M32C Board Support Packages
-  */
-
-/**
-  *  @defgroup m32c_m32cbsp M32C M32CBSP Modules
-  *
-  *  @ingroup bsp_m32c
-  *
-  *  @brief M32C M32CBSP Modules
-  */
Index: ps/m32c/m32cbsp/headers.am
===================================================================
--- bsps/m32c/m32cbsp/headers.am	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,6 +1,0 @@
-## This file was generated by "./boostrap -H".
-
-include_HEADERS =
-include_HEADERS += ../../../../../../bsps/m32c/m32cbsp/include/bsp.h
-include_HEADERS += include/bspopts.h
-include_HEADERS += ../../../../../../bsps/m32c/m32cbsp/include/tm27.h
Index: ps/m32c/m32cbsp/include/bsp.h
===================================================================
--- bsps/m32c/m32cbsp/include/bsp.h	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,49 +1,0 @@
-/**
-  *  @file
-  *
-  *  @ingroup m32c_bsp
-  *
-  *  @brief m32c simulator definitions in gdb
-  */
-
-/*  bsp.h
- *
- *  This include file contains some definitions specific to the
- *  h8 simulator in gdb.
- *
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef LIBBSP_M32C_M32CBSP_BSP_H
-#define LIBBSP_M32C_M32CBSP_BSP_H
-
-#include <bspopts.h>
-#include <bsp/default-initial-extension.h>
-
-#include <rtems.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  *  @defgroup m32c_bsp Clock Tick Support
-  *
-  *  @ingroup m32c_m32cbsp
-  *
-  *  @brief Clock Tick Support Package
-  */
-
-void *clock_driver_sim_idle_body(uintptr_t);
-#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
Index: ps/m32c/m32cbsp/include/tm27.h
===================================================================
--- bsps/m32c/m32cbsp/include/tm27.h	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,1 +1,0 @@
-#include <rtems/tm27-default.h>
Index: ps/m32c/m32cbsp/start/bsp_specs
===================================================================
--- bsps/m32c/m32cbsp/start/bsp_specs	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,9 +1,0 @@
-%rename endfile old_endfile
-%rename startfile old_startfile
-
-*startfile:
-%{!qrtems: %(old_startfile)} \
-%{!nostdlib: %{qrtems: crtbegin.o%s}}
-
-*endfile:
-%{!qrtems: %(old_endfile)} %{!nostdlib: %{qrtems: crtend.o%s}}
Index: ps/m32c/m32cbsp/start/bspstart.c
===================================================================
--- bsps/m32c/m32cbsp/start/bspstart.c	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,24 +1,0 @@
-/*
- *  COPYRIGHT (c) 1989-2008.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#include <bsp.h>
-#include <bsp/bootcard.h>
-
-extern void sys_sbrk(int);
-
-/*
- * This routine would usually do the bulk of the system initialization.
- * But if a BSP doesn't need to do anything, it can use this version.
- */
-
-void bsp_start( void )
-{
-  /* Tell the simulator not to test for heap/stack collision */
-  sys_sbrk(0);
-}
Index: ps/m32c/m32cbsp/start/crtn.S
===================================================================
--- bsps/m32c/m32cbsp/start/crtn.S	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,58 +1,0 @@
-/*
-
-Copyright (c) 2005 Red Hat Incorporated.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-    Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-
-    Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-
-    The name of Red Hat Incorporated may not be used to endorse
-    or promote products derived from this software without specific
-    prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*/
-
-
-#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
-#define A16
-#define A(n,w) n
-#define W w
-#else
-#define A24
-#define A(n,w) w
-#define W l
-#endif
-
-	.section	.init,"ax",@progbits
-	jsr.a	_m32c_run_preinit_array
-	jsr.a	_m32c_run_init_array
-	exitd
-	.global	__m32c_init_end
-__m32c_init_end:
-
-	.section	.fini,"ax",@progbits
-
-	exitd
-	.global	__m32c_fini_end
-__m32c_fini_end:
-
-	.text
-
Index: ps/m32c/m32cbsp/start/linkcmds
===================================================================
--- bsps/m32c/m32cbsp/start/linkcmds	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,207 +1,0 @@
-/*
- * Declare some sizes.
- */
-_RamBase = DEFINED(_RamBase) ? _RamBase : 0x200000;
-_RamSize = DEFINED(_RamSize) ? _RamSize : 0x800000;
-_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
-
-/* Default linker script, for normal executables */
-OUTPUT_FORMAT("elf32-m32c", "elf32-m32c",
-	      "elf32-m32c")
-OUTPUT_ARCH(m32c)
-ENTRY(_start)
-STARTUP(start.o)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-MEMORY {
-	RAM (w) : ORIGIN = 0x200000, LENGTH = 0x800000
-	VEC (r) : ORIGIN = 0xffffdc, LENGTH = 32
-	RESETVEC (r) : ORIGIN = 0xfffffc, LENGTH = 4
-}
-SECTIONS
-{
-  /* There are three cases we care about: First, RW data that must be
-     in the low 64k.  This will always be copied from ROM.  Second, RO
-     data that must be in the low 64k.  This may be copied from ROM if
-     the ROM is above 64k.  Third, anything that does not need to be
-     in the first 64k.  Chips normally only have two memory regions;
-     low ram and either high or low rom.  We map the low rom needs
-     into one of the actual regions.  */
-
-  /* .text goes first so the rom image of ram data will follow it.  */
-  .text           :
-  {
-    *(.text .stub .text.* .gnu.linkonce.t.*)
-    KEEP (*(.text.*personality*))
-    /* .gnu.warning sections are handled specially by elf32.em.  */
-    *(.gnu.warning)
-    *(.interp .hash .dynsym .dynstr .gnu.version*)
-    PROVIDE (__etext = .);
-    PROVIDE (_etext = .);
-    PROVIDE (etext = .);
-    . = ALIGN(2);
-  } > RAM =0
-
-  /* rodata will either be part of data, or will be in low rom.  So we
-     might be spanning it, or we might not.  This lets us include it
-     in our calculations when appropriate.  */
-
-  .rodata : {
-    . = ALIGN(2);
-    *(.plt)
-    KEEP (*(.init))
-    KEEP (*(.fini))
-    *(.rodata .rodata.* .gnu.linkonce.r.*)
-    KEEP (*(SORT(.rtemsroset.*)))
-    *(.rodata1)
-    *(.eh_frame_hdr)
-    KEEP (*(.eh_frame))
-    KEEP (*(.gcc_except_table)) *(.gcc_except_table.*)
-    . = ALIGN(2);
-    PROVIDE(__romdatastart = .); /* IF_ROROM */
-  } > RAM
-
-  .tdata : {
-    __TLS_Data_begin = .;
-    *(.tdata .tdata.* .gnu.linkonce.td.*)
-    __TLS_Data_end = .;
-  } > RAM
-  .tbss : {
-    __TLS_BSS_begin = .;
-    *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
-    __TLS_BSS_end = .;
-  } > RAM
-  __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
-  __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
-  __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
-  __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
-  __TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
-  __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
-
-  .data : {
-    . = ALIGN(32 / 8);
-    PROVIDE (__datastart = .); /* IF_ROROM */
-    PROVIDE (__preinit_array_start = .);
-    KEEP (*(.preinit_array))
-    PROVIDE (__preinit_array_end = .);
-    PROVIDE (__init_array_start = .);
-    KEEP (*(.init_array))
-    PROVIDE (__init_array_end = .);
-    PROVIDE (__fini_array_start = .);
-    KEEP (*(.fini_array))
-    PROVIDE (__fini_array_end = .);
-
-    /* gcc uses crtbegin.o to find the start of
-       the constructors, so we make sure it is
-       first.  Because this is a wildcard, it
-       doesn't matter if the user does not
-       actually link against crtbegin.o; the
-       linker won't look for a file to match a
-       wildcard.  The wildcard also means that it
-       doesn't matter which directory crtbegin.o
-       is in.  */
-    KEEP (*crtbegin*.o(.ctors))
-    /* We don't want to include the .ctor section from
-       from the crtend.o file until after the sorted ctors.
-       The .ctor section from the crtend file contains the
-       end of ctors marker and it must be last */
-    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-
-    KEEP (*crtbegin*.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-
-    KEEP (*(.jcr))
-    *(.data.rel.ro.local) *(.data.rel.ro*)
-    *(.dynamic)
-
-    *(.data .data.* .gnu.linkonce.d.*)
-    KEEP (*(SORT(.rtemsrwset.*)))
-    KEEP (*(.gnu.linkonce.d.*personality*))
-    SORT(CONSTRUCTORS)
-    *(.data1)
-    *(.got.plt) *(.got)
-
-    . = ALIGN(2);
-    _edata = .;
-    PROVIDE (edata = .);
-    PROVIDE (__dataend = .);
-  } > RAM 
-
-  /* Note that __romdatacopysize may be ZERO for the simulator, which
-     knows how to intialize RAM directly.  It should ONLY be used for
-     copying data from ROM to RAM; if you need to know the size of the
-     data section, subtract the end symbol from the start symbol.  */
-  /* Note that crt0 assumes this is even; all the start/stop symbols
-     are also assumed word-aligned.  */
-  PROVIDE (__romdatacopysize = 0);
-
-  .bss : {
-    . = ALIGN(2);
-    PROVIDE (__bssstart = .);
-    *(.dynbss)
-    *(.bss .bss.* .gnu.linkonce.b.*)
-    *(COMMON)
-    . = ALIGN(2);
-    PROVIDE (__bssend = .);
-    _end = .;
-    PROVIDE (end = .);
-  } > RAM
-  PROVIDE (__bsssize = 0);
-
-  .rtemsstack (NOLOAD) : {
-    *(SORT(.rtemsstack.*))
-  } > RAM
-
-  PROVIDE (_WorkAreaBase = .);
-  . = 0xa00000;
-  PROVIDE (_WorkAreaEnd = .);
-  PROVIDE (_WorkAreaSize = _WorkAreaEnd - _WorkAreaBase);
-
-  .vec : {
-    *(.vec)
-  } > VEC
-  .resetvec : {
-    *(.resetvec)
-  } > RESETVEC
-
-  /* The rest are all not normally part of the runtime image.  */
-
-  /* Stabs debugging sections.  */
-  .stab          0 : { *(.stab) }
-  .stabstr       0 : { *(.stabstr) }
-  .stab.excl     0 : { *(.stab.excl) }
-  .stab.exclstr  0 : { *(.stab.exclstr) }
-  .stab.index    0 : { *(.stab.index) }
-  .stab.indexstr 0 : { *(.stab.indexstr) }
-  .comment       0 : { *(.comment) }
-  /* DWARF debug sections.
-     Symbols in the DWARF debugging sections are relative to the beginning
-     of the section so we begin them at 0.  */
-  /* DWARF 1 */
-  .debug          0 : { *(.debug) }
-  .line           0 : { *(.line) }
-  /* GNU DWARF 1 extensions */
-  .debug_srcinfo  0 : { *(.debug_srcinfo) }
-  .debug_sfnames  0 : { *(.debug_sfnames) }
-  /* DWARF 1.1 and DWARF 2 */
-  .debug_aranges  0 : { *(.debug_aranges) }
-  .debug_pubnames 0 : { *(.debug_pubnames) }
-  /* DWARF 2 */
-  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
-  .debug_abbrev   0 : { *(.debug_abbrev) }
-  .debug_line     0 : { *(.debug_line) }
-  .debug_frame    0 : { *(.debug_frame) }
-  .debug_str      0 : { *(.debug_str) }
-  .debug_loc      0 : { *(.debug_loc) }
-  .debug_macinfo  0 : { *(.debug_macinfo) }
-  /* SGI/MIPS DWARF 2 extensions */
-  .debug_weaknames 0 : { *(.debug_weaknames) }
-  .debug_funcnames 0 : { *(.debug_funcnames) }
-  .debug_typenames 0 : { *(.debug_typenames) }
-  .debug_varnames  0 : { *(.debug_varnames) }
-  /DISCARD/ : { *(.note.GNU-stack) }
-}
Index: ps/m32c/m32cbsp/start/start.S
===================================================================
--- bsps/m32c/m32cbsp/start/start.S	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,183 +1,0 @@
-/*
-
-Copyright (c) 2005 Red Hat Incorporated.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-    Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-
-    Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-
-    The name of Red Hat Incorporated may not be used to endorse
-    or promote products derived from this software without specific
-    prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*/
-
-#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
-#define A16
-#define A(n,w) n
-#define W w
-#define ALIGN 1
-#else
-#define A24
-#define A(n,w) w
-#define W l
-#define ALIGN 2
-#endif
-
-	.text
-
-	.global _start
-_start:
-.LFB2:
-	fset	U	/* User stack */
-	ldc	#__ISR_Stack_area_end,sp
-
-#ifdef A16
-	mov.b	#%hi8(__romdatastart),r1h
-	mov.w	#%lo16(__romdatastart),a0
-	mov.w	#__datastart,a1
-#else
-	mov.l	#__romdatastart,a0
-	mov.l	#__datastart,a1
-#endif
-	mov.w	#__romdatacopysize,r3
-	shl.w	#-1,r3
-	smovf.w
-
-#ifdef A16
-	mov.w	#__bssstart,a1
-#else
-	mov.l	#__bssstart,a1
-#endif
-	mov.w	#__bsssize,r3
-	shl.w	#-1,r3
-	mov.w	#0,r0
-	sstr.w
-
-	/* jsr.a	__m32c_init */
-
-	jsr.a	_boot_card
-.LFE2:
-
-#ifdef A24
-	/* rv in r0, ok for arg0 */
-#else
-	mov.w	r0,r1
-#endif
-
-	.global _bsp_reset
-_bsp_reset:
-	jsr.a	_sys_exit
-
-	.text
-
-	.global	_m32c_run_preinit_array
-	.type	_m32c_run_preinit_array,@function
-_m32c_run_preinit_array:
-	mov.W	#__preinit_array_start,a0
-	mov.W	#__preinit_array_end,a1
-	jmp.w	_m32c_run_inilist
-
-	.global	_m32c_run_init_array
-	.type	_m32c_run_init_array,@function
-_m32c_run_init_array:
-	mov.W	#__init_array_start,a0
-	mov.W	#__init_array_end,a1
-	jmp.w	_m32c_run_inilist
-
-	.global	_m32c_run_fini_array
-	.type	_m32c_run_fini_array,@function
-_m32c_run_fini_array:
-	mov.W	#__fini_array_start,a0
-	mov.W	#__fini_array_end,a1
-	/* fall through */
-
-_m32c_run_inilist:
-next_inilist:
-	cmp.W	a0,a1
-	jeq	done_inilist
-	pushm	a0,a1
-	mov.W	[a0],a0
-#ifdef A16
-	mov.b:s	#0,a1	/* zero extends */
-	jsri.a	a1a0
-#else
-	jsri.a	a0
-#endif
-	popm	a0,a1
-	add.W	A(#2,#4),a0
-	jmp.b	next_inilist
-done_inilist:
-	rts
-
-	.section	.init,"ax",@progbits
-
-	.global __init
-	.global __m32c_init
-__init:
-__m32c_init:
-	enter	#0
-	exitd
-
-	.section	.fini,"ax",@progbits
-
-	.global __fini
-	.global __m32c_fini
-__fini:
-__m32c_fini:
-	enter	#0
-	jsr.a	_m32c_run_fini_array
-	exitd
-
-
-;;; Provide Dwarf unwinding information that will help GDB stop
-;;; backtraces at the right place.  This is stolen from assembly
-;;; code generated by GCC with -dA.
-	.section	.debug_frame,"",@progbits
-.Lframe0:
-	.4byte	.LECIE0-.LSCIE0	; Length of Common Information Entry
-.LSCIE0:
-	.4byte	0xffffffff	; CIE Identifier Tag
-	.byte	0x1	; CIE Version
-	.ascii "\0"	; CIE Augmentation
-	.uleb128 0x1	; CIE Code Alignment Factor
-	.sleb128 -1	; CIE Data Alignment Factor
-	.byte	0xd	; CIE RA Column
-	.byte	0xc	; DW_CFA_def_cfa
-	.uleb128 0xc
-	.uleb128 0x3
-	.byte	0x8d	; DW_CFA_offset, column 0xd
-	.uleb128 0x3
-	.p2align ALIGN
-.LECIE0:
-.LSFDE0:
-	.4byte	.LEFDE0-.LASFDE0	; FDE Length
-.LASFDE0:
-	.4byte	.Lframe0	; FDE CIE offset
-	.4byte	.LFB2		; FDE initial location
-	.4byte	.LFE2-.LFB2	; FDE address range
-	.byte   0xf     	; DW_CFA_def_cfa_expression
-	.uleb128 1		; length of expression
-	.byte 	0x30		; DW_OP_lit0
-	.p2align ALIGN
-.LEFDE0:
-
-	.text
Index: c/src/aclocal/check-networking.m4
===================================================================
--- c/src/aclocal/check-networking.m4	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ c/src/aclocal/check-networking.m4	(revision bfcf1473cf117d039c76f1f10e40185cdc2f51ed)
@@ -10,5 +10,5 @@
     case "$RTEMS_CPU" in
     # do not have address space to hold BSD TCP/IP stack
-    epiphany* | m32c*)
+    epiphany*)
       rtems_cv_HAS_NETWORKING="no"
       ;;
Index: c/src/aclocal/rtems-cpu-subdirs.m4
===================================================================
--- c/src/aclocal/rtems-cpu-subdirs.m4	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ c/src/aclocal/rtems-cpu-subdirs.m4	(revision bfcf1473cf117d039c76f1f10e40185cdc2f51ed)
@@ -16,5 +16,4 @@
 _RTEMS_CPU_SUBDIR([i386],[$1]);;
 _RTEMS_CPU_SUBDIR([lm32],[$1]);;
-_RTEMS_CPU_SUBDIR([m32c],[$1]);;
 _RTEMS_CPU_SUBDIR([m68k],[$1]);;
 _RTEMS_CPU_SUBDIR([mips],[$1]);;
Index: src/lib/libbsp/m32c/Makefile.am
===================================================================
--- c/src/lib/libbsp/m32c/Makefile.am	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,7 +1,0 @@
-ACLOCAL_AMFLAGS = -I ../../../aclocal
-
-## Descend into the @RTEMS_BSP_FAMILY@ directory
-_SUBDIRS = @RTEMS_BSP_FAMILY@
-
-
-include $(top_srcdir)/../../../automake/subdirs.am
Index: src/lib/libbsp/m32c/acinclude.m4
===================================================================
--- c/src/lib/libbsp/m32c/acinclude.m4	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,10 +1,0 @@
-# RTEMS_CHECK_BSPDIR(RTEMS_BSP_FAMILY)
-AC_DEFUN([RTEMS_CHECK_BSPDIR],
-[
-  case "$1" in
-  m32cbsp )
-    AC_CONFIG_SUBDIRS([m32cbsp]);;
-  *)
-    AC_MSG_ERROR([Invalid BSP]);;
-  esac
-])
Index: src/lib/libbsp/m32c/configure.ac
===================================================================
--- c/src/lib/libbsp/m32c/configure.ac	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,21 +1,0 @@
-## Process this file with autoconf to produce a configure script.
-
-AC_PREREQ([2.69])
-AC_INIT([rtems-c-src-lib-libbsp-m32c],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
-RTEMS_TOP(../../../../..)
-RTEMS_SOURCE_TOP
-RTEMS_BUILD_TOP
-
-RTEMS_CANONICAL_TARGET_CPU
-AM_INIT_AUTOMAKE([no-define foreign subdir-objects 1.12.2])
-AM_MAINTAINER_MODE
-
-RTEMS_ENV_RTEMSBSP
-
-RTEMS_PROJECT_ROOT
-
-RTEMS_CHECK_BSPDIR([$RTEMS_BSP_FAMILY])
-
-# Explicitly list all Makefiles here
-AC_CONFIG_FILES([Makefile])
-AC_OUTPUT
Index: src/lib/libbsp/m32c/m32cbsp/Makefile.am
===================================================================
--- c/src/lib/libbsp/m32c/m32cbsp/Makefile.am	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,36 +1,0 @@
-ACLOCAL_AMFLAGS = -I ../../../../aclocal
-
-include $(top_srcdir)/../../../../automake/compile.am
-include $(top_srcdir)/../../bsp.am
-
-dist_project_lib_DATA = ../../../../../../bsps/m32c/m32cbsp/start/bsp_specs
-
-noinst_PROGRAMS =
-
-
-start.$(OBJEXT): ../../../../../../bsps/m32c/m32cbsp/start/start.S
-	$(CPPASCOMPILE) -o $@ -c $<
-project_lib_DATA = start.$(OBJEXT)
-
-project_lib_DATA += linkcmds
-
-project_lib_LIBRARIES = librtemsbsp.a
-librtemsbsp_a_SOURCES =
-librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/bspfatal-default.c
-librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/bspgetworkarea-default.c
-librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/bspreset-empty.c
-librtemsbsp_a_SOURCES += ../../../../../../bsps/m32c/m32cbsp/start/bspstart.c
-librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/sbrk.c
-librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/getentropy/getentropy-cpucounter.c
-librtemsbsp_a_SOURCES += ../../../../../../bsps/m32c/m32cbsp/start/crtn.S
-librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/clock/clock-simidle.c
-librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-polled.c
-librtemsbsp_a_SOURCES += ../../../../../../bsps/m32c/m32cbsp/console/console-io.c
-librtemsbsp_a_SOURCES += ../../../../../../bsps/m32c/m32cbsp/console/syscalls.S
-librtemsbsp_a_SOURCES += ../../../../../../bsps/m32c/m32cbsp/btimer/btimer.c
-
-# Cache
-librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-
-include $(srcdir)/../../../../../../bsps/shared/shared-sources.am
-include $(srcdir)/../../../../../../bsps/m32c/m32cbsp/headers.am
Index: src/lib/libbsp/m32c/m32cbsp/configure.ac
===================================================================
--- c/src/lib/libbsp/m32c/m32cbsp/configure.ac	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,19 +1,0 @@
-## Process this file with autoconf to produce a configure script.
-
-AC_PREREQ([2.69])
-AC_INIT([rtems-c-src-lib-libbsp-m32c-m32csim],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
-RTEMS_TOP(../../../../../..)
-RTEMS_SOURCE_TOP
-RTEMS_BUILD_TOP
-RTEMS_BSP_LINKCMDS
-
-RTEMS_CANONICAL_TARGET_CPU
-AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2])
-RTEMS_BSP_CONFIGURE
-
-
-RTEMS_BSP_CLEANUP_OPTIONS
-
-# Explicitly list all Makefiles here
-AC_CONFIG_FILES([Makefile])
-AC_OUTPUT
Index: cpukit/Makefile.am
===================================================================
--- cpukit/Makefile.am	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ cpukit/Makefile.am	(revision bfcf1473cf117d039c76f1f10e40185cdc2f51ed)
@@ -469,4 +469,6 @@
 librtemscpu_a_SOURCES += libmd/md4.c
 librtemscpu_a_SOURCES += libmd/md5.c
+librtemscpu_a_SOURCES += libmd/sha256c.c
+librtemscpu_a_SOURCES += libmd/sha512c.c
 librtemscpu_a_SOURCES += libstdthreads/call_once.c
 librtemscpu_a_SOURCES += libstdthreads/cnd.c
@@ -1501,11 +1503,4 @@
 endif
 
-if SHA
-
-librtemscpu_a_SOURCES += libmd/sha256c.c
-librtemscpu_a_SOURCES += libmd/sha512c.c
-
-endif
-
 if CPU_ARM
 
@@ -1594,18 +1589,4 @@
 endif
 
-if CPU_M32C
-
-include $(srcdir)/score/cpu/m32c/headers.am
-
-librtemscpu_a_SOURCES += score/cpu/m32c/context_init.c
-librtemscpu_a_SOURCES += score/cpu/m32c/context_switch.S
-librtemscpu_a_SOURCES += score/cpu/m32c/cpu.c
-librtemscpu_a_SOURCES += score/cpu/m32c/m32c-exception-frame-print.c
-librtemscpu_a_SOURCES += score/cpu/m32c/varvects.S
-librtemscpu_a_SOURCES += score/cpu/no_cpu/cpucounterfrequency.c
-librtemscpu_a_SOURCES += score/cpu/no_cpu/cpucounterread.c
-
-endif
-
 if CPU_M68K
 
Index: cpukit/aclocal/check-networking.m4
===================================================================
--- cpukit/aclocal/check-networking.m4	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ cpukit/aclocal/check-networking.m4	(revision bfcf1473cf117d039c76f1f10e40185cdc2f51ed)
@@ -11,5 +11,5 @@
     case "$host" in
     # do not have address space to hold BSD TCP/IP stack
-    epiphany* | m32c*)
+    epiphany*)
       rtems_cv_HAS_NETWORKING="no"
       ;;
Index: cpukit/configure.ac
===================================================================
--- cpukit/configure.ac	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ cpukit/configure.ac	(revision bfcf1473cf117d039c76f1f10e40185cdc2f51ed)
@@ -336,14 +336,4 @@
 AC_MSG_RESULT([$HAVE_LIBDEBUGGER])
 
-AC_MSG_CHECKING([whether CPU supports SHA])
-case $RTEMS_CPU in
-  m32c)
-   HAVE_SHA=no ;;
-  *)
-   HAVE_SHA=yes ;;
-esac
-AM_CONDITIONAL(SHA,[test x"$HAVE_SHA" = x"yes"])
-AC_MSG_RESULT([$HAVE_SHA])
-
 # Filter libpci to only build for architectures that have support for it
 AC_MSG_CHECKING([whether CPU supports libpci])
@@ -373,5 +363,4 @@
 AM_CONDITIONAL([CPU_I386],[test $RTEMS_CPU = "i386"])
 AM_CONDITIONAL([CPU_LM32],[test $RTEMS_CPU = "lm32"])
-AM_CONDITIONAL([CPU_M32C],[test $RTEMS_CPU = "m32c"])
 AM_CONDITIONAL([CPU_M68K],[test $RTEMS_CPU = "m68k"])
 AM_CONDITIONAL([CPU_MIPS],[test $RTEMS_CPU = "mips"])
Index: cpukit/libmisc/dummy/default-configuration.c
===================================================================
--- cpukit/libmisc/dummy/default-configuration.c	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ cpukit/libmisc/dummy/default-configuration.c	(revision bfcf1473cf117d039c76f1f10e40185cdc2f51ed)
@@ -91,12 +91,8 @@
 
 /* on smaller architectures lower the number or resources */
-#if defined(__m32c__)
-  #define CONFIGURE_MAXIMUM_TASKS 3
-#else
-  #define CONFIGURE_UNLIMITED_OBJECTS
-  #define CONFIGURE_MAXIMUM_USER_EXTENSIONS 8
-  #define CONFIGURE_MAXIMUM_DRIVERS 16
-  #define CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS 32
-#endif
+#define CONFIGURE_UNLIMITED_OBJECTS
+#define CONFIGURE_MAXIMUM_USER_EXTENSIONS 8
+#define CONFIGURE_MAXIMUM_DRIVERS 16
+#define CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS 32
 
 /* Include basic device drivers needed to call delays */
Index: ukit/score/cpu/m32c/context_init.c
===================================================================
--- cpukit/score/cpu/m32c/context_init.c	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,87 +1,0 @@
-/**
- *  @file
- *
- *  @brief Initialize Context Area
- *  @ingroup ScoreContext
- */
-
-/*
- *  COPYRIGHT (c) 1989-2008.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <stdint.h>
-#include <rtems/system.h>
-
-typedef struct {
-  uint16_t sbLow;
-  uint16_t sbHigh;       /* push/pop sb */
-  uint16_t flg;          /* push/pop flg */
-  uint32_t a1;           /* pushm */
-  uint32_t a0;
-  uint32_t r0r2;
-  uint32_t r1r3;
-  uint16_t frameLow;     /* exitd */
-  uint16_t frameHigh;
-  uint16_t startLow;
-  uint16_t startHigh;
-  uint16_t zero;
-} Starting_Frame;
-
-#if defined(__r8c_cpu__)
-  #warning "_get_sb: not implemented on R8C"
-  #define _get_sb( _sb )
-#else
-  #define _get_sb( _sb ) \
-    __asm__ volatile( "stc sb, %0" : "=r" (_sb))
-#endif
-
-void _CPU_Context_Initialize(
-  Context_Control  *the_context,
-  uint32_t         *stack_base,
-  size_t            size,
-  uint32_t          new_level,
-  void             *entry_point,
-  bool              is_fp,
-  void             *tls_area
-)
-{
-  void *stackEnd = stack_base;
-  register uint32_t sb;
-  Starting_Frame *frame;
-
-  _get_sb( sb );
-  stackEnd += size;
-
-  frame = (Starting_Frame *)stackEnd;
-  frame--;
-
-  frame->zero = 0;
-  frame->sbLow = ((uint32_t)sb) & 0xffff;
-  frame->sbHigh = ((uint32_t)sb >> 16) & 0xffff;
-  frame->flg = 0x80;        /* User stack */
-  if ( !new_level )         /* interrupt level 0 --> enabled */
-    frame->flg |= 0x40;
-  frame->a0 = 0x01020304;
-  frame->a1 =0xa1a2a3a4;
-  frame->r0r2 = 0;
-  frame->r1r3 = 0;
-#if defined(__r8c_cpu__)
-  #warning "not implemented on R8C"
-#else
-  frame->frameLow  = (uint16_t) (((uint32_t)frame)  & 0xffff);
-  frame->frameHigh = (uint16_t) (((uint32_t)frame >> 16) & 0xffff);
-  frame->startLow  = (uint16_t) (((uint32_t)entry_point) & 0xffff);
-  frame->startHigh = (uint16_t) (((uint32_t)entry_point >> 16) & 0xffff);
-#endif
-  the_context->sp = (uintptr_t)frame;
-  the_context->fb = (uintptr_t)&frame->frameLow;
-}
Index: ukit/score/cpu/m32c/context_switch.S
===================================================================
--- cpukit/score/cpu/m32c/context_switch.S	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,66 +1,0 @@
-/*
- *  Context switch for the Reneas M32C
- *
- *  COPYRIGHT (c) 1989-2008.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#define ARG_EXECUTING 8
-#define ARG_HEIR      12
-
-#define CTXT_SP  0
-#define CTXT_FB  4
-
-	.file	"context_switch.S"
-	.text
-	.global	__CPU_Context_switch
-	.type	__CPU_Context_switch, @function
-__CPU_Context_switch:
-	enter	#0
-	pushm 	a0,a1,r0,r1,r2,r3
-	pushc	flg
-	pushc	sb
-
-#if defined(__r8c_cpu__)
-  #warning "not implemented on R8C"
-#else
-	mov.l	ARG_EXECUTING[fb],a0	; a0 = executing
-	stc  	fb,a1
-	mov.l	a1,CTXT_FB[a0]		; save fb
-	stc  	sp,a1
-	mov.l	a1,CTXT_SP[a0]		; save sp
-
-	mov.l	ARG_HEIR[fb],a0		; a0 = heir
-
-restore:
-	mov.l	CTXT_SP[a0],a1
-	ldc  	a1,sp			; restore sp
-	mov.l	CTXT_FB[a0],a1
-	ldc  	a1,fb			; restore fb
-#endif
-	popc	sb
-	popc	flg
-	popm 	a0,a1,r0,r1,r2,r3
-	exitd
-	.size	__CPU_Context_switch, .-__CPU_Context_switch
-
-#define ARG_RESTART 8
-
-	.global	__CPU_Context_Restart_self
-	.type	__CPU_Context_Restart_self, @function
-__CPU_Context_Restart_self:
-	enter	#0
-#if defined(__r8c_cpu__)
-  #warning "__CPU_Context_Restart_self: not implemented on R8C"
-#else
-	mov.l	ARG_RESTART[fb],a0	; a0 = heir
-	jmp.s	restore
-#endif
Index: ukit/score/cpu/m32c/cpu.c
===================================================================
--- cpukit/score/cpu/m32c/cpu.c	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,140 +1,0 @@
-/**
- *  @file
- *
- *  @brief M32C CPU Dependent Source
- */
-
-/*
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <rtems/system.h>
-#include <rtems/score/isr.h>
-#include <varvects.h>
-
-/*  _CPU_Initialize
- *
- *  This routine performs processor dependent initialization.
- *
- *  INPUT PARAMETERS: NONE
- *
- *  NO_CPU Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-void _CPU_Initialize(void)
-{
-  #if !defined(__r8c_cpu__)
-    __asm__ volatile( "ldc    #__var_vects,intb" );
-  #endif
-}
-
-/*
- *  This routine returns the current interrupt level.
- *
- *  NO_CPU Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-uint32_t   _CPU_ISR_Get_level( void )
-{
-  int flag;
-  m32c_get_flg( flag );
-
-  return ((flag & 0x40) ? 0 : 1);
-}
-
-/*
- *  _CPU_ISR_install_raw_handler
- *
- *  NO_CPU Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-void _CPU_ISR_install_raw_handler(
-  uint32_t    vector,
-  proc_ptr    new_handler,
-  proc_ptr   *old_handler
-)
-{
-  /*
-   *  This is where we install the interrupt handler into the "raw" interrupt
-   *  table used by the CPU to dispatch interrupt handlers.
-   */
-#if defined(__r8c_cpu__)
-  #warning "_CPU_ISR_install_raw_handler not implemented on R8C"
-#else
-  _set_var_vect(new_handler,vector);
-#endif
-}
-
-/*
- *  _CPU_ISR_install_vector
- *
- *  NO_CPU Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-void _CPU_ISR_install_vector(
-  uint32_t    vector,
-  proc_ptr    new_handler,
-  proc_ptr   *old_handler
-)
-{
-   *old_handler = _ISR_Vector_table[ vector ];
-
-   /*
-    *  If the interrupt vector table is a table of pointer to isr entry
-    *  points, then we need to install the appropriate RTEMS interrupt
-    *  handler for this vector number.
-    */
-
-   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
-
-   /*
-    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
-    *  be used by the _ISR_Handler so the user gets control.
-    */
-
-    _ISR_Vector_table[ vector ] = new_handler;
-}
-
-/*
- *  _CPU_Thread_Idle_body
- *
- *  NOTES:
- *
- *  1. This is the same as the regular CPU independent algorithm.
- *
- *  2. If you implement this using a "halt", "idle", or "shutdown"
- *     instruction, then don't forget to put it in an infinite loop.
- *
- *  3. Be warned. Some processors with onboard DMA have been known
- *     to stop the DMA if the CPU were put in IDLE mode.  This might
- *     also be a problem with other on-chip peripherals.  So use this
- *     hook with caution.
- *
- *  NO_CPU Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-void *_CPU_Thread_Idle_body( uintptr_t ignored )
-{
-
-  for( ; ; )
-    /* insert your "halt" instruction here */ ;
-}
Index: ukit/score/cpu/m32c/headers.am
===================================================================
--- cpukit/score/cpu/m32c/headers.am	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,8 +1,0 @@
-## This file was generated by "./boostrap -H".
-include_HEADERS += score/cpu/m32c/include/varvects.h
-include_rtems_HEADERS += score/cpu/m32c/include/rtems/asm.h
-include_rtems_score_HEADERS += score/cpu/m32c/include/rtems/score/cpu.h
-include_rtems_score_HEADERS += score/cpu/m32c/include/rtems/score/cpu_asm.h
-include_rtems_score_HEADERS += score/cpu/m32c/include/rtems/score/cpuatomic.h
-include_rtems_score_HEADERS += score/cpu/m32c/include/rtems/score/cpuimpl.h
-include_rtems_score_HEADERS += score/cpu/m32c/include/rtems/score/m32c.h
Index: ukit/score/cpu/m32c/include/rtems/asm.h
===================================================================
--- cpukit/score/cpu/m32c/include/rtems/asm.h	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,124 +1,0 @@
-/**
- * @file
- * 
- * @brief Address the Problems Caused by Incompatible Flavor of 
- * Assemblers and Toolsets
- *
- * This include file attempts to address the problems
- * caused by incompatible flavors of assemblers and
- * toolsets.  It primarily addresses variations in the
- * use of leading underscores on symbols and the requirement
- * that register names be preceded by a %.
- * 
- * NOTE: The spacing in the use of these macros
- *       is critical to them working as advertised.
- */
-
-/*
- *  COPYRIGHT:
- *
- *  This file is based on similar code found in newlib available
- *  from ftp.cygnus.com.  The file which was used had no copyright
- *  notice.  This file is freely distributable as long as the source
- *  of the file is noted.  This file is:
- *
- *  COPYRIGHT (c) 1994-2006.
- *  On-Line Applications Research Corporation (OAR).
- */
-
-#ifndef _RTEMS_ASM_H
-#define _RTEMS_ASM_H
-
-/*
- *  Indicate we are in an assembly file and get the basic CPU definitions.
- */
-
-#ifndef ASM
-#define ASM
-#endif
-#include <rtems/score/cpuopts.h>
-#include <rtems/score/m32c.h>
-
-#ifndef __USER_LABEL_PREFIX__
-/**
- * Recent versions of GNU cpp define variables which indicate the
- * need for underscores and percents.  If not using GNU cpp or
- * the version does not support this, then you will obviously
- * have to define these as appropriate.
- *
- * This symbol is prefixed to all C program symbols.
- */
-#define __USER_LABEL_PREFIX__ _
-#endif
-
-#ifndef __REGISTER_PREFIX__
-/**
- * @see __USER_LABEL_PREFIX__
- *
- * This symbol is prefixed to all register names.
- */
-#define __REGISTER_PREFIX__
-#endif
-
-#include <rtems/concat.h>
-
-/** Use the right prefix for global labels.  */
-#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
-
-/** Use the right prefix for registers.  */
-#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
-
-/*
- *  define macros for all of the registers on this CPU
- *
- *  EXAMPLE:     #define d0 REG (d0)
- */
-
-/*
- *  Define macros to handle section beginning and ends.
- */
-
-
-/** This macro is used to denote the beginning of a code declaration. */
-#define BEGIN_CODE_DCL .text
-/** This macro is used to denote the end of a code declaration. */
-#define END_CODE_DCL
-/** 
- * This macro is used to denote the beginning of a data declaration section.
- */
-#define BEGIN_DATA_DCL .data
-/** This macro is used to denote the end of a data declaration section. */
-#define END_DATA_DCL
-/** This macro is used to denote the beginning of a code section. */
-#define BEGIN_CODE .text
-/** This macro is used to denote the end of a code section. */
-#define END_CODE
-/** This macro is used to denote the beginning of a data section. */
-#define BEGIN_DATA
-/** This macro is used to denote the end of a data section. */
-#define END_DATA
-/** This macro is used to denote the beginning of the
- *  unitialized data section.
- */
-#define BEGIN_BSS
-/** This macro is used to denote the end of the unitialized data section.  */
-#define END_BSS
-/** This macro is used to denote the end of the assembly file.  */
-#define END
-
-/**
- * This macro is used to declare a public global symbol.
- *
- * NOTE: This must be tailored for a particular flavor of the C compiler.
- * They may need to put underscores in front of the symbols.
- */
-#define PUBLIC(sym) .globl SYM (sym)
-
-/**
- * This macro is used to prototype a public global symbol.
- *
- * @see PUBLIC(sym) .globl SYM (sym)
- */
-#define EXTERN(sym) .globl SYM (sym)
-
-#endif
Index: ukit/score/cpu/m32c/include/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/m32c/include/rtems/score/cpu.h	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,833 +1,0 @@
-/**
- * @file
- * 
- * @brief M32C CPU Dependent Source
- */
-
-/*
- *  This include file contains information pertaining to the XXX
- *  processor.
- *
- *  @note This file is part of a porting template that is intended
- *  to be used as the starting point when porting RTEMS to a new
- *  CPU family.  The following needs to be done when using this as
- *  the starting point for a new port:
- *
- *  + Anywhere there is an XXX, it should be replaced
- *    with information about the CPU family being ported to.
- *
- *  + At the end of each comment section, there is a heading which
- *    says "Port Specific Information:".  When porting to RTEMS,
- *    add CPU family specific information in this section
- */
-
-/*
- *  COPYRIGHT (c) 1989-2008.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_CPU_H
-#define _RTEMS_SCORE_CPU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rtems/score/basedefs.h>
-#include <rtems/score/m32c.h>
-
-/* conditional compilation parameters */
-
-#define RTEMS_USE_16_BIT_OBJECT
-
-/**
- * Does the CPU follow the simple vectored interrupt model?
- *
- * If TRUE, then RTEMS allocates the vector table it internally manages.
- * If FALSE, then the BSP is assumed to allocate and manage the vector
- * table
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
-
-/**
- * Does the RTEMS invoke the user's ISR with the vector number and
- * a pointer to the saved interrupt frame (1) or just the vector
- * number (0)?
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_ISR_PASSES_FRAME_POINTER FALSE
-
-/**
- * @def CPU_HARDWARE_FP
- *
- * Does the CPU have hardware floating point?
- *
- * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
- * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
- *
- * If there is a FP coprocessor such as the i387 or mc68881, then
- * the answer is TRUE.
- *
- * The macro name "M32C_HAS_FPU" should be made CPU specific.
- * It indicates whether or not this CPU model has FP support.  For
- * example, it would be possible to have an i386_nofp CPU model
- * which set this to false to indicate that you have an i386 without
- * an i387 and wish to leave floating point support out of RTEMS.
- */
-
-/**
- * @def CPU_SOFTWARE_FP
- *
- * Does the CPU have no hardware floating point and GCC provides a
- * software floating point implementation which must be context
- * switched?
- *
- * This feature conditional is used to indicate whether or not there
- * is software implemented floating point that must be context
- * switched.  The determination of whether or not this applies
- * is very tool specific and the state saved/restored is also
- * compiler specific.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#if ( M32C_HAS_FPU == 1 )
-#define CPU_HARDWARE_FP     TRUE
-#else
-#define CPU_HARDWARE_FP     FALSE
-#endif
-#define CPU_SOFTWARE_FP     FALSE
-
-#define CPU_CONTEXT_FP_SIZE 0
-
-/**
- * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
- *
- * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
- * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
- *
- * So far, the only CPUs in which this option has been used are the
- * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
- * gcc both implicitly used the floating point registers to perform
- * integer multiplies.  Similarly, the PowerPC port of gcc has been
- * seen to allocate floating point local variables and touch the FPU
- * even when the flow through a subroutine (like vfprintf()) might
- * not use floating point formats.
- *
- * If a function which you would not think utilize the FP unit DOES,
- * then one can not easily predict which tasks will use the FP hardware.
- * In this case, this option should be TRUE.
- *
- * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_ALL_TASKS_ARE_FP     TRUE
-
-/**
- * Should the IDLE task have a floating point context?
- *
- * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
- * and it has a floating point context which is switched in and out.
- * If FALSE, then the IDLE task does not have a floating point context.
- *
- * Setting this to TRUE negatively impacts the time required to preempt
- * the IDLE task from an interrupt because the floating point context
- * must be saved as part of the preemption.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_IDLE_TASK_IS_FP      FALSE
-
-/**
- * Should the saving of the floating point registers be deferred
- * until a context switch is made to another different floating point
- * task?
- *
- * If TRUE, then the floating point context will not be stored until
- * necessary.  It will remain in the floating point registers and not
- * disturned until another floating point task is switched to.
- *
- * If FALSE, then the floating point context is saved when a floating
- * point task is switched out and restored when the next floating point
- * task is restored.  The state of the floating point registers between
- * those two operations is not specified.
- *
- * If the floating point context does NOT have to be saved as part of
- * interrupt dispatching, then it should be safe to set this to TRUE.
- *
- * Setting this flag to TRUE results in using a different algorithm
- * for deciding when to save and restore the floating point context.
- * The deferred FP switch algorithm minimizes the number of times
- * the FP context is saved and restored.  The FP context is not saved
- * until a context switch is made to another, different FP task.
- * Thus in a system with only one FP task, the FP context will never
- * be saved or restored.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
-
-#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
-
-/**
- * Does the stack grow up (toward higher addresses) or down
- * (toward lower addresses)?
- *
- * If TRUE, then the grows upward.
- * If FALSE, then the grows toward smaller addresses.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_STACK_GROWS_UP               TRUE
-
-/* FIXME: Is this the right value? */
-#define CPU_CACHE_LINE_BYTES 2
-
-#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
-
-/**
- * @ingroup CPUInterrupt
- * 
- * The following defines the number of bits actually used in the
- * interrupt field of the task mode.  How those bits map to the
- * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_MODES_INTERRUPT_MASK   0x00000001
-
-#define CPU_MAXIMUM_PROCESSORS 32
-
-/*
- *  Processor defined structures required for cpukit/score.
- *
- *  Port Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-/* may need to put some structures here.  */
-
-/**
- * @defgroup CPUContext Processor Dependent Context Management
- *
- * From the highest level viewpoint, there are 2 types of context to save.
- *
- *    -# Interrupt registers to save
- *    -# Task level registers to save
- *
- * Since RTEMS handles integer and floating point contexts separately, this
- * means we have the following 3 context items:
- *
- *    -# task level context stuff::  Context_Control
- *    -# floating point task stuff:: Context_Control_fp
- *    -# special interrupt level context :: CPU_Interrupt_frame
- *
- * On some processors, it is cost-effective to save only the callee
- * preserved registers during a task context switch.  This means
- * that the ISR code needs to save those registers which do not
- * persist across function calls.  It is not mandatory to make this
- * distinctions between the caller/callee saves registers for the
- * purpose of minimizing context saved during task switch and on interrupts.
- * If the cost of saving extra registers is minimal, simplicity is the
- * choice.  Save the same context on interrupt entry as for tasks in
- * this case.
- *
- * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
- * care should be used in designing the context area.
- *
- * On some CPUs with hardware floating point support, the Context_Control_fp
- * structure will not be used or it simply consist of an array of a
- * fixed number of bytes.   This is done when the floating point context
- * is dumped by a "FP save context" type instruction and the format
- * is not really defined by the CPU.  In this case, there is no need
- * to figure out the exact format -- only the size.  Of course, although
- * this is enough information for RTEMS, it is probably not enough for
- * a debugger such as gdb.  But that is another problem.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-/**@{**/
-
-/**
- * @ingroup Management
- * 
- * This defines the minimal set of integer and processor state registers
- * that must be saved during a voluntary context switch from one thread
- * to another.
- */
-typedef struct {
-  /** This will contain the stack pointer. */
-  uint32_t sp;
-  /** This will contain the frame base pointer. */
-  uint32_t fb;
-} Context_Control;
-
-/**
- * @ingroup Management
- *
- * This macro returns the stack pointer associated with @a _context.
- *
- * @param[in] _context is the thread context area to access
- *
- * @return This method returns the stack pointer.
- */
-#define _CPU_Context_Get_SP( _context ) \
-  (_context)->sp
-
-/**
- * @ingroup Management
- * 
- * This defines the set of integer and processor state registers that must
- * be saved during an interrupt.  This set does not include any which are
- * in @ref Context_Control.
- */
-typedef struct {
-    /** 
-     * This field is a hint that a port will have a number of integer
-     * registers that need to be saved when an interrupt occurs or
-     * when a context switch occurs at the end of an ISR.
-     */
-    uint32_t   special_interrupt_register;
-} CPU_Interrupt_frame;
-
-/** @} */
-
-/**
- * @defgroup CPUInterrupt Processor Dependent Interrupt Management
- */
-/**@{**/
-
-/*
- *  Nothing prevents the porter from declaring more CPU specific variables.
- *
- *  Port Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-/* XXX: if needed, put more variables here */
-
-/**
- * Amount of extra stack (above minimum stack size) required by
- * MPCI receive server thread.  Remember that in a multiprocessor
- * system this thread must exist and be able to process all directives.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
-
-/**
- * This defines the number of entries in the @ref _ISR_Vector_table managed
- * by RTEMS.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
-
-/** This defines the highest interrupt vector number for this port. */
-#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
-
-/**
- * This is defined if the port has a special way to report the ISR nesting
- * level.  Most ports maintain the variable @a _ISR_Nest_level.
- */
-#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
-
-/** @} */
-
-/**
- * @ingroup CPUContext
- * 
- * Should be large enough to run all RTEMS tests.  This ensures
- * that a "reasonable" small application should not have any problems.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_STACK_MINIMUM_SIZE          (2048L)
-
-#ifdef __m32cm_cpu__
-  #define CPU_SIZEOF_POINTER 4
-#else
-  #define CPU_SIZEOF_POINTER 2
-#endif
-
-/**
- * CPU's worst alignment requirement for data types on a byte boundary.  This
- * alignment does not take into account the requirements for the stack.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_ALIGNMENT              2
-
-/**
- * This number corresponds to the byte alignment requirement for the
- * heap handler.  This alignment requirement may be stricter than that
- * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
- * common for the heap to follow the same alignment requirement as
- * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
- * the heap, then this should be set to @ref CPU_ALIGNMENT.
- *
- * NOTE:  This does not have to be a power of 2 although it should be
- *        a multiple of 2 greater than or equal to 2.  The requirement
- *        to be a multiple of 2 is because the heap uses the least
- *        significant field of the front and back flags to indicate
- *        that a block is in use or free.  So you do not want any odd
- *        length blocks really putting length data in that bit.
- *
- *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
- *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
- *        elements allocated from the heap meet all restrictions.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_HEAP_ALIGNMENT         4
-
-/**
- * This number corresponds to the byte alignment requirement for the
- * stack.  This alignment requirement may be stricter than that for the
- * data types alignment specified by @ref CPU_ALIGNMENT.  If the
- * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
- * set to 0.
- *
- * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define CPU_STACK_ALIGNMENT        0
-
-#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
-
-/*
- *  ISR handler macros
- */
-
-/**
- * @ingroup CPUInterrupt
- * 
- * Support routine to initialize the RTEMS vector table after it is allocated.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define _CPU_Initialize_vectors()
-
-/**
- * @ingroup CPUInterrupt
- * 
- * Disable all interrupts for an RTEMS critical section.  The previous
- * level is returned in @a _isr_cookie.
- *
- * @param[out] _isr_cookie will contain the previous level cookie
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define _CPU_ISR_Disable( _isr_cookie ) \
-  do { \
-    int _flg; \
-    m32c_get_flg( _flg ); \
-    _isr_cookie = _flg; \
-    __asm__ volatile( "fclr I" ); \
-  } while(0)
-
-/**
- * @ingroup CPUInterrupt
- * 
- * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
- * This indicates the end of an RTEMS critical section.  The parameter
- * @a _isr_cookie is not modified.
- *
- * @param[in] _isr_cookie contain the previous level cookie
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define _CPU_ISR_Enable(_isr_cookie) \
-  do { \
-    int _flg = (int) (_isr_cookie); \
-    m32c_set_flg( _flg ); \
-  } while(0)
-
-/**
- * @ingroup CPUInterrupt
- * 
- * This temporarily restores the interrupt to @a _isr_cookie before immediately
- * disabling them again.  This is used to divide long RTEMS critical
- * sections into two or more parts.  The parameter @a _isr_cookie is not
- * modified.
- *
- * @param[in] _isr_cookie contain the previous level cookie
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define _CPU_ISR_Flash( _isr_cookie ) \
-  do { \
-    int _flg = (int) (_isr_cookie); \
-    m32c_set_flg( _flg ); \
-    __asm__ volatile( "fclr I" ); \
-  } while(0)
-
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
-{
-  return ( level & 0x40 ) != 0;
-}
-
-/**
- * @ingroup CPUInterrupt
- *
- * This routine and @ref _CPU_ISR_Get_level
- * Map the interrupt level in task mode onto the hardware that the CPU
- * actually provides.  Currently, interrupt levels which do not
- * map onto the CPU in a generic fashion are undefined.  Someday,
- * it would be nice if these were "mapped" by the application
- * via a callout.  For example, m68k has 8 levels 0 - 7, levels
- * 8 - 255 would be available for bsp/application specific meaning.
- *This could be used to manage a programmable interrupt controller
- * via the rtems_task_mode directive.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define _CPU_ISR_Set_level( _new_level ) \
-  do { \
-    if (_new_level) __asm__ volatile( "fclr I" ); \
-    else            __asm__ volatile( "fset I" ); \
-  } while(0)
-
-/**
- * @ingroup CPUInterrupt
- * 
- * Return the current interrupt disable level for this task in
- * the format used by the interrupt level portion of the task mode.
- *
- * NOTE: This routine usually must be implemented as a subroutine.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-uint32_t   _CPU_ISR_Get_level( void );
-
-/* end of ISR handler macros */
-
-/* Context handler macros */
-
-/**
- * @ingroup CPUContext
- * 
- * Initialize the context to a state suitable for starting a
- * task after a context restore operation.  Generally, this
- * involves:
- *
- *    - setting a starting address
- *    - preparing the stack
- *    - preparing the stack and frame pointers
- *    - setting the proper interrupt level in the context
- *    - initializing the floating point context
- *
- * This routine generally does not set any unnecessary register
- * in the context.  The state of the "general data" registers is
- * undefined at task start time.
- *
- * @param[in] _the_context is the context structure to be initialized
- * @param[in] _stack_base is the lowest physical address of this task's stack
- * @param[in] _size is the size of this task's stack
- * @param[in] _isr is the interrupt disable level
- * @param[in] _entry_point is the thread's entry point.  This is
- *        always @a _Thread_Handler
- * @param[in] _is_fp is TRUE if the thread is to be a floating
- *       point thread.  This is typically only used on CPUs where the
- *       FPU may be easily disabled by software such as on the SPARC
- *       where the PSR contains an enable FPU bit.
- * @param[in] tls_area is the thread-local storage (TLS) area
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-void _CPU_Context_Initialize(
-  Context_Control  *the_context,
-  uint32_t         *stack_base,
-  size_t            size,
-  uint32_t          new_level,
-  void             *entry_point,
-  bool              is_fp,
-  void             *tls_area
-);
-
-/**
- * This routine is responsible for somehow restarting the currently
- * executing task.  If you are lucky, then all that is necessary
- * is restoring the context.  Otherwise, there will need to be
- * a special assembly routine which does something special in this
- * case.  For many ports, simply adding a label to the restore path
- * of @ref _CPU_Context_switch will work.  On other ports, it may be
- * possibly to load a few arguments and jump to the restore path. It will
- * not work if restarting self conflicts with the stack frame
- * assumptions of restoring a context.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-void _CPU_Context_Restart_self(
-  Context_Control  *the_context
-) RTEMS_NO_RETURN;
-
-/**
- * This routine initializes the FP context area passed to it to.
- * There are a few standard ways in which to initialize the
- * floating point context.  The code included for this macro assumes
- * that this is a CPU in which a "initial" FP context was saved into
- * @a _CPU_Null_fp_context and it simply copies it to the destination
- * context passed to it.
- *
- * Other floating point context save/restore models include:
- *   -# not doing anything, and
- *   -# putting a "null FP status word" in the correct place in the FP context.
- *
- * @param[in] _destination is the floating point context area
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define _CPU_Context_Initialize_fp( _destination ) \
-  { \
-   *(*(_destination)) = _CPU_Null_fp_context; \
-  }
-
-/* end of Context handler macros */
-
-/* Fatal Error manager macros */
-
-/**
- * This routine copies _error into a known place -- typically a stack
- * location or a register, optionally disables interrupts, and
- * halts/stops the CPU.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define _CPU_Fatal_halt( _source, _error ) \
-  { \
-  }
-
-/* end of Fatal Error manager macros */
-
-#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
-
-/* functions */
-
-/**
- * This routine performs CPU dependent initialization.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-void _CPU_Initialize(void);
-
-/**
- * @ingroup CPUInterrupt
- *
- * This routine installs a "raw" interrupt handler directly into the
- * processor's vector table.
- *
- * @param[in] vector is the vector number
- * @param[in] new_handler is the raw ISR handler to install
- * @param[in] old_handler is the previously installed ISR Handler
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-void _CPU_ISR_install_raw_handler(
-  uint32_t    vector,
-  proc_ptr    new_handler,
-  proc_ptr   *old_handler
-);
-
-/**
- * @ingroup CPUInterrupt
- * 
- * This routine installs an interrupt vector.
- *
- * @param[in] vector is the vector number
- * @param[in] new_handler is the RTEMS ISR handler to install
- * @param[in] old_handler is the previously installed ISR Handler
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-void _CPU_ISR_install_vector(
-  uint32_t    vector,
-  proc_ptr    new_handler,
-  proc_ptr   *old_handler
-);
-
-void *_CPU_Thread_Idle_body( uintptr_t ignored );
-
-/**
- * @ingroup CPUContext
- * 
- * This routine switches from the run context to the heir context.
- *
- * @param[in] run points to the context of the currently executing task
- * @param[in] heir points to the context of the heir task
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-void _CPU_Context_switch(
-  Context_Control  *run,
-  Context_Control  *heir
-);
-
-/**
- * @ingroup CPUContext
- * 
- * This routine is generally used only to restart self in an
- * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
- *
- * @param[in] new_context points to the context to be restored.
- *
- * NOTE: May be unnecessary to reload some registers.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-void _CPU_Context_restore(
-  Context_Control *new_context
-) RTEMS_NO_RETURN;
-
-/* FIXME */
-typedef CPU_Interrupt_frame CPU_Exception_frame;
-
-void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
-
-/**
- * @ingroup CPUEndian
- * 
- * The following routine swaps the endian format of an unsigned int.
- * It must be static because it is referenced indirectly.
- *
- * This version will work on any processor, but if there is a better
- * way for your CPU PLEASE use it.  The most common way to do this is to:
- *
- *    swap least significant two bytes with 16-bit rotate
- *    swap upper and lower 16-bits
- *    swap most significant two bytes with 16-bit rotate
- *
- * Some CPUs have special instructions which swap a 32-bit quantity in
- * a single instruction (e.g. i486).  It is probably best to avoid
- * an "endian swapping control bit" in the CPU.  One good reason is
- * that interrupts would probably have to be disabled to ensure that
- * an interrupt does not try to access the same "chunk" with the wrong
- * endian.  Another good reason is that on some CPUs, the endian bit
- * endianness for ALL fetches -- both code and data -- so the code
- * will be fetched incorrectly.
- *
- * @param[in] value is the value to be swapped
- * @return the value after being endian swapped
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-static inline uint32_t CPU_swap_u32(
-  uint32_t value
-)
-{
-  uint32_t byte1, byte2, byte3, byte4, swapped;
-
-  byte4 = (value >> 24) & 0xff;
-  byte3 = (value >> 16) & 0xff;
-  byte2 = (value >> 8)  & 0xff;
-  byte1 =  value        & 0xff;
-
-  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
-  return swapped;
-}
-
-/**
- * @ingroup CPUEndian
- * 
- * This routine swaps a 16 bir quantity.
- *
- * @param[in] value is the value to be swapped
- * @return the value after being endian swapped
- */
-#define CPU_swap_u16( value ) \
-  (((value&0xff) << 8) | ((value >> 8)&0xff))
-
-typedef uint32_t CPU_Counter_ticks;
-
-uint32_t _CPU_Counter_frequency( void );
-
-CPU_Counter_ticks _CPU_Counter_read( void );
-
-static inline CPU_Counter_ticks _CPU_Counter_difference(
-  CPU_Counter_ticks second,
-  CPU_Counter_ticks first
-)
-{
-  return second - first;
-}
-
-/** Type that can store a 32-bit integer or a pointer. */
-typedef unsigned long CPU_Uint32ptr;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
Index: ukit/score/cpu/m32c/include/rtems/score/cpu_asm.h
===================================================================
--- cpukit/score/cpu/m32c/include/rtems/score/cpu_asm.h	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,72 +1,0 @@
-/**
- * @file
- * 
- * @brief M32C CPU Assembly File
- * 
- * Very loose template for an include file for the cpu_asm.? file
- * if it is implemented as a ".S" file (preprocessed by cpp) instead
- * of a ".s" file (preprocessed by gm4 or gasp).
- */
-
-/*
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- *
- */
-
-#ifndef _RTEMS_SCORE_CPU_ASM_H
-#define _RTEMS_SCORE_CPU_ASM_H
-
-/* pull in the generated offsets */
-
-#include <rtems/score/offsets.h>
-
-/*
- * Hardware General Registers
- */
-
-/* put something here */
-
-/*
- * Hardware Floating Point Registers
- */
-
-/* put something here */
-
-/*
- * Hardware Control Registers
- */
-
-/* put something here */
-
-/*
- * Calling Convention
- */
-
-/* put something here */
-
-/*
- * Temporary registers
- */
-
-/* put something here */
-
-/*
- * Floating Point Registers - SW Conventions
- */
-
-/* put something here */
-
-/*
- * Temporary floating point registers
- */
-
-/* put something here */
-
-#endif
-
-/* end of file */
Index: ukit/score/cpu/m32c/include/rtems/score/cpuatomic.h
===================================================================
--- cpukit/score/cpu/m32c/include/rtems/score/cpuatomic.h	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,14 +1,0 @@
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
Index: ukit/score/cpu/m32c/include/rtems/score/cpuimpl.h
===================================================================
--- cpukit/score/cpu/m32c/include/rtems/score/cpuimpl.h	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,56 +1,0 @@
-/**
- * @file
- *
- * @brief CPU Port Implementation API
- */
-
-/*
- * Copyright (c) 2013 embedded brains GmbH
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_CPUIMPL_H
-#define _RTEMS_SCORE_CPUIMPL_H
-
-#include <rtems/score/cpu.h>
-
-#define CPU_PER_CPU_CONTROL_SIZE 0
-
-#ifndef ASM
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern )
-{
-  /* TODO */
-}
-
-RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern )
-{
-  while (1) {
-    /* TODO */
-  }
-}
-
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
-{
-  __asm__ volatile ( ".word 0" );
-}
-
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
-{
-  __asm__ volatile ( "nop" );
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ASM */
-
-#endif /* _RTEMS_SCORE_CPUIMPL_H */
Index: ukit/score/cpu/m32c/include/rtems/score/m32c.h
===================================================================
--- cpukit/score/cpu/m32c/include/rtems/score/m32c.h	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,76 +1,0 @@
-/**
- * @file
- *
- * @brief M32C Set up Basic CPU Dependency Settings Based on Compiler Settings
- *
- * This file sets up basic CPU dependency settings based on
- * compiler settings.  For example, it can determine if
- * floating point is available.  This particular implementation
- * is specified to the NO CPU port.
- */
-
-/*
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_NO_CPU_H
-#define _RTEMS_SCORE_NO_CPU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- *  This file contains the information required to build
- *  RTEMS for a particular member of the NO CPU family.
- *  It does this by setting variables to indicate which
- *  implementation dependent features are present in a particular
- *  member of the family.
- *
- *  This is a good place to list all the known CPU models
- *  that this port supports and which RTEMS CPU model they correspond
- *  to.
- */
-
-#if defined(rtems_multilib)
-/*
- *  Figure out all CPU Model Feature Flags based upon compiler
- *  predefines.
- */
-
-#define CPU_MODEL_NAME  "rtems_multilib"
-#define NOCPU_HAS_FPU     1
-
-#elif defined(__m32c__)
-
-#define CPU_MODEL_NAME  "m32c"
-#define M32C_HAS_FPU    0
-
-#else
-
-#error "Unsupported CPU Model"
-
-#endif
-
-/*
- *  Define the name of the CPU family.
- */
-
-#define CPU_NAME "m32c"
-
-#define m32c_get_flg( _flg ) \
-  __asm__ volatile( "stc flg, %0" : "=r" (_flg))
-
-#define m32c_set_flg( _flg ) \
-  __asm__ volatile( "ldc %1, flg" : "=r" (_flg) : "r" (_flg) )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _RTEMS_SCORE_NO_CPU_H */
Index: ukit/score/cpu/m32c/include/varvects.h
===================================================================
--- cpukit/score/cpu/m32c/include/varvects.h	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,58 +1,0 @@
-/**
- * @file
- *
- * @brief M32C Built-in Variable Vector Table Interface
- *
- * This file defines the interface to the built-in variable vector
- * table in R8C/M16C/M32C chips.
- */
-
-/*
- * Copyright (c) 2008 Red Hat Incorporated.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *     Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *     Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *
- *     The name of Red Hat Incorporated may not be used to endorse
- *     or promote products derived from this software without specific
- *     prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _VARVECTS_H_
-#define _VARVECTS_H_
-
-typedef void (*_m32c_interrupt_func)(void) __attribute__((mode(SI)));
-extern _m32c_interrupt_func _var_vects[];
-
-#if defined(__r8c_cpu__) || defined (__m16c_cpu__)
-
-#define _set_var_vect(f,n) \
-  { __asm__ ("mov.w #%%lo16(%d0),__var_vects+%d1" : : "s" (f), "g" (n*4));	\
-    __asm__ ("mov.w #%%hi16(%d0),__var_vects+%d1" : : "s" (f), "g" (n*4+2)); }
-
-#else
-
-#define _set_var_vect(f,n) \
-  _var_vects[n] = f
-
-#endif
-#endif
Index: ukit/score/cpu/m32c/m32c-exception-frame-print.c
===================================================================
--- cpukit/score/cpu/m32c/m32c-exception-frame-print.c	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,24 +1,0 @@
-/*
- * Copyright (c) 2012 embedded brains GmbH.  All rights reserved.
- *
- *  embedded brains GmbH
- *  Obere Lagerstr. 30
- *  82178 Puchheim
- *  Germany
- *  <rtems@embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifdef HAVE_CONFIG_H
-  #include "config.h"
-#endif
-
-#include <rtems/score/cpu.h>
-
-void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
-{
-  /* TODO */
-}
Index: ukit/score/cpu/m32c/varvects.S
===================================================================
--- cpukit/score/cpu/m32c/varvects.S	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ 	(revision )
@@ -1,47 +1,0 @@
-/*
-
-Copyright (c) 2008 Red Hat Incorporated.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-    Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-
-    Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-
-    The name of Red Hat Incorporated may not be used to endorse
-    or promote products derived from this software without specific
-    prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*/
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-/* This works with varvects.h
-*/
-
-	.section ".var_vects","aw",@progbits
-	.global	__var_vects
-	.type	__var_vects,@object
-	.size	__var_vects, 256
-__var_vects:
-	.zero	256
-
-	.text
Index: testsuites/sptests/sptask_err03/init.c
===================================================================
--- testsuites/sptests/sptask_err03/init.c	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ testsuites/sptests/sptask_err03/init.c	(revision bfcf1473cf117d039c76f1f10e40185cdc2f51ed)
@@ -74,7 +74,4 @@
    * If the bsp provides its own stack allocator, then
    * skip the test that tries to allocate a stack that is too big.
-   *
-   * If on the m32c, we can't even ask for enough memory to trip this
-   * error.
    */
 
@@ -82,7 +79,4 @@
   if (rtems_configuration_get_stack_allocate_hook())
     skipUnsatisfied = true;
-  #if defined(__m32c__)
-    skipUnsatisfied = true;
-  #endif
 
   if ( skipUnsatisfied ) {
Index: testsuites/sptests/sptimer_err02/init.c
===================================================================
--- testsuites/sptests/sptimer_err02/init.c	(revision 7ea717815f1ed67cb1757457079fd954c0f9a0b7)
+++ testsuites/sptests/sptimer_err02/init.c	(revision bfcf1473cf117d039c76f1f10e40185cdc2f51ed)
@@ -34,5 +34,4 @@
   rtems_id                 timer_id;
   rtems_name               timer_name;
-  bool                     skipUnsatisfied;
 
   /* Set System time */
@@ -75,23 +74,15 @@
   puts( "TA1 - rtems_timer_initiate_server - RTEMS_INVALID_PRIORITY" );
 
-  skipUnsatisfied = false;
-  #if defined(__m32c__)
-    skipUnsatisfied = true;
-  #endif
-  if (skipUnsatisfied) {
-    puts( "TA1 - rtems_timer_initiate_server - RTEMS_UNSATISFIED -- SKIPPED" );
-  } else {
-    status = rtems_timer_initiate_server(
-      RTEMS_TIMER_SERVER_DEFAULT_PRIORITY,
-      0x10000000,
-      0
-    );
-    fatal_directive_status(
-      status,
-      RTEMS_UNSATISFIED,
-      "rtems_timer_initiate_server too much stack "
-    );
-    puts( "TA1 - rtems_timer_initiate_server - RTEMS_UNSATISFIED" );
-  }
+  status = rtems_timer_initiate_server(
+    RTEMS_TIMER_SERVER_DEFAULT_PRIORITY,
+    0x10000000,
+    0
+  );
+  fatal_directive_status(
+    status,
+    RTEMS_UNSATISFIED,
+    "rtems_timer_initiate_server too much stack "
+  );
+  puts( "TA1 - rtems_timer_initiate_server - RTEMS_UNSATISFIED" );
 
   status =
