Changeset bf27a21 in rtems-docs

02/22/22 14:42:47 (8 months ago)
Alex White <alex.white@…>
Alex White <alex.white@…> (02/22/22 14:42:47)
Joel Sherrill <joel@…> (03/23/22 19:26:40)

microblaze: Document BSPs and update CPU supplement

2 edited


  • cpu-supplement/xilinx_microblaze.rst

    r49f84b7 rbf27a21  
    11.. SPDX-License-Identifier: CC-BY-SA-4.0
    3 .. Copyright (C) 1988, 2002 On-Line Applications Research Corporation (OAR)
     3.. Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
    55Xilinx MicroBlaze Specific Information
     8This chapter discusses the dependencies of the *MicroBlaze architecture*
     11**Architecture Documents**
     13For information on the MicroBlaze architecture, refer to
     14*UG984 MicroBlaze Processor Reference Guide*
     17CPU Model Dependent Features
     20There are no CPU model dependent features in this port.
     22Calling Conventions
     25Please refer to "Chapter 4: MicroBlaze Application Binary Interface" of
     26*UG984 MicroBlaze Processor Reference Guide*
     29Interrupt Processing
     32Hardware exceptions, interrupts, and user exceptions are all supported. When a
     33hardware exception or user exception occurs, a fatal error will be generated.
     34When an interrupt occurs, the interrupt source is determined by reading the
     35AXI Interrupt Controller's Interrupt Status Register and masking it with the
     36Interrupt Enable Register.
     38Interrupt Levels
     41There are exactly two interrupt levels on MicroBlaze with respect to RTEMS.
     42Level zero corresponds to interrupts disabled. Level one corresponds to
     43interrupts enabled. This is the inverse of how most other architectures handle
     44interrupt enable status.
     46Interrupt Stack
     49The memory region for the interrupt stack is defined by the BSP.
     51Default Fatal Error Processing
     54The default fatal error is BSP-specific.
    856Symmetric Multiprocessing
    16 Thread-local storage is not implemented.
     64Thread-local storage is supported.
  • user/bsps/bsps-microblaze.rst

    r49f84b7 rbf27a21  
    33.. Copyright (C) 2018 embedded brains GmbH
     4.. Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
    5 microblaze (Microblaze)
     6microblaze (MicroBlaze)
    8 There are no Microblaze BSPs yet.
     9KCU105 QEMU
     12The basic hardware initialization is performed by the BSP. This BSP supports the
     13QEMU emulated Xilinx AXI Interrupt Controller v4.1.
     15Boot via ELF
     18The executable image is booted by QEMU in ELF format.
     20Clock Driver
     23The clock driver supports the QEMU emulated Xilinx AXI Timer v2.0. It is
     24implemented as a simple downcounter.
     26Console Driver
     29The console driver supports the QEMU emulated Xilinx AXI UART Lite v2.0. It is
     30initialized to a baud rate of 115200.
     32Network Driver
     35Support for networking is provided by the libbsd library. Network interface
     36configuration is extracted from the device tree binary which, by default, is
     37in `<bsp/microblaze-dtb.h> <>`_.
     38The device tree source for the default device tree is at `dts/system.dts <>`_.
     40To replace the default device tree with your own, assuming ``my_device_tree.dts``
     41is the name of your device tree source file, first you must convert your device
     42tree to .dtb format.
     44.. code-block:: none
     46  $ dtc -I dts -O dtb my_device_tree.dts > my_device_tree.dtb
     48The device tree blob, ``my_device_tree.dtb``, can now be converted to a C file.
     49The name ``system_dtb`` is significant as it is the name expected by the BSP.
     51.. code-block:: none
     53  $ rtems-bin2c -C -A 8 -N system_dtb my_device_tree.dtb my_dtb
     55The ``BSP_MICROBLAZE_FPGA_DTB_HEADER_PATH`` BSP configuration option can then be
     56set to the path of the resulting source file, ``my_dtb.c``, to include it in the
     57BSP build.
     59.. code-block:: none
     61  BSP_MICROBLAZE_FPGA_DTB_HEADER_PATH = /path/to/my_dtb.c
     64Running Executables
     67A .dtb (device tree blob) file should be provided to QEMU via the ``-hw-dtb``
     68option. In the example command below, the device tree blob comes from the Xilinx
     69Petalinux KCU105 MicroBlaze BSP (
     71Executables generated by this BSP can be run using the following command:
     73.. code-block:: none
     75  $ qemu-system-microblazeel -no-reboot -nographic -M microblaze-fdt-plnx -m 256 \
     76   -serial mon:stdio -display none -hw-dtb system.dtb -kernel example.exe
     78Debugging with QEMU
     81To debug an application, add the option ``-s`` to make QEMU listen for GDB
     82connections on port 1234. Add the ``-S`` option to also stop execution until
     83a connection is made.
     85For example, to debug the hello sample and break at ``Init``, first start QEMU.
     87.. code-block:: none
     89  $ qemu-system-microblazeel -no-reboot -nographic -M microblaze-fdt-plnx -m 256 \
     90   -serial mon:stdio -display none -hw-dtb system.dtb -kernel \
     91   build/microblaze/kcu105_qemu/testsuites/samples/hello.exe -s -S
     93Then start GDB and connect to QEMU.
     95.. code-block:: none
     97  $ microblaze-rtems6-gdb build/microblaze/kcu105_qemu/testsuites/samples/hello.exe
     98  (gdb) target remote localhost:1234
     99  (gdb) break Init
     100  (gdb) continue
     105The basic hardware initialization is performed by the BSP. This BSP supports the
     106Xilinx AXI Interrupt Controller v4.1.
     108This BSP was tested using the Xilinx Kintex UltraScale FPGA KCU105 board
     109configured with the default Petalinux KCU105 MicroBlaze BSP. The defaults may
     110need to be adjusted using BSP configuration options to match the memory layout
     111and configuration of your board.
     113Clock Driver
     116The clock driver supports the Xilinx AXI Timer v2.0. It is implemented as a
     117simple downcounter.
     119Console Driver
     122The console driver supports the Xilinx AXI UART Lite v2.0.
     127The following debugging procedure was used for debugging RTEMS applications
     128running on the Xilinx KCU105 board using GDB.
     130First send an FPGA bitstream to the board using OpenOCD.
     132.. code-block:: none
     134  $ openocd -f board/kcu105.cfg -c "init; pld load 0 system.bit; exit"
     136After the board has been programmed, start the Vivado ``hw_server`` application
     137to serve as the debug server. Leave it running in the background for the rest of
     138the process.
     140.. code-block:: none
     142  $ tools/Xilinx/Vivado/2020.2/bin/hw_server
     144With the debug server running, connect to the debug server with GDB, load the
     145application, and debug as usual. By default the GDB server listens on port 3002.
     147.. code-block:: none
     149  $ microblaze-rtems6-gdb example.exe
     150  (gdb) target extended-remote localhost:3002
     151  (gdb) load
     152  (gdb) break Init
     153  (gdb) continue
Note: See TracChangeset for help on using the changeset viewer.