Changeset beb289e in rtems


Ignore:
Timestamp:
Aug 19, 2016, 9:59:12 AM (3 years ago)
Author:
Christian Mauderer <Christian.Mauderer@…>
Branches:
master
Children:
b9cc5aa
Parents:
29594b4
git-author:
Christian Mauderer <Christian.Mauderer@…> (08/19/16 09:59:12)
git-committer:
Sebastian Huber <sebastian.huber@…> (09/07/16 11:38:53)
Message:

bsp/atsam: Move ram init values to structure.

Location:
c/src/lib/libbsp/arm/atsam
Files:
1 added
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/atsam/Makefile.am

    r29594b4 rbeb289e  
    399399libbsp_a_SOURCES += startup/power-rtc.c
    400400libbsp_a_SOURCES += startup/power-clock.c
     401libbsp_a_SOURCES += startup/sdram-config.c
    401402
    402403# IRQ
  • c/src/lib/libbsp/arm/atsam/libraries/libboard/include/board_memories.h

    r29594b4 rbeb289e  
    4444extern void BOARD_ConfigureSdram(void);
    4545extern uint32_t BOARD_SdramValidation(uint32_t baseAddr, uint32_t size);
     46#ifdef __rtems__
     47struct BOARD_Sdram_Config {
     48  uint32_t sdramc_tr;
     49  uint32_t sdramc_cr;
     50  uint32_t sdramc_mdr;
     51  uint32_t sdramc_cfr1;
     52};
     53
     54extern const struct BOARD_Sdram_Config BOARD_Sdram_Config;
     55#endif /* __rtems__ */
    4656
    4757#endif /* #ifndef BOARD_MEMORIES_H */
  • c/src/lib/libbsp/arm/atsam/libraries/libboard/source/board_memories.c

    r29594b4 rbeb289e  
    168168        asynchronous timings (TRC, TRAS, etc.), number of columns, rows,
    169169        CAS latency, and the data bus width. */
     170#ifndef __rtems__
    170171        SDRAMC->SDRAMC_CR =
    171172                SDRAMC_CR_NC_COL8      // 8 column bits
     
    181182                | SDRAMC_CR_TRAS(9)      // Command period (ACT to PRE)  42ns min
    182183                | SDRAMC_CR_TXSR(15U);   // Exit self-refresh to active time  70ns Min
     184#else /* __rtems__ */
     185        SDRAMC->SDRAMC_CR = BOARD_Sdram_Config.sdramc_cr;
     186#endif /* __rtems__ */
    183187
    184188        /* 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive
     
    187191
    188192        /* 3. The SDRAM memory type must be set in the Memory Device Register.*/
     193#ifndef __rtems__
    189194        SDRAMC->SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM;
     195#else /* __rtems__ */
     196        SDRAMC->SDRAMC_MDR = BOARD_Sdram_Config.sdramc_mdr;
     197#endif /* __rtems__ */
    190198
    191199        /* 4. A minimum pause of 200 ŠÌs is provided to precede any signal toggle.*/
     
    255263        // For IS42S16100E, 2048 refresh cycle every 32ms, every 15.625 ŠÌs
    256264        /* ((32 x 10(^-3))/2048) x150 x (10^6) */
     265#ifndef __rtems__
    257266        SDRAMC->SDRAMC_TR = 1562;
    258267        SDRAMC->SDRAMC_CFR1 |= SDRAMC_CFR1_UNAL;
     268#else /* __rtems__ */
     269        SDRAMC->SDRAMC_TR = BOARD_Sdram_Config.sdramc_tr;
     270        SDRAMC->SDRAMC_CFR1 = BOARD_Sdram_Config.sdramc_cfr1;
     271#endif /* __rtems__ */
    259272        /* After initialization, the SDRAM devices are fully functional. */
    260273}
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