Changeset be45f8e in rtems


Ignore:
Timestamp:
Nov 4, 2005, 1:00:33 AM (15 years ago)
Author:
Till Straumann <strauman@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
8c9fffd
Parents:
ab20575
Message:

2005-11-03 <strauman@…>

  • Makefile.am, include/bsp.h: Added new shared pretaskinghook.c and

zerobss.c files to list to be made. Added some explanations about
CPU <-> PCI <-> VME address mapping issues.

Location:
c/src/lib/libbsp/powerpc/motorola_powerpc
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/motorola_powerpc/ChangeLog

    rab20575 rbe45f8e  
     12005-11-03      <strauman@slac.stanford.edu>
     2
     3        * Makefile.am, include/bsp.h: Added new shared pretaskinghook.c and
     4    zerobss.c files to list to be made. Added some explanations about
     5    CPU <-> PCI <-> VME address mapping issues.
    162005-11-03      straumanatslacdotstanforddotedu
    27
  • c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.am

    rab20575 rbe45f8e  
    4242noinst_PROGRAMS += startup.rel
    4343startup_rel_SOURCES = ../../powerpc/shared/startup/bspstart.c \
     44        ../../powerpc/shared/startup/pretaskinghook.c \
     45        ../../powerpc/shared/startup/zerobss.c \
    4446    ../../powerpc/shared/startup/pgtbl_setup.c \
    4547    ../../powerpc/shared/startup/pgtbl_activate.c \
  • c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h

    rab20575 rbe45f8e  
    3333#define CONFIGURE_INTERRUPT_STACK_MEMORY  (16 * 1024)
    3434
     35/*
     36 * diagram illustrating the role of the configuration
     37 * constants
     38 *  PCI_MEM_WIN0:        CPU starting addr where PCI memory space is visible
     39 *  PCI_MEM_BASE:        CPU address of PCI mem addr. zero. (regardless of this
     40 *                       address being 'visible' or not!).
     41 * _VME_A32_WIN0_ON_PCI: PCI starting addr of the 1st window to VME
     42 * _VME_A32_WIN0_ON_VME: VME address of that same window
     43 *
     44 * AFAIK, only PreP boards have a non-zero PCI_MEM_BASE (i.e., an offset between
     45 * CPU and PCI addresses). The mvme2300 'ppcbug' firmware configures the PCI
     46 * bus using PCI base addresses! I.e., drivers need to add PCI_MEM_BASE to
     47 * the base address read from PCI config.space in order to translate that
     48 * into a CPU address.
     49 *
     50 * NOTE: VME addresses should NEVER be translated using these constants!
     51 *       they are strictly for BSP internal use. Drivers etc. should use
     52 *       the translation routines int VME.h (BSP_vme2local_adrs/BSP_local2vme_adrs).
     53 *
     54 *           CPU ADDR                  PCI_ADDR                                VME ADDR
     55 *
     56 *           00000000                  XXXXXXXX                                XXXXXXXX
     57 *    ^  ^   ........         
     58 *    |  |
     59 *    |  |  e.g., RAM                  XXXXXXXX
     60 *    |  |                                                                     00000000
     61 *    |  |  .........                                                          ^
     62 *    |  |            (possible offset                                         |
     63 *    |  |             between pci and XXXXXXXX                                | ......
     64 *    |  |             cpu addresses)                                          |
     65 *    |  v                                                                     |
     66 *    |  PCI_MEM_BASE  ------------->  00000000 ---------------                |
     67 *    |     ........                   ........               ^                |
     68 *    |                                invisible              |                |
     69 *    |     ........                   from CPU               |                |
     70 *    v                                                       |                |
     71 *       PCI_MEM_WIN0 =============  first visible PCI addr   |                |
     72 *                                                            |                |
     73 *        pci devices   pci window                            |                |
     74 *       visible here                                         v                v
     75 *                      mapped by   ========== _VME_A32_WIN0_ON_PCI =======  _VME_A32_WIN0_ON_VME
     76 *                                                 vme window
     77 *        VME devices   hostbridge                 mapped by
     78 *       visible here                              universe
     79 *                    =====================================================
     80 *
     81 */
     82
    3583/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */
    3684#if defined(mvme2100)
     
    3987/* address of our ram on the PCI bus   */
    4088#define PCI_DRAM_OFFSET         CHRP_PCI_DRAM_OFFSET
     89/* offset of pci memory as seen from the CPU */
    4190#define PCI_MEM_BASE            0
     91/* where (in CPU addr. space) does the PCI window start */
    4292#define PCI_MEM_WIN0            0x80000000
    4393
     
    103153extern unsigned int BSP_mem_size;
    104154/*
     155 * Start of the heap
     156 */
     157extern unsigned int BSP_heap_start;
     158/*
    105159 * PCI Bus Frequency
    106160 */
     
    127181/* clear hostbridge errors
    128182 *
    129  * enableMCP: whether to enable MCP checkstop / machine check interrupts
    130  *            on the hostbridge and in HID0.
    131  *
    132  *            NOTE: HID0 and MEREN are left alone if this flag is 0
    133  *
    134  * quiet    : be silent
    135  *
    136  * RETURNS  : raven MERST register contents (lowermost 16 bits), 0 if
    137  *            there were no errors
     183 * NOTE: The routine returns always (-1) if 'enableMCP==1'
     184 *       [semantics needed by libbspExt] if the MCP input is not wired.
     185 *       It returns and clears the error bits of the PCI status register.
     186 *       MCP support is disabled because:
     187 *         a) the 2100 has no raven chip
     188 *         b) the raven (2300) would raise machine check interrupts
     189 *            on PCI config space access to empty slots.
    138190 */
    139191extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);
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