Changeset bd91ff4e in rtems


Ignore:
Timestamp:
Nov 10, 2004, 10:15:01 PM (15 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Children:
9d8590d
Parents:
ae460ec
Message:

2004-11-10 Richard Campbell <richard.campbell@…>

  • ChangeLog?, Makefile.am, bootloader/misc.c, bootloader/pci.c, bootloader/pci.h, console/console.c, console/inch.c, console/reboot.c, console/uart.c, console/uart.h, include/bsp.h, irq/irq.c, irq/irq.h, irq/irq_init.c, motorola/motorola.c, motorola/motorola.h, openpic/openpic.c, openpic/openpic.h, pci/detect_raven_bridge.c, pci/pci.c, pci/pci.h, start/start.S, startup/bspstart.c, vectors/vectors_init.c, vme/vmeconfig.c: Add MVME2100 BSP and MPC8240 support. There was also a significant amount of spelling and whitespace cleanup.
  • tod/.cvsignore, tod/Makefile.am, tod/todcfg.c: New files.
Location:
c/src/lib/libbsp/powerpc/shared
Files:
3 added
25 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/shared/ChangeLog

    rae460ec rbd91ff4e  
     12004-11-10      Richard Campbell <richard.campbell@oarcorp.com>
     2
     3        * ChangeLog, Makefile.am, bootloader/misc.c, bootloader/pci.c,
     4        bootloader/pci.h, console/console.c, console/inch.c,
     5        console/reboot.c, console/uart.c, console/uart.h, include/bsp.h,
     6        irq/irq.c, irq/irq.h, irq/irq_init.c, motorola/motorola.c,
     7        motorola/motorola.h, openpic/openpic.c, openpic/openpic.h,
     8        pci/detect_raven_bridge.c, pci/pci.c, pci/pci.h, start/start.S,
     9        startup/bspstart.c, vectors/vectors_init.c, vme/vmeconfig.c: Add
     10        MVME2100 BSP and MPC8240 support. There was also a significant amount
     11        of spelling and whitespace cleanup.
     12        * tod/.cvsignore, tod/Makefile.am, tod/todcfg.c: New files.
     13
     142004-11-10      Richard Campbell <richard.campbell@oarcorp.com>
     15
     16        * Makefile.am, bootloader/misc.c, bootloader/pci.c, bootloader/pci.h,
     17        console/console.c, console/inch.c, console/reboot.c, console/uart.c,
     18        console/uart.h, include/bsp.h, irq/irq.c, irq/irq.h, irq/irq_init.c,
     19        motorola/motorola.c, motorola/motorola.h, openpic/openpic.c,
     20        openpic/openpic.h, pci/detect_raven_bridge.c, pci/pci.c, pci/pci.h,
     21        start/start.S, startup/bspstart.c, vectors/vectors_init.c,
     22        vme/vmeconfig.c: Add MVME2100 BSP and MPC8240 support.
     23        * tod/.cvsignore, tod/Makefile.am, tod/todcfg.c: New files.
     24
    1252004-09-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
    226
  • c/src/lib/libbsp/powerpc/shared/Makefile.am

    rae460ec rbd91ff4e  
    66if need_shared
    77SUBDIRS = clock console include pci residual openpic irq vectors start \
    8     startup motorola bootloader vme
     8    startup motorola bootloader vme tod
    99endif
    1010
  • c/src/lib/libbsp/powerpc/shared/bootloader/misc.c

    rae460ec rbd91ff4e  
    2525#include <libcpu/byteorder.h>
    2626#include <rtems/bspIo.h>
     27#include <bsp.h>
    2728
    2829SPR_RW(DEC)
     
    281282         * select the serial console if not.
    282283         */
     284#if defined(BSP_KBD_IOBASE)
    283285        err = kbdreset();
    284         if (err) select_console(CONSOLE_SERIAL);
     286        if (err) select_console(CONSOLE_SERIAL);
     287#else
     288        err = 1;
     289        select_console(CONSOLE_SERIAL);
     290#endif
    285291
    286292        printk("\nModel: %s\nSerial: %s\n"
     
    294300               (vpd.TimeBaseDivisor ? vpd.TimeBaseDivisor : 4000),
    295301               res->TotalMemory);
    296         printk("Original MSR: %lx\nOriginal HID0: %lx\nOriginal R31: %lx\n",
    297                bd->o_msr, bd->o_hid0, bd->o_r31);
    298302
    299303        /* This reconfigures all the PCI subsystem */
  • c/src/lib/libbsp/powerpc/shared/bootloader/pci.c

    rae460ec rbd91ff4e  
    2525#include <libcpu/page.h>
    2626#include <bsp/consoleIo.h>
     27#include <string.h>
    2728
    2829typedef unsigned int u32;
  • c/src/lib/libbsp/powerpc/shared/bootloader/pci.h

    rae460ec rbd91ff4e  
    498498#define PCI_DEVICE_ID_MOTOROLA_MPC105   0x0001
    499499#define PCI_DEVICE_ID_MOTOROLA_MPC106   0x0002
     500#define PCI_DEVICE_ID_MOTOROLA_MPC8240  0x0003
    500501#define PCI_DEVICE_ID_MOTOROLA_RAVEN    0x4801
    501502
  • c/src/lib/libbsp/powerpc/shared/console/console.c

    rae460ec rbd91ff4e  
    7575                },
    7676};
    77 
    7877
    7978/*-------------------------------------------------------------------------+
     
    136135
    137136  }
     137
    138138  return RTEMS_SUCCESSFUL;
    139139} /* console_initialize */
     
    175175  rtems_status_code              status;
    176176  static rtems_termios_callbacks cb =
     177#if defined(USE_POLLED_IO)
     178  {
     179    NULL,                               /* firstOpen */
     180    NULL,                               /* lastClose */
     181    NULL,                               /* pollRead */
     182    BSP_uart_termios_write_polled,      /* write */
     183    conSetAttr,                         /* setAttributes */
     184    NULL,                               /* stopRemoteTx */
     185    NULL,                               /* startRemoteTx */
     186    0                                   /* outputUsesInterrupts */
     187  };
     188#else
    177189  {
    178190    console_first_open,                 /* firstOpen */
    179191    console_last_close,                 /* lastClose */
    180     NULL,                                               /* pollRead */
    181     BSP_uart_termios_write_com, /* write */
    182     conSetAttr,                                 /* setAttributes */
    183     NULL,                                               /* stopRemoteTx */
    184     NULL,                                               /* startRemoteTx */
    185     1                                                   /* outputUsesInterrupts */
     192    NULL,                               /* pollRead */
     193    BSP_uart_termios_write_com,         /* write */
     194    conSetAttr,                         /* setAttributes */
     195    NULL,                               /* stopRemoteTx */
     196    NULL,                               /* startRemoteTx */
     197    1                                   /* outputUsesInterrupts */
    186198  };
     199#endif
    187200
    188201  status = rtems_termios_open (major, minor, arg, &cb);
     
    190203  if(status != RTEMS_SUCCESSFUL)
    191204    {
    192       printk("Error openning console device\n");
     205      printk("Error opening console device\n");
    193206      return status;
    194207    }
  • c/src/lib/libbsp/powerpc/shared/console/inch.c

    rae460ec rbd91ff4e  
    2121
    2222#include <bsp.h>
     23#if defined(BSP_KBD_IOBASE)
    2324#include <bsp/irq.h>
    2425
     
    300301    return c;
    301302} /* _IBMPC_inch */
    302 
    303 
    304 
    305 
    306 
    307 
     303#endif
  • c/src/lib/libbsp/powerpc/shared/console/reboot.c

    rae460ec rbd91ff4e  
    1717  CPU_print_stack();
    1818  /* shutdown and reboot */
     19#if defined(BSP_KBD_IOBASE)
    1920  kbd_outb(0x4, 0xFE);      /* use keyboard controler to do the job... */
     21#endif
    2022} /* rtemsReboot */
  • c/src/lib/libbsp/powerpc/shared/console/uart.c

    rae460ec rbd91ff4e  
    133133{
    134134  unsigned char tmp;
    135   
     135 
    136136  /* Sanity check */
    137137  SANITY_CHECK(uart);
     
    157157      return;
    158158    }
    159  
     159
    160160  /* Set DLAB bit to 1 */
    161161  uwrite(uart, LCR, DLAB);
    162  
     162
    163163  /* Set baud rate */
    164164  uwrite(uart, DLL,  (BSPBaseBaud/baud) & 0xff);
     
    186186  uart_data[uart].hwFlow     = hwFlow;
    187187  uart_data[uart].baud       = baud;
     188
    188189  return;
    189190}
     
    202203  /*
    203204   * This function may be called whenever TERMIOS parameters
    204    * are changed, so we have to make sire that baud change is
     205   * are changed, so we have to make sure that baud change is
    205206   * indeed required
    206207   */
     
    461462uart_isr_is_on(const rtems_irq_connect_data *irq)
    462463{
    463 int uart = (irq->name == BSP_ISA_UART_COM1_IRQ) ?
     464  int uart;
     465
     466#if defined(mvme2100)
     467  uart = BSP_UART_COM1;
     468#else
     469  uart = (irq->name == BSP_ISA_UART_COM1_IRQ) ?
    464470                        BSP_UART_COM1 : BSP_UART_COM2;
     471#endif
    465472  return uread(uart,IER);
    466473}
     
    470477{
    471478        rtems_irq_connect_data d={0};
     479#if defined(mvme2100)
     480        d.name = BSP_UART_COM1_IRQ;
     481#else
    472482        d.name = (uart == BSP_UART_COM1) ?
    473483                        BSP_ISA_UART_COM1_IRQ : BSP_ISA_UART_COM2_IRQ;
     484#endif
    474485        d.off  = d.on = uart_noop;
    475486        d.isOn = uart_isr_is_on;
     
    527538
    528539int
     540BSP_uart_termios_write_polled(int minor, const char *buf, int len)
     541{
     542  int uart=minor;       /* could differ, theoretically */
     543  int nwrite;
     544  const char *b = buf;
     545
     546  assert(buf != NULL);
     547
     548  for (nwrite=0 ; nwrite < len ; nwrite++) {
     549    BSP_uart_polled_write(uart, *b++);
     550  }
     551  return nwrite;
     552}
     553
     554int
    529555BSP_uart_termios_write_com(int minor, const char *buf, int len)
    530556{
     
    537563    }
    538564
    539   /* If there TX buffer is busy - something is royally screwed up */
     565  /* If the TX buffer is busy - something is royally screwed up */
    540566  /*   assert((uread(BSP_UART_COM1, LSR) & THRE) != 0); */
    541567       
  • c/src/lib/libbsp/powerpc/shared/console/uart.h

    rae460ec rbd91ff4e  
    1717
    1818void BSP_uart_init(int uart, int baud, int hwFlow);
    19 void BSP_uart_set_baud(int aurt, int baud);
     19void BSP_uart_set_baud(int uart, int baud);
    2020void BSP_uart_intr_ctrl(int uart, int cmd);
    2121void BSP_uart_throttle(int uart);
     
    3232int  BSP_uart_install_isr(int uart, rtems_irq_hdl handler);
    3333int  BSP_uart_remove_isr(int uart, rtems_irq_hdl handler);
     34int  BSP_uart_termios_write_polled(int minor, const char *buf, int len);
    3435int  BSP_uart_get_break_cb(int uart, rtems_libio_ioctl_args_t *arg);
    3536int  BSP_uart_set_break_cb(int uart, rtems_libio_ioctl_args_t *arg);
  • c/src/lib/libbsp/powerpc/shared/include/bsp.h

    rae460ec rbd91ff4e  
    2727 */
    2828
     29#if defined(mvme2100)
     30#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 1
     31#else
    2932#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
     33#endif
     34
    3035#define CONFIGURE_INTERRUPT_STACK_MEMORY  (16 * 1024)
    3136
    32 /* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */
    33 #define _IO_BASE                        PREP_ISA_IO_BASE
     37/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */
     38#if defined(mvme2100)
     39#define _IO_BASE                CHRP_ISA_IO_BASE
     40#define _ISA_MEM_BASE           CHRP_ISA_MEM_BASE
     41/* address of our ram on the PCI bus   */
     42#define PCI_DRAM_OFFSET         CHRP_PCI_DRAM_OFFSET
     43#define PCI_MEM_BASE            0x80000000
     44#define PCI_MEM_BASE_ADJUSTMENT 0
     45
     46#else
     47#define _IO_BASE                PREP_ISA_IO_BASE
    3448#define _ISA_MEM_BASE           PREP_ISA_MEM_BASE
    3549/* address of our ram on the PCI bus   */
     
    3751/* offset of pci memory as seen from the CPU */
    3852#define PCI_MEM_BASE            PREP_ISA_MEM_BASE
    39 
    40 /*
    41  *  base address definitions for several devices
    42  *
    43  */
     53#define PCI_MEM_BASE_ADJUSTMENT PREP_ISA_MEM_BASE
     54#endif
     55
     56/*
     57 *  Base address definitions for several devices
     58 *
     59 *  MVME2100 is very similar but has fewer devices and uses on-CPU EPIC
     60 *  implementation of OpenPIC controller.  It also cannot be probed to
     61 *  find out what it is which is VERY different from other Motorola boards.
     62 */
     63
     64#if defined(mvme2100)
     65#define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x01e10000)
     66/* #define BSP_UART_IOBASE_COM1     (0xffe10000) */
     67#define BSP_OPEN_PIC_BASE_OFFSET 0x40000
     68
     69#define MVME_HAS_DEC21140
     70#else
    4471#define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x3f8)
    4572#define BSP_UART_IOBASE_COM2 ((_IO_BASE)+0x2f8)
     73
    4674#define BSP_KBD_IOBASE       ((_IO_BASE)+0x60)
    4775#define BSP_VGA_IOBASE       ((_IO_BASE)+0x3c0)
    4876
     77#if defined(mvme2300)
     78#define MVME_HAS_DEC21140
     79#endif
     80#endif
     81
     82#define BSP_UART_BAUD_BASE      115200
    4983#define BSP_CONSOLE_PORT        BSP_UART_COM1
    50 #define BSP_UART_BAUD_BASE      115200
     84
     85#if defined(MVME_HAS_DEC21140)
     86struct rtems_bsdnet_ifconfig;
     87int rtems_dec21140_driver_attach (struct rtems_bsdnet_ifconfig *, int);
     88                                                                               
     89#define RTEMS_BSP_NETWORK_DRIVER_NAME "dc1"
     90#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_dec21140_driver_attach
     91#endif
    5192 
    5293#include <bsp/openpic.h>
  • c/src/lib/libbsp/powerpc/shared/irq/irq.c

    rae460ec rbd91ff4e  
    2222#include <libcpu/io.h>
    2323#include <bsp/vectors.h>
     24#include <stdlib.h>
    2425
    2526#include <rtems/bspIo.h> /* for printk */
     
    2930 * pointer to the mask representing the additionnal irq vectors
    3031 * that must be disabled when a particular entry is activated.
    31  * They will be dynamically computed from teh prioruty table given
     32 * They will be dynamically computed from the priority table given
    3233 * in BSP_rtems_irq_mngt_set();
    3334 * CAUTION : this table is accessed directly by interrupt routine
     
    6869
    6970/*
    70  * Check if IRQ is a Porcessor IRQ
     71 * Check if IRQ is a Processor IRQ
    7172 */
    7273static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine)
     
    127128    unsigned int level;
    128129    rtems_irq_connect_data* vchain;
    129   
     130 
    130131    if (!isValidInterrupt(irq->name)) {
    131132      printk("Invalid interrupt vector %d\n",irq->name);
     
    192193{
    193194    unsigned int level;
    194   
     195 
    195196    if (!isValidInterrupt(irq->name)) {
    196197      printk("Invalid interrupt vector %d\n",irq->name);
     
    364365
    365366/*
    366  * ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
     367 * RTEMS Global Interrupt Handler Management Routines
    367368 */
    368369
     
    518519  register unsigned new_msr;
    519520
    520 
    521521  if (excNum == ASM_DEC_VECTOR) {
    522522    _CPU_MSR_GET(msr);
     
    528528    _CPU_MSR_SET(msr);
    529529    return;
    530    
    531   }
     530  }
     531
    532532  irq = openpic_irq(0);
    533533  if (irq == OPENPIC_VEC_SPURIOUS) {
  • c/src/lib/libbsp/powerpc/shared/irq/irq.h

    rae460ec rbd91ff4e  
    22 *
    33 *  This include file describe the data structure and the functions implemented
    4  *  by rtems to write interrupt handlers.
    5  *
    6  *  CopyRight (C) 1999 valette@crf.canon.fr
     4 *  by RTEMS to write interrupt handlers.
     5 *
     6 *  Copyright (C) 1999 valette@crf.canon.fr
    77 *
    88 *  This code is heavilly inspired by the public specification of STREAM V2
     
    2121#ifndef LIBBSP_POWERPC_MCP750_IRQ_IRQ_H
    2222#define LIBBSP_POWERPC_MCP750_IRQ_IRQ_H
    23 
    2423
    2524/*
     
    6665
    6766/*
    68  * Symblolic IRQ names and related definitions.
     67 * Symbolic IRQ names and related definitions.
    6968 */
    7069
    7170typedef enum {
    7271  /* Base vector for our ISA IRQ handlers. */
    73   BSP_ISA_IRQ_VECTOR_BASE       =       BSP_ASM_IRQ_VECTOR_BASE,
     72  BSP_ISA_IRQ_VECTOR_BASE       = BSP_ASM_IRQ_VECTOR_BASE,
    7473  /*
    7574   * ISA IRQ handler related definitions
    7675   */
    77   BSP_ISA_IRQ_NUMBER            =       16,
    78   BSP_ISA_IRQ_LOWEST_OFFSET     =       0,
    79   BSP_ISA_IRQ_MAX_OFFSET        =       BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1,
     76  BSP_ISA_IRQ_NUMBER            = 16,
     77  BSP_ISA_IRQ_LOWEST_OFFSET     = 0,
     78  BSP_ISA_IRQ_MAX_OFFSET        = BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1,
    8079  /*
    8180   * PCI IRQ handlers related definitions
    8281   * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
    8382   */
    84   BSP_PCI_IRQ_NUMBER            =       16,
    85   BSP_PCI_IRQ_LOWEST_OFFSET     =       BSP_ISA_IRQ_NUMBER,
    86   BSP_PCI_IRQ_MAX_OFFSET        =       BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1,
    87   /*
    88    * PowerPc exceptions handled as interrupt where a rtems managed interrupt
     83  BSP_PCI_IRQ_NUMBER            = 16,
     84  BSP_PCI_IRQ_LOWEST_OFFSET     = BSP_ISA_IRQ_NUMBER,
     85  BSP_PCI_IRQ_MAX_OFFSET        = BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1,
     86  /*
     87   * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
    8988   * handler might be connected
    9089   */
    91   BSP_PROCESSOR_IRQ_NUMBER      =       1,
    92   BSP_PROCESSOR_IRQ_LOWEST_OFFSET =     BSP_PCI_IRQ_MAX_OFFSET + 1,
    93   BSP_PROCESSOR_IRQ_MAX_OFFSET  =       BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1,
     90  BSP_PROCESSOR_IRQ_NUMBER      = 1,
     91  BSP_PROCESSOR_IRQ_LOWEST_OFFSET = BSP_PCI_IRQ_MAX_OFFSET + 1,
     92  BSP_PROCESSOR_IRQ_MAX_OFFSET  = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1,
    9493  /* Misc vectors for OPENPIC irqs (IPI, timers)
    9594   */
    96   BSP_MISC_IRQ_NUMBER           =       8,
    97   BSP_MISC_IRQ_LOWEST_OFFSET    =       BSP_PROCESSOR_IRQ_MAX_OFFSET + 1,
    98   BSP_MISC_IRQ_MAX_OFFSET       =       BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1,
     95  BSP_MISC_IRQ_NUMBER           = 8,
     96  BSP_MISC_IRQ_LOWEST_OFFSET    = BSP_PROCESSOR_IRQ_MAX_OFFSET + 1,
     97  BSP_MISC_IRQ_MAX_OFFSET       = BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1,
    9998  /*
    10099   * Summary
    101100   */
    102   BSP_IRQ_NUMBER                =       BSP_MISC_IRQ_MAX_OFFSET + 1,
    103   BSP_LOWEST_OFFSET             =       BSP_ISA_IRQ_LOWEST_OFFSET,
    104   BSP_MAX_OFFSET                =       BSP_MISC_IRQ_MAX_OFFSET,
     101  BSP_IRQ_NUMBER                = BSP_MISC_IRQ_MAX_OFFSET + 1,
     102  BSP_LOWEST_OFFSET             = BSP_ISA_IRQ_LOWEST_OFFSET,
     103  BSP_MAX_OFFSET                = BSP_MISC_IRQ_MAX_OFFSET,
    105104    /*
    106105     * Some ISA IRQ symbolic name definition
    107      */       
    108   BSP_ISA_PERIODIC_TIMER        =       0,
    109 
    110   BSP_ISA_KEYBOARD              =       1,
    111 
    112   BSP_ISA_UART_COM2_IRQ         =       3,
    113 
    114   BSP_ISA_UART_COM1_IRQ         =       4,
    115 
    116   BSP_ISA_RT_TIMER1             =       8,
    117  
    118   BSP_ISA_RT_TIMER3             =       10,
     106     */
     107  BSP_ISA_PERIODIC_TIMER        =  0,
     108  BSP_ISA_KEYBOARD              =  1,
     109  BSP_ISA_UART_COM2_IRQ         =  3,
     110  BSP_ISA_UART_COM1_IRQ         =  4,
     111  BSP_ISA_RT_TIMER1             =  8,
     112  BSP_ISA_RT_TIMER3             = 10,
    119113    /*
    120114     * Some PCI IRQ symbolic name definition
    121115     */
    122   BSP_PCI_IRQ0                  =       BSP_PCI_IRQ_LOWEST_OFFSET,
    123   BSP_PCI_ISA_BRIDGE_IRQ        =       BSP_PCI_IRQ0,
     116  BSP_PCI_IRQ0                  = BSP_PCI_IRQ_LOWEST_OFFSET,
     117  BSP_PCI_ISA_BRIDGE_IRQ        = BSP_PCI_IRQ0,
     118
     119#if defined(mvme2100)
     120  BSP_DEC21143_IRQ                = BSP_PCI_IRQ_LOWEST_OFFSET + 1,
     121  BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ   = BSP_PCI_IRQ_LOWEST_OFFSET + 2,
     122  BSP_PCMIP_TYPE1_SLOT1_IRQ       = BSP_PCI_IRQ_LOWEST_OFFSET + 3,
     123  BSP_PCMIP_TYPE2_SLOT0_IRQ       = BSP_PCI_IRQ_LOWEST_OFFSET + 4,
     124  BSP_PCMIP_TYPE2_SLOT1_IRQ       = BSP_PCI_IRQ_LOWEST_OFFSET + 5,
     125  BSP_PCI_INTA_UNIVERSE_LINT0_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 7,
     126  BSP_PCI_INTB_UNIVERSE_LINT1_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 8,
     127  BSP_PCI_INTC_UNIVERSE_LINT2_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 9,
     128  BSP_PCI_INTD_UNIVERSE_LINT3_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 10,
     129  BSP_UART_COM1_IRQ               = BSP_PCI_IRQ_LOWEST_OFFSET + 13,
     130  BSP_FRONT_PANEL_ABORT_IRQ       = BSP_PCI_IRQ_LOWEST_OFFSET + 14,
     131  BSP_RTC_IRQ                     = BSP_PCI_IRQ_LOWEST_OFFSET + 15,
     132#endif
     133
    124134    /*
    125      * Some Processor execption handled as rtems IRQ symbolic name definition
     135     * Some Processor exception handled as RTEMS IRQ symbolic name definition
    126136     */
    127   BSP_DECREMENTER               =       BSP_PROCESSOR_IRQ_LOWEST_OFFSET
    128  
    129 }rtems_irq_symbolic_name;
    130 
    131    
    132 
     137  BSP_DECREMENTER               = BSP_PROCESSOR_IRQ_LOWEST_OFFSET
     138
     139} rtems_irq_symbolic_name;
    133140
    134141/*
     
    163170       * RTEMS may well need such a function when restoring normal interrupt
    164171       * processing after a debug session.
    165        *
    166172       */
    167173      rtems_irq_enable          on;     
     
    206212  /*
    207213   * software priorities associated with interrupts.
    208    * if irqPrio  [i]  >  intrPrio  [j]  it  means  that 
     214   * if irqPrio  [i]  >  intrPrio  [j]  it  means  that
    209215   * interrupt handler hdl connected for interrupt name i
    210216   * will  not be interrupted by the handler connected for interrupt j
     
    237243int BSP_irq_enable_at_i8259s            (const rtems_irq_symbolic_name irqLine);
    238244/*
    239  * function to acknoledge a particular irq at 8259 level. After calling
     245 * function to acknowledge a particular irq at 8259 level. After calling
    240246 * this function, if a device asserts an enabled interrupt line it will
    241  * be propagated further to the processor. Mainly usefull for people
    242  * writting raw handlers as this is automagically done for rtems managed
     247 * be propagated further to the processor. Mainly useful for people
     248 * writing raw handlers as this is automagically done for RTEMS managed
    243249 * handlers.
    244250 */
     
    261267 *      4) modify them to disable the current interrupt at 8259 level (and may
    262268 *      be others depending on software priorities)
    263  *      5) aknowledge the i8259s',
     269 *      5) acknowledge the i8259s',
    264270 *      6) demask the processor,
    265271 *      7) call the application handler
     
    268274 *
    269275 *      a) can perfectly be written is C,
    270  *      b) may also well directly call the part of the RTEMS API that can be used
    271  *      from interrupt level,
    272  *      c) It only responsible for handling the jobs that need to be done at
    273  *      the device level including (aknowledging/re-enabling the interrupt at device,
    274  *      level, getting the data,...)
     276 *      b) may also well directly call the part of the RTEMS API that can be
     277 *         used from interrupt level,
     278 *      c) It is only responsible for handling the jobs that need to be done at
     279 *         the device level including (acknowledging/re-enabling the interrupt
     280 *         at the device level, getting the data,...)
    275281 *
    276282 *      When returning from the function, the following will be performed by
     
    283289 *      5) restore the C scratch registers...
    284290 *      6) restore initial execution flow
    285  *
    286291 */
    287292int BSP_install_rtems_irq_handler       (const rtems_irq_connect_data*);
     
    297302/*
    298303 * function to get disconnect the RTEMS irq handler for ptr->name.
    299  * This function checks that the value given is the current one for safety reason.
     304 * This function checks that the value given is the current one for safety
     305 * reasons.
    300306 * The user can use the previous function to get it.
    301307 */
     
    330336 */
    331337int BSP_rtems_irq_mngt_get(rtems_irq_global_settings**);
    332  
     338
    333339extern void BSP_rtems_irq_mng_init(unsigned cpuId);
    334340extern void BSP_i8259s_init(void);
  • c/src/lib/libbsp/powerpc/shared/irq/irq_init.c

    rae460ec rbd91ff4e  
    2929#include <bsp/motorola.h>
    3030#include <rtems/bspIo.h>
    31 
    32 /*
    33 #define SHOW_ISA_PCI_BRIDGE_SETTINGS
    34 */
    3531
    3632typedef struct {
     
    6965static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
    7066  /*
    71    * actual rpiorities for interrupt :
     67   * actual priorities for interrupt :
    7268   *    0   means that only current interrupt is masked
    7369   *    255 means all other interrupts are masked
     
    7672   * ISA interrupts.
    7773   * The second entry has a priority of 255 because
    78    * it is the slave pic entry and is should always remain
     74   * it is the slave pic entry and should always remain
    7975   * unmasked.
    8076   */
     
    9288};
    9389
     90#if defined(mvme2100)
     91static unsigned char mvme2100_openpic_initpolarities[16] = {
     92    0,  /* Not used - should be disabled */
     93    0,  /* DEC21143 Controller */
     94    0,  /* PMC/PC-MIP Type I Slot 0 */
     95    0,  /* PC-MIP Type I Slot 1 */
     96    0,  /* PC-MIP Type II Slot 0 */
     97    0,  /* PC-MIP Type II Slot 1 */
     98    0,  /* Not used - should be disabled */
     99    0,  /* PCI Expansion Interrupt A/Universe II (LINT0) */
     100    0,  /* PCI Expansion Interrupt B/Universe II (LINT1) */
     101    0,  /* PCI Expansion Interrupt C/Universe II (LINT2) */
     102    0,  /* PCI Expansion Interrupt D/Universe II (LINT3) */
     103    0,  /* Not used - should be disabled */
     104    0,  /* Not used - should be disabled */
     105    1,  /* 16550 UART */
     106    0,  /* Front panel Abort Switch */
     107    0,  /* RTC IRQ */
     108};
     109
     110static unsigned char mvme2100_openpic_initsenses[] = {
     111    0,  /* Not used - should be disabled */
     112    1,  /* DEC21143 Controller */
     113    1,  /* PMC/PC-MIP Type I Slot 0 */
     114    1,  /* PC-MIP Type I Slot 1 */
     115    1,  /* PC-MIP Type II Slot 0 */
     116    1,  /* PC-MIP Type II Slot 1 */
     117    0,  /* Not used - should be disabled */
     118    1,  /* PCI Expansion Interrupt A/Universe II (LINT0) */
     119    1,  /* PCI Expansion Interrupt B/Universe II (LINT1) */
     120    1,  /* PCI Expansion Interrupt C/Universe II (LINT2) */
     121    1,  /* PCI Expansion Interrupt D/Universe II (LINT3) */
     122    0,  /* Not used - should be disabled */
     123    0,  /* Not used - should be disabled */
     124    1,  /* 16550 UART */
     125    0,  /* Front panel Abort Switch */
     126    1,  /* RTC IRQ */
     127};
     128#else
    94129static unsigned char mcp750_openpic_initpolarities[16] = {
    95130    1,  /* 8259 cascade */
     
    115150    1,  /* MCP750_INT_PCI_BUS2_INTD */
    116151};
     152#endif
    117153
    118154void VIA_isa_bridge_interrupts_setup(void)
     
    227263void BSP_rtems_irq_mng_init(unsigned cpuId)
    228264{
     265#if !defined(mvme2100)
     266  int known_cpi_isa_bridge = 0;
     267#endif
    229268  rtems_raw_except_connect_data vectorDesc;
    230   int known_cpi_isa_bridge = 0;
    231269  int i;
    232270 
     
    234272   * First initialize the Interrupt management hardware
    235273   */
    236 #ifdef TRACE_IRQ_INIT 
     274#if defined(mvme2100)
     275#ifdef TRACE_IRQ_INIT
     276  printk("Going to initialize EPIC interrupt controller (openpic compliant)\n");
     277#endif
     278  openpic_init(1, mvme2100_openpic_initpolarities, mvme2100_openpic_initsenses);
     279#else
     280#ifdef TRACE_IRQ_INIT
    237281  printk("Going to initialize raven interrupt controller (openpic compliant)\n");
    238 #endif       
     282#endif
    239283  openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses);
     284#endif       
     285
     286#if !defined(mvme2100)
    240287#ifdef TRACE_IRQ_INIT 
    241288  printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
     
    262309  printk("Going to initialize the ISA PC legacy IRQ management hardware\n");
    263310#endif       
     311
    264312  BSP_i8259s_init();
    265   /*
    266    * Initialize Rtems management interrupt table
     313#endif
     314
     315  /*
     316   * Initialize RTEMS management interrupt table
    267317   */
    268318    /*
     
    310360      BSP_panic("Unable to initialize RTEMS external raw exception\n");
    311361    }
    312 #ifdef TRACE_IRQ_INIT 
    313     printk("RTEMS IRQ management is now operationnal\n");
     362#ifdef TRACE_IRQ_INIT
     363    printk("RTEMS IRQ management is now operational\n");
    314364#endif
    315365}
  • c/src/lib/libbsp/powerpc/shared/motorola/motorola.c

    rae460ec rbd91ff4e  
    1313 */
    1414
    15 
     15#include <bsp.h>
    1616#include <bsp/motorola.h>
    1717#include <rtems/bspIo.h>
     
    2121
    2222/*
    23 ** Board-specific table that maps interrupt names to onboard pci
    24 ** peripherals as well as local pci busses.  This table is used at
     23** Board-specific table that maps interrupt names to onboard PCI
     24** peripherals as well as local PCI busses.  This table is used at
    2525** bspstart() to configure the interrupt name & pin for all devices that
    2626** do not have it already specified.  If the device is already
     
    117117   NULL_INTMAP };
    118118
    119 
    120 
    121 
    122 
    123 
    124 
     119static struct _int_map mvme2100_intmap[] = {
     120   {0, 0, 0, {{1, {16,-1,-1,-1}}, /* something shows up in slot 0 and OpenPIC */
     121                                  /* 0 is unused.  This hushes the init code. */
     122               NULL_PINMAP}},
     123
     124   {0, 13, 0, {{1, {23,24,25,26}},  /* PCI INT[A-D]/Universe Lint[0-3] */
     125               NULL_PINMAP}},
     126
     127   {0, 14, 0, {{1, {17,-1,-1,-1}},  /* onboard ethernet */
     128               NULL_PINMAP}},
     129
     130   NULL_INTMAP };
    125131
    126132/*
     
    141147   return prep_pci_intpins[ slot % 4 ][ pin-1 ];
    142148}
    143 
    144 
    145 
    146 
    147 
    148 
    149 
    150 
    151149
    152150typedef struct {
     
    163161      int               (*swizzler)(int, int);
    164162} mot_info_t;
    165 
    166163
    167164static const mot_info_t mot_boards[] = {
     
    186183  {0x1E0, 0xFE, "MVME 3600 with MVME761", NULL, NULL},
    187184  {0x1E0, 0xFF, "MVME 1600-001 or 1600-011", NULL, NULL},
    188   {0x000, 0x00, ""}
     185  {0x000, 0x00, ""},   /* end of probeable values for automatic scan */
     186  {0x000, 0x00, "MVME 2100", mvme2100_intmap, prep_pci_swizzle},
    189187};
    190188
    191 
    192 
    193189prep_t currentPrepType;
    194 motorolaBoard           currentBoard;
     190motorolaBoard currentBoard;
     191
    195192prep_t checkPrepBoardType(RESIDUAL *res)
    196193{
     
    214211}
    215212
    216 motorolaBoard   getMotorolaBoard()
    217 {
     213motorolaBoard getMotorolaBoard()
     214{
     215/*
     216 *  At least the MVME2100 does not have the CPU Type and Base Type Registers,
     217 *  so it cannot be probed.
     218 *
     219 *  NOTE: Every path must set currentBoard.
     220 */
     221#if defined(mvme2100)
     222  currentBoard = (motorolaBoard) MVME_2100;
     223#else
    218224  unsigned char  cpu_type;
    219225  unsigned char  base_mod;
    220226  int            entry;
    221227  int            mot_entry = -1;
    222 
     228 
    223229  cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0;
    224230  base_mod = inb(MOTOROLA_BASETYPE_REG);
     
    235241    if (mot_boards[entry].base_type != base_mod)
    236242      continue;
    237     else{
     243    else {
    238244      mot_entry = entry;
    239245      break;
     
    248254  }
    249255  currentBoard = (motorolaBoard) mot_entry;
     256#endif
    250257  return currentBoard;
    251258}
     
    262269{
    263270  if (board == MOTOROLA_UNKNOWN) return NULL;
     271  /* printk( "IntMap board %d 0x%08x\n", board, mot_boards[board].intmap ); */
    264272  return mot_boards[board].intmap;
    265273}
  • c/src/lib/libbsp/powerpc/shared/motorola/motorola.h

    rae460ec rbd91ff4e  
    5353  MVME_3600_W_MVME761           = 18,
    5454  MVME_1600                     = 19,
     55  /* In the table, slot 20 is the marker for end of automatic probe and scan */
     56  MVME_2100                     = 21,
    5557  MOTOROLA_UNKNOWN              = 255
    5658} motorolaBoard;
     
    6062  HOST_BRIDGE_HAWK      = 1,
    6163  HOST_BRIDGE_UNKNOWN   = 255
    62 }motorolaHostBridge;
     64} motorolaHostBridge;
    6365 
    6466#define MOTOROLA_CPUTYPE_REG    0x800
  • c/src/lib/libbsp/powerpc/shared/openpic/openpic.c

    rae460ec rbd91ff4e  
    2121
    2222#include <rtems.h>
     23#include <bsp.h>
    2324#include <rtems/bspIo.h>
    2425#include <bsp/openpic.h>
     
    2627#include <libcpu/io.h>
    2728#include <libcpu/byteorder.h>
    28 #include <bsp.h>
    2929#include <rtems/bspIo.h>
    3030
     
    199199
    200200    /* Kludge for the Raven */
     201/*
    201202    pci_read_config_dword(0, 0, 0, 0, &t);
     203*/
    202204    if (t == PCI_VENDOR_ID_MOTOROLA + (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) {
    203205        vendor = "Motorola";
     
    480482void openpic_initirq(unsigned int irq, unsigned int pri, unsigned int vec, int pol, int sense)
    481483{
     484#if 0
     485  printk("openpic_initirq: irq=%d pri=%d vec=%d pol=%d sense=%d\n",
     486    irq, pri, vec, pol, sense);
     487#endif
     488
    482489    check_arg_irq(irq);
    483490    check_arg_pri(pri);
  • c/src/lib/libbsp/powerpc/shared/openpic/openpic.h

    rae460ec rbd91ff4e  
    3838#define _RTEMS_OPENPIC_H
    3939
    40 
    4140    /*
    4241     *  OpenPIC supports up to 2048 interrupt sources and up to 32 processors
    4342     */
    4443
     44#if defined(mpc8240) || defined(mpc8245)
     45#define OPENPIC_MAX_SOURCES     (2048 - 16)
     46#else
    4547#define OPENPIC_MAX_SOURCES     2048
     48#endif
    4649#define OPENPIC_MAX_PROCESSORS  32
    4750
     
    158161    OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS];
    159162    char Pad1[0xee00];
     163#if defined(mpc8240) || defined(mpc8245)
     164    char Pad2[0x0200];
     165#endif
    160166} OpenPIC_Global;
    161167
  • c/src/lib/libbsp/powerpc/shared/pci/detect_raven_bridge.c

    rae460ec rbd91ff4e  
    1313
    1414#include <rtems/bspIo.h>
     15#include <libcpu/cpuIdent.h>
    1516
    16 #define RAVEN_MPIC_IOSPACE_ENABLE       0x1
    17 #define RAVEN_MPIC_MEMSPACE_ENABLE      0x2
    18 #define RAVEN_MASTER_ENABLE             0x4
    19 #define RAVEN_PARITY_CHECK_ENABLE       0x40
    20 #define RAVEN_SYSTEM_ERROR_ENABLE       0x100
    21 #define RAVEN_CLEAR_EVENTS_MASK         0xf9000000
     17#define RAVEN_MPIC_IOSPACE_ENABLE  0x0001
     18#define RAVEN_MPIC_MEMSPACE_ENABLE 0x0002
     19#define RAVEN_MASTER_ENABLE        0x0004
     20#define RAVEN_PARITY_CHECK_ENABLE  0x0040
     21#define RAVEN_SYSTEM_ERROR_ENABLE  0x0100
     22#define RAVEN_CLEAR_EVENTS_MASK    0xf9000000
    2223
    23 #define RAVEN_MPIC_MEREN                ((volatile unsigned *)0xfeff0020)
    24 #define RAVEN_MPIC_MERST                ((volatile unsigned *)0xfeff0024)
     24#define RAVEN_MPIC_MEREN    ((volatile unsigned *)0xfeff0020)
     25#define RAVEN_MPIC_MERST    ((volatile unsigned *)0xfeff0024)
    2526/* enable machine check on all conditions */
    26 #define MEREN_VAL                               0x2f00
     27#define MEREN_VAL           0x2f00
    2728
    2829#define pci BSP_pci_configuration
     30extern unsigned int EUMBBAR;
    2931
    3032extern const pci_config_access_functions pci_direct_functions;
     
    3638unsigned merst;
    3739
    38                 merst = in_be32(RAVEN_MPIC_MERST);
    39                 /* write back value to clear status */
    40                 out_be32(RAVEN_MPIC_MERST, merst);
     40    merst = in_be32(RAVEN_MPIC_MERST);
     41    /* write back value to clear status */
     42    out_be32(RAVEN_MPIC_MERST, merst);
    4143
    42                 if (enableMCP) {
    43                         if (!quiet)
    44                                 printk("Enabling MCP generation on hostbridge errors\n");
    45                         out_be32(RAVEN_MPIC_MEREN, MEREN_VAL);
    46                 } else {
    47                         out_be32(RAVEN_MPIC_MEREN, 0);
    48                         if ( !quiet && enableMCP ) {
    49                                 printk("leaving MCP interrupt disabled\n");
    50                         }
    51                 }
    52                 return (merst & 0xffff);
     44    if (enableMCP) {
     45      if (!quiet)
     46        printk("Enabling MCP generation on hostbridge errors\n");
     47      out_be32(RAVEN_MPIC_MEREN, MEREN_VAL);
     48    } else {
     49      out_be32(RAVEN_MPIC_MEREN, 0);
     50      if ( !quiet && enableMCP ) {
     51        printk("leaving MCP interrupt disabled\n");
     52      }
     53    }
     54    return (merst & 0xffff);
    5355}
    5456
    5557void detect_host_bridge()
    5658{
     59#if (defined(mpc8240) || defined(mpc8245))
     60  /*
     61   * If the processor is an 8240 or an 8245 then the PIC is built
     62   * in instead of being on the PCI bus. The MVME2100 is using Processor
     63   * Address Map B (CHRP) although the Programmer's Reference Guide says
     64   * it defaults to Map A.
     65   */
     66  /* We have an EPIC Interrupt Controller  */
     67  OpenPIC = (volatile struct OpenPIC *) (EUMBBAR + BSP_OPEN_PIC_BASE_OFFSET);
     68  pci.pci_functions = &pci_indirect_functions;
     69  pci.pci_config_addr = (volatile unsigned char *) 0xfec00000;
     70  pci.pci_config_data = (volatile unsigned char *) 0xfee00000;
     71#else
     72
    5773  PPC_DEVICE *hostbridge;
    5874  unsigned int id0;
    5975  unsigned int tmp;
    60  
     76
    6177  /*
    6278   * This code assumes that the host bridge is located at
     
    6581   * (still used in BSD source code) works.
    6682   */
    67   hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL,
    68                                   BridgeController,
    69                                   PCIBridge, -1, 0);
     83  hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL,
     84            BridgeController,
     85            PCIBridge, -1, 0);
     86
    7087  if (hostbridge) {
    7188    if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) {
    7289      pci.pci_functions=&pci_indirect_functions;
    73       /* Should be extracted from residual data, 
     90      /* Should be extracted from residual data,
    7491       * indeed MPC106 in CHRP mode is different,
    7592       * but we should not use residual data in
    76        * this case anyway. 
     93       * this case anyway.
    7794       */
    78       pci.pci_config_addr = ((volatile unsigned char *) 
    79                               (ptr_mem_map->io_base+0xcf8));
     95      pci.pci_config_addr = ((volatile unsigned char *)
     96             (ptr_mem_map->io_base+0xcf8));
    8097      pci.pci_config_data = ptr_mem_map->io_base+0xcfc;
    8198    } else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) {
     
    88105    pci.pci_functions = &pci_direct_functions;
    89106    /* On all direct bridges I know the host bridge itself
    90      * appears as device 0 function 0. 
    91                 */
     107     * appears as device 0 function 0.
     108    */
    92109    pci_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &id0);
    93110    if (id0==~0U) {
    94111      pci.pci_functions = &pci_indirect_functions;
    95       pci.pci_config_addr = ((volatile unsigned char*)
    96                               (ptr_mem_map->io_base+0xcf8));
    97       pci.pci_config_data = ((volatile unsigned char*)ptr_mem_map->io_base+0xcfc);
     112      pci.pci_config_addr = (volatile unsigned char*)
     113              (ptr_mem_map->io_base+0xcf8);
     114      pci.pci_config_data = (volatile unsigned char*)
     115                              (ptr_mem_map->io_base+0xcfc);
    98116    }
    99117    /* Here we should check that the host bridge is actually
     
    103121  }
    104122  pci_read_config_dword(0, 0, 0, 0, &id0);
     123
    105124  if(id0 == PCI_VENDOR_ID_MOTOROLA +
    106125     (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) {
     
    109128     */
    110129    pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0);
    111 #ifdef SHOW_RAVEN_SETTING   
     130#ifdef SHOW_RAVEN_SETTING
    112131    printk("RAVEN PCI command register = %x\n",id0);
    113 #endif   
     132#endif
    114133    id0 |= RAVEN_CLEAR_EVENTS_MASK;
    115134    pci_write_config_dword(0, 0, 0, PCI_COMMAND, id0);
    116135    pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0);
    117 #ifdef SHOW_RAVEN_SETTING   
     136#ifdef SHOW_RAVEN_SETTING
    118137    printk("After error clearing RAVEN PCI command register = %x\n",id0);
    119 #endif   
    120    
     138#endif
     139
    121140    if (id0 & RAVEN_MPIC_IOSPACE_ENABLE) {
    122141      pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_0, &tmp);
    123 #ifdef SHOW_RAVEN_SETTING   
    124       printk("Raven MPIC is accessed via IO Space Access at address : %x\n",(tmp & ~0x1));
    125 #endif   
     142#ifdef SHOW_RAVEN_SETTING
     143      printk("Raven MPIC is accessed via IO Space Access at address : %x\n",
     144          (tmp & ~0x1));
     145#endif
    126146    }
    127147    if (id0 & RAVEN_MPIC_MEMSPACE_ENABLE) {
    128148      pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_1, &tmp);
    129 #ifdef SHOW_RAVEN_SETTING   
    130       printk("Raven MPIC is accessed via memory Space Access at address : %x\n", tmp);
    131 #endif   
     149#ifdef SHOW_RAVEN_SETTING
     150      printk("Raven MPIC is accessed via memory Space Access"
     151             "at address : %x\n", tmp)
     152#endif
    132153      OpenPIC=(volatile struct OpenPIC *) (tmp + PREP_ISA_MEM_BASE);
    133       printk("OpenPIC found at %x.\n",
    134              OpenPIC);
     154      printk("OpenPIC found at %x.\n", OpenPIC);
    135155    }
    136156  }
     157#endif
    137158  if (OpenPIC == (volatile struct OpenPIC *)0) {
    138159    BSP_panic("OpenPic Not found\n");
    139160  }
    140 
    141161}
  • c/src/lib/libbsp/powerpc/shared/pci/pci.c

    rae460ec rbd91ff4e  
    22 * pci.c :  this file contains basic PCI Io functions.
    33 *
    4  *  CopyRight (C) 1999 valette@crf.canon.fr
     4 *  Copyright (C) 1999 valette@crf.canon.fr
    55 *
    6  *  This code is heavilly inspired by the public specification of STREAM V2
     6 *  This code is heavily inspired by the public specification of STREAM V2
    77 *  that can be found at :
    88 *
     
    218218
    219219
    220 
    221 
    222 
    223 
    224 
    225 
    226 
    227 
    228 
    229 
    230 
    231220#define PRINT_MSG() \
    232221             printk("pci : Device %d:%02x routed to interrupt_line %d\n", pbus, pslot, int_name )
     
    237226** the names defined in the routing record.
    238227*/
    239 static int test_intname( struct _int_map *row, int pbus, int pslot, int int_pin, int int_name )
     228static int test_intname(
     229  const struct _int_map *row,
     230  int pbus,
     231  int pslot,
     232  int int_pin,
     233  int int_name
     234)
    240235{
    241    int j,k;
     236   int j, k;
    242237   int _nopin= -1, _noname= -1;
    243238
     
    334329
    335330
    336 void FixupPCI( struct _int_map *bspmap, int (*swizzler)(int,int) )
     331void FixupPCI( const struct _int_map *bspmap, int (*swizzler)(int,int) )
    337332{
    338333   unsigned char        cvalue;
  • c/src/lib/libbsp/powerpc/shared/pci/pci.h

    rae460ec rbd91ff4e  
    11651165};
    11661166
    1167 void FixupPCI( struct _int_map *, int (*swizzler)(int,int) );
     1167void FixupPCI( const struct _int_map *, int (*swizzler)(int,int) );
    11681168
    11691169
  • c/src/lib/libbsp/powerpc/shared/start/start.S

    rae460ec rbd91ff4e  
    1515#include <rtems/score/cpu.h>
    1616#include <libcpu/io.h>
     17#include <bspopts.h>
    1718
    1819#define SYNC \
     
    2930        sc
    3031
    31                
    3232        .text
    3333        .globl  __rtems_entry_point
     
    6868 */
    6969        lis     r11,KERNELBASE@h
    70         ori     r11,r11,0x1ffe          /* set up BAT registers for 604 */
     70/* set up BAT registers for 604 */
     71        ori     r11,r11,0x1ffe         
    7172        li      r8,2                    /* R/W access */
    7273        isync
     74#if defined(mvme2100)
     75        /* BSP_vme_config() wants to use BAT0, this board will use the
     76         * available BAT1 to map RAM.
     77         */
     78        mtspr   DBAT1L,r8               /* N.B. 6xx (not 601) have valid */
     79        mtspr   DBAT1U,r11              /* bit in upper BAT register */
     80        mtspr   IBAT1L,r8
     81        mtspr   IBAT1U,r11
     82#else
    7383        mtspr   DBAT0L,r8               /* N.B. 6xx (not 601) have valid */
    7484        mtspr   DBAT0U,r11              /* bit in upper BAT register */
    7585        mtspr   IBAT0L,r8
    7686        mtspr   IBAT0U,r11
     87#endif
    7788        isync
    7889
     
    8899enter_C_code:
    89100        bl      MMUon
    90         bl  __eabi      /* setup EABI and SYSV environment */
     101        bl      __eabi  /* setup EABI and SYSV environment */
    91102        bl      zero_bss
    92103        /*
     
    106117        mr      r1, r9
    107118        /*
    108          * We are know in a environment that is totally independent from bootloader setup.
     119         * We are now in a environment that is totally independent from
     120         * bootloader setup.
    109121         */
    110122        lis     r5,environ@ha
     
    114126        bl      boot_card
    115127        bl      _return_to_ppcbug
    116        
     128
    117129        .globl  MMUon
    118130        .type   MMUon,@function
    119 MMUon: 
     131MMUon:
    120132        mfmsr   r0
     133        ori     r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP
     134#if defined(mvme2100)
     135        /* Data addr translation is broken for the mvme2100, disable it here */
     136        xori    r0,r0, MSR_DR
     137#endif
    121138#if (PPC_HAS_FPU == 0)
    122         ori     r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP
    123139        xori    r0, r0, MSR_EE | MSR_IP | MSR_FP
    124140#else
    125         ori     r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP
    126141        xori    r0, r0, MSR_EE | MSR_IP | MSR_FE0 | MSR_FE1
    127142#endif
     
    131146        SYNC
    132147        rfi
    133        
     148
    134149        .globl  MMUoff
    135150        .type   MMUoff,@function
    136 MMUoff: 
     151MMUoff: 
    137152        mfmsr   r0
    138153        ori     r0,r0,MSR_IR| MSR_DR | MSR_IP
  • c/src/lib/libbsp/powerpc/shared/startup/bspstart.c

    rae460ec rbd91ff4e  
    2020#include <string.h>
    2121
     22#include <bsp.h>
    2223#include <rtems/libio.h>
    2324#include <rtems/libcsupport.h>
     
    2930#include <bsp/irq.h>
    3031#include <bsp/VME.h>
    31 #include <bsp.h>
    3232#include <libcpu/bat.h>
    3333#include <libcpu/pte121.h>
     
    4949SPR_RW(SPRG1)
    5050
     51#if defined(DEBUG_BATS)
     52void printBAT( int bat, unsigned32 upper, unsigned32 lower )
     53{
     54  unsigned32 lowest_addr;
     55  unsigned32 size;
     56
     57  printk("BAT%d raw(upper=0x%08x, lower=0x%08x) ", bat, upper, lower );
     58
     59  lowest_addr = (upper & 0xFFFE0000);
     60  size = (((upper & 0x00001FFC) >> 2) + 1) * (128 * 1024);
     61  printk(" range(0x%08x, 0x%08x) %s%s %s%s%s%s %s\n",
     62    lowest_addr,
     63    lowest_addr + (size - 1),
     64    (upper & 0x01) ? "P" : "p",
     65    (upper & 0x02) ? "S" : "s",
     66    (lower & 0x08) ? "G" : "g",
     67    (lower & 0x10) ? "M" : "m",
     68    (lower & 0x20) ? "I" : "i",
     69    (lower & 0x40) ? "W" : "w",
     70    (lower & 0x01) ? "Read Only" :
     71      ((lower & 0x02) ? "Read/Write" : "No Access")
     72  );
     73}
     74
     75void ShowBATS(){
     76  unsigned32 lower;
     77  unsigned32 upper;
     78
     79  __MFSPR(536, upper); __MFSPR(537, lower); printBAT( 0, upper, lower );
     80  __MFSPR(538, upper); __MFSPR(539, lower); printBAT( 1, upper, lower );
     81  __MFSPR(540, upper); __MFSPR(541, lower); printBAT( 2, upper, lower );
     82  __MFSPR(542, upper); __MFSPR(543, lower); printBAT( 3, upper, lower );
     83}
     84#endif
     85
    5186/*
    5287 * Copy of residuals passed by firmware
     
    131166void bsp_pretasking_hook(void)
    132167{
    133     rtems_unsigned32        heap_start;   
    134     rtems_unsigned32        heap_size;
    135     rtems_unsigned32        heap_sbrk_spared;
    136         extern rtems_unsigned32 _bsp_sbrk_init(rtems_unsigned32, rtems_unsigned32*);
    137 
    138     heap_start = ((rtems_unsigned32) __rtems_end) +INIT_STACK_SIZE + INTR_STACK_SIZE;
    139     if (heap_start & (CPU_ALIGNMENT-1))
    140         heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
    141 
    142     heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size;
    143 
    144         heap_sbrk_spared=_bsp_sbrk_init(heap_start, &heap_size);
     168  rtems_unsigned32        heap_start;   
     169  rtems_unsigned32        heap_size;
     170  rtems_unsigned32        heap_sbrk_spared;
     171  extern rtems_unsigned32 _bsp_sbrk_init(rtems_unsigned32, rtems_unsigned32*);
     172
     173  heap_start = ((rtems_unsigned32) __rtems_end) +
     174                INIT_STACK_SIZE + INTR_STACK_SIZE;
     175  if (heap_start & (CPU_ALIGNMENT-1))
     176      heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
     177
     178  heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size;
     179  heap_sbrk_spared=_bsp_sbrk_init(heap_start, &heap_size);
    145180
    146181#ifdef SHOW_MORE_INIT_SETTINGS
    147         printk(" HEAP start %x  size %x (%x bytes spared for sbrk)\n", heap_start, heap_size, heap_sbrk_spared);
     182  printk( "HEAP start %x  size %x (%x bytes spared for sbrk)\n",
     183             heap_start, heap_size, heap_sbrk_spared);
    148184#endif   
    149185
    150     bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared);
    151 
     186  bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared);
    152187
    153188#ifdef RTEMS_DEBUG
    154     rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
     189  rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
    155190#endif
    156191}
     
    174209}
    175210
     211#if defined(mpc8240) || defined(mpc8245)
     212unsigned int EUMBBAR;
     213
     214/*
     215 * Return the current value of the Embedded Utilities Memory Block Base Address
     216 * Register (EUMBBAR) as read from the processor configuration register using
     217 * Processor Address Map B (CHRP).
     218 */
     219unsigned int get_eumbbar() {
     220  register int a, e;
     221
     222  asm volatile( "lis %0,0xfec0; ori  %0,%0,0x0000": "=r" (a) );
     223  asm volatile("sync");
     224                                                               
     225  asm volatile("lis %0,0x8000; ori %0,%0,0x0078": "=r"(e) );
     226  asm volatile("stwbrx  %0,0x0,%1": "=r"(e): "r"(a)); 
     227  asm volatile("sync");
     228
     229  asm volatile("lis %0,0xfee0; ori %0,%0,0x0000": "=r" (a) );
     230  asm volatile("sync");
     231                                                         
     232  asm volatile("lwbrx %0,0x0,%1": "=r" (e): "r" (a));
     233  asm volatile("isync");
     234  return e;
     235}
     236#endif
     237
    176238/*
    177239 *  bsp_start
     
    182244void bsp_start( void )
    183245{
    184   int err;
    185246  unsigned char *stack;
     247#if !defined(mpc8240) && !defined(mpc8245)
    186248  unsigned l2cr;
     249#endif
    187250  register unsigned char* intrStack;
    188251  unsigned char *work_space_start;
     
    192255  motorolaBoard myBoard;
    193256  Triv121PgTbl  pt=0;
    194   /*
    195    * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
    196    * store the result in global variables so that it can be used latter...
     257
     258  select_console(CONSOLE_SERIAL);
     259  /*
     260   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
     261   * function store the result in global variables so that it can be used
     262   * later...
    197263   */
    198264  myCpu         = get_ppc_cpu_type();
    199265  myCpuRevision = get_ppc_cpu_revision();
     266
     267#if defined(mvme2100)
     268  EUMBBAR = get_eumbbar();
     269
     270  Cpu_table.exceptions_in_RAM    = TRUE;
     271  { unsigned v = 0x3000 ; _CPU_MSR_SET(v); }
     272#endif
     273
     274#if !defined(mpc8240) && !defined(mpc8245)
    200275  /*
    201276   * enables L1 Cache. Note that the L1_caches_enables() codes checks for
     
    203278   */
    204279  L1_caches_enables();
     280
    205281  /*
    206282   * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for
     
    213289  if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1))
    214290    set_L2CR(0xb9A14000);
    215   /*
    216    * the initial stack  has aready been set to this value in start.S
     291#endif
     292
     293  /*
     294   * the initial stack has already been set to this value in start.S
    217295   * so there is no need to set it in r1 again... It is just for info
    218296   * so that It can be printed without accessing R1.
    219297   */
    220   stack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
    221 
    222  /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
     298  stack = ((unsigned char*) __rtems_end) +
     299               INIT_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
     300
     301  /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
    223302  *((unsigned32 *)stack) = 0;
    224303
     
    227306   * SPRG1 = software managed IRQ stack
    228307   *
    229    * This could be done latter (e.g in IRQ_INIT) but it helps to understand
     308   * This could be done later (e.g in IRQ_INIT) but it helps to understand
    230309   * some settings below...
    231310   */
    232   intrStack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
     311  intrStack = ((unsigned char*) __rtems_end) +
     312    INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
    233313
    234314  /* make sure it's properly aligned */
     
    244324
    245325  /*
    246    * Initialize default raw exception hanlders. See vectors/vectors_init.c
     326   * Initialize default raw exception handlers. See vectors/vectors_init.c
    247327   */
    248328  initialize_exceptions();
    249   /*
    250    * Init MMU block address translation to enable hardware
    251    * access
    252    */
    253   /*
    254    * PC legacy IO space used for inb/outb and all PC
    255    * compatible hardware
    256    */
    257   setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE);
    258   /*
    259    * PCI devices memory area. Needed to access OPENPIC features
    260    * provided by the RAVEN
    261    */
    262   /* T. Straumann: give more PCI address space */
    263   setdbat(2, PCI_MEM_BASE, PCI_MEM_BASE, 0x10000000, IO_PAGE);
    264   /*
    265    * Must have acces to open pic PCI ACK registers
    266    * provided by the RAVEN
    267    *
     329
     330  /*
     331   * Init MMU block address translation to enable hardware access
     332   */
     333#if !defined(mvme2100)
     334  /*
     335   * PC legacy IO space used for inb/outb and all PC compatible hardware
     336   */
     337   setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE);
     338#endif
     339
     340  /*
     341   * PCI devices memory area. Needed to access OpenPIC features
     342   * provided by the Raven
     343   *
     344   * T. Straumann: give more PCI address space
     345   */
     346   setdbat(2, PCI_MEM_BASE, PCI_MEM_BASE, 0x10000000, IO_PAGE);
     347
     348  /*
     349   * Must have access to OpenPIC PCI ACK registers provided by the Raven
    268350   */
    269351  setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
     
    271353  select_console(CONSOLE_LOG);
    272354
    273   /* We check that the keyboard is present and immediately
     355  /*
     356   * We check that the keyboard is present and immediately
    274357   * select the serial console if not.
    275358   */
    276   err = kbdreset();
    277   if (err) select_console(CONSOLE_SERIAL);
     359#if defined(BSP_KBD_IOBASE)
     360  { int err;
     361    err = kbdreset();
     362    if (err) select_console(CONSOLE_SERIAL);
     363  }
     364#else
     365  select_console(CONSOLE_SERIAL);
     366#endif
    278367
    279368  boardManufacturer   =  checkPrepBoardType(&residualCopy);
     
    285374 
    286375  printk("-----------------------------------------\n");
    287   printk("Welcome to %s on %s\n", _RTEMS_version, motorolaBoardToString(myBoard));
     376  printk("Welcome to %s on %s\n", _RTEMS_version,
     377                                    motorolaBoardToString(myBoard));
    288378  printk("-----------------------------------------\n");
    289379#ifdef SHOW_MORE_INIT_SETTINGS 
     
    309399  InitializePCI();
    310400
    311  {
    312     struct _int_map     *bspmap  = motorolaIntMap(currentBoard);
    313     if( bspmap )
    314     {
    315        printk("pci : Configuring interrupt routing for '%s'\n", motorolaBoardToString(currentBoard));
     401  {
     402    const struct _int_map *bspmap = motorolaIntMap(currentBoard);
     403    if( bspmap ) {
     404       printk("pci : Configuring interrupt routing for '%s'\n",
     405         motorolaBoardToString(currentBoard));
    316406       FixupPCI(bspmap, motorolaIntSwizzle(currentBoard) );
    317407    }
     
    320410 }
    321411
    322 
    323412#ifdef SHOW_MORE_INIT_SETTINGS
    324413  printk("Number of PCI buses found is : %d\n", BusCountPCI());
     
    331420  __asm__ __volatile ("sc");
    332421  /*
    333    * Check we can still catch exceptions and returned coorectly.
     422   * Check we can still catch exceptions and return correctly.
    334423   */
    335424  printk("Testing exception handling Part 2\n");
    336425  __asm__ __volatile ("sc");
     426
     427  /*
     428   *  Somehow doing the above seems to clobber SPRG0 on the mvme2100.  It
     429   *  is probably a not so subtle hint that you do not want to use PPCBug
     430   *  once RTEMS is up and running.  Anyway, we still needs to indicate
     431   *  that we have fixed PR288.  Eventually, this should go away.
     432   */
     433  _write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
    337434#endif 
    338435
    339 
    340   BSP_mem_size                          = residualCopy.TotalMemory;
    341   BSP_bus_frequency                     = residualCopy.VitalProductData.ProcessorBusHz;
    342   BSP_processor_frequency               = residualCopy.VitalProductData.ProcessorHz;
    343   BSP_time_base_divisor                 = (residualCopy.VitalProductData.TimeBaseDivisor?
    344                                            residualCopy.VitalProductData.TimeBaseDivisor : 4000);
     436  BSP_mem_size            = residualCopy.TotalMemory;
     437  BSP_bus_frequency       = residualCopy.VitalProductData.ProcessorBusHz;
     438  BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz;
     439  BSP_time_base_divisor   = (residualCopy.VitalProductData.TimeBaseDivisor?
     440                    residualCopy.VitalProductData.TimeBaseDivisor : 4000);
    345441
    346442  /* clear hostbridge errors but leave MCP disabled -
     
    348444   */
    349445  _BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/);
    350 
    351446
    352447  /* Allocate and set up the page table mappings
     
    359454  pt = BSP_pgtbl_setup(&BSP_mem_size);
    360455
    361   if (!pt ||
    362           TRIV121_MAP_SUCCESS != triv121PgTblMap(
    363                                                                                 pt,
    364                                                                                 TRIV121_121_VSID,
    365                                                                                 0xfeff0000,
    366                                                                                 1,
    367                                                                                 TRIV121_ATTR_IO_PAGE,
    368                                                                                 TRIV121_PP_RW_PAGE
    369                                                                                 )) {
    370         printk("WARNING: unable to setup page tables VME bridge must share PCI space\n");
     456  if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap(
     457            pt, TRIV121_121_VSID, 0xfeff0000, 1,
     458            TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) {
     459        printk("WARNING: unable to setup page tables VME "
     460               "bridge must share PCI space\n");
    371461  }
    372  
     462
    373463  /*
    374464   * Set up our hooks
     
    385475
    386476#ifdef SHOW_MORE_INIT_SETTINGS
    387   printk("BSP_Configuration.work_space_size = %x\n", BSP_Configuration.work_space_size);
     477  printk("BSP_Configuration.work_space_size = %x\n",
     478          BSP_Configuration.work_space_size);
    388479#endif 
    389480  work_space_start =
    390481    (unsigned char *)BSP_mem_size - BSP_Configuration.work_space_size;
    391482
    392   if ( work_space_start <= ((unsigned char *)__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE) {
     483  if ( work_space_start <=
     484       ((unsigned char *)__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE) {
    393485    printk( "bspstart: Not enough RAM!!!\n" );
    394486    bsp_cleanup();
     
    402494  BSP_rtems_irq_mng_init(0);
    403495
    404  
    405496  /* Activate the page table mappings only after
    406497   * initializing interrupts because the irq_mng_init()
     
    412503#endif
    413504    BSP_pgtbl_activate(pt);
    414         /* finally, switch off DBAT3 */
    415         setdbat(3, 0, 0, 0, 0);
     505    /* finally, switch off DBAT3 */
     506    setdbat(3, 0, 0, 0, 0);
    416507  }
    417508
    418509  /*
    419    * Initialize VME bridge - needs working PCI
    420    * and IRQ subsystems...
     510   * Initialize VME bridge - needs working PCI and IRQ subsystems...
    421511   */
    422512#ifdef SHOW_MORE_INIT_SETTINGS
    423513  printk("Going to initialize VME bridge\n");
    424514#endif
    425   /* VME initialization is in a separate file so apps which don't use
    426    * VME or want a different configuration may link against a customized
    427    * routine.
     515  /*
     516   * VME initialization is in a separate file so apps which don't use VME or
     517   * want a different configuration may link against a customized routine.
    428518   */
    429519  BSP_vme_config();
     520
     521
     522#if defined(DEBUG_BATS)
     523  ShowBATS();
     524#endif
    430525
    431526#ifdef SHOW_MORE_INIT_SETTINGS
  • c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c

    rae460ec rbd91ff4e  
    176176    BSP_panic("Exception handling initialization failed\n");
    177177  }
     178#ifdef RTEMS_DEBUG
    178179  else {
    179180    printk("Exception handling initialization done\n");
    180181  }
     182#endif
    181183}
  • c/src/lib/libbsp/powerpc/shared/vme/vmeconfig.c

    rae460ec rbd91ff4e  
    3535} dbat0u;
    3636
    37   if (currentBoard < MVME_2300 || currentBoard >= MVME_1600) {
    38                 printk("VME bridge for this board is unknown - if it's a Tundra Universe, add the board to 'shared/vme/vmeconfig.c'\n");
    39                 printk("Skipping VME initialization...\n");
    40                 return;
    41   }
    42 
    4337  vmeUniverseInit();
    4438  vmeUniverseReset();
    45 
    4639  /* setup a PCI area to map the VME bus */
    4740
     
    5043  /* if we have page tables, BAT0 is available */
    5144  if (dbat0u.bat.vs || dbat0u.bat.vp) {
    52         printk("WARNING: BAT0 is taken (no pagetables?); VME bridge must share PCI range for VME access\n");
    53         printk("Skipping VME initialization...\n");
     45        printk("WARNING: BAT0 is taken (no pagetables?); "
     46               "VME bridge must share PCI range for VME access\n"
     47               "Skipping VME initialization...\n");
    5448        return;
    5549  }
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