Changeset bd91ff4e in rtems
- Timestamp:
- Nov 10, 2004, 10:15:01 PM (16 years ago)
- Children:
- 9d8590d
- Parents:
- ae460ec
- Location:
- c/src/lib/libbsp/powerpc/shared
- Files:
-
- 3 added
- 25 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/powerpc/shared/ChangeLog
rae460ec rbd91ff4e 1 2004-11-10 Richard Campbell <richard.campbell@oarcorp.com> 2 3 * ChangeLog, Makefile.am, bootloader/misc.c, bootloader/pci.c, 4 bootloader/pci.h, console/console.c, console/inch.c, 5 console/reboot.c, console/uart.c, console/uart.h, include/bsp.h, 6 irq/irq.c, irq/irq.h, irq/irq_init.c, motorola/motorola.c, 7 motorola/motorola.h, openpic/openpic.c, openpic/openpic.h, 8 pci/detect_raven_bridge.c, pci/pci.c, pci/pci.h, start/start.S, 9 startup/bspstart.c, vectors/vectors_init.c, vme/vmeconfig.c: Add 10 MVME2100 BSP and MPC8240 support. There was also a significant amount 11 of spelling and whitespace cleanup. 12 * tod/.cvsignore, tod/Makefile.am, tod/todcfg.c: New files. 13 14 2004-11-10 Richard Campbell <richard.campbell@oarcorp.com> 15 16 * Makefile.am, bootloader/misc.c, bootloader/pci.c, bootloader/pci.h, 17 console/console.c, console/inch.c, console/reboot.c, console/uart.c, 18 console/uart.h, include/bsp.h, irq/irq.c, irq/irq.h, irq/irq_init.c, 19 motorola/motorola.c, motorola/motorola.h, openpic/openpic.c, 20 openpic/openpic.h, pci/detect_raven_bridge.c, pci/pci.c, pci/pci.h, 21 start/start.S, startup/bspstart.c, vectors/vectors_init.c, 22 vme/vmeconfig.c: Add MVME2100 BSP and MPC8240 support. 23 * tod/.cvsignore, tod/Makefile.am, tod/todcfg.c: New files. 24 1 25 2004-09-27 Greg Menke <gregory.menke@gsfc.nasa.gov> 2 26 -
c/src/lib/libbsp/powerpc/shared/Makefile.am
rae460ec rbd91ff4e 6 6 if need_shared 7 7 SUBDIRS = clock console include pci residual openpic irq vectors start \ 8 startup motorola bootloader vme 8 startup motorola bootloader vme tod 9 9 endif 10 10 -
c/src/lib/libbsp/powerpc/shared/bootloader/misc.c
rae460ec rbd91ff4e 25 25 #include <libcpu/byteorder.h> 26 26 #include <rtems/bspIo.h> 27 #include <bsp.h> 27 28 28 29 SPR_RW(DEC) … … 281 282 * select the serial console if not. 282 283 */ 284 #if defined(BSP_KBD_IOBASE) 283 285 err = kbdreset(); 284 if (err) select_console(CONSOLE_SERIAL); 286 if (err) select_console(CONSOLE_SERIAL); 287 #else 288 err = 1; 289 select_console(CONSOLE_SERIAL); 290 #endif 285 291 286 292 printk("\nModel: %s\nSerial: %s\n" … … 294 300 (vpd.TimeBaseDivisor ? vpd.TimeBaseDivisor : 4000), 295 301 res->TotalMemory); 296 printk("Original MSR: %lx\nOriginal HID0: %lx\nOriginal R31: %lx\n",297 bd->o_msr, bd->o_hid0, bd->o_r31);298 302 299 303 /* This reconfigures all the PCI subsystem */ -
c/src/lib/libbsp/powerpc/shared/bootloader/pci.c
rae460ec rbd91ff4e 25 25 #include <libcpu/page.h> 26 26 #include <bsp/consoleIo.h> 27 #include <string.h> 27 28 28 29 typedef unsigned int u32; -
c/src/lib/libbsp/powerpc/shared/bootloader/pci.h
rae460ec rbd91ff4e 498 498 #define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001 499 499 #define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 500 #define PCI_DEVICE_ID_MOTOROLA_MPC8240 0x0003 500 501 #define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801 501 502 -
c/src/lib/libbsp/powerpc/shared/console/console.c
rae460ec rbd91ff4e 75 75 }, 76 76 }; 77 78 77 79 78 /*-------------------------------------------------------------------------+ … … 136 135 137 136 } 137 138 138 return RTEMS_SUCCESSFUL; 139 139 } /* console_initialize */ … … 175 175 rtems_status_code status; 176 176 static rtems_termios_callbacks cb = 177 #if defined(USE_POLLED_IO) 178 { 179 NULL, /* firstOpen */ 180 NULL, /* lastClose */ 181 NULL, /* pollRead */ 182 BSP_uart_termios_write_polled, /* write */ 183 conSetAttr, /* setAttributes */ 184 NULL, /* stopRemoteTx */ 185 NULL, /* startRemoteTx */ 186 0 /* outputUsesInterrupts */ 187 }; 188 #else 177 189 { 178 190 console_first_open, /* firstOpen */ 179 191 console_last_close, /* lastClose */ 180 NULL, 181 BSP_uart_termios_write_com, /* write */182 conSetAttr, 183 NULL, 184 NULL, 185 1 192 NULL, /* pollRead */ 193 BSP_uart_termios_write_com, /* write */ 194 conSetAttr, /* setAttributes */ 195 NULL, /* stopRemoteTx */ 196 NULL, /* startRemoteTx */ 197 1 /* outputUsesInterrupts */ 186 198 }; 199 #endif 187 200 188 201 status = rtems_termios_open (major, minor, arg, &cb); … … 190 203 if(status != RTEMS_SUCCESSFUL) 191 204 { 192 printk("Error open ning console device\n");205 printk("Error opening console device\n"); 193 206 return status; 194 207 } -
c/src/lib/libbsp/powerpc/shared/console/inch.c
rae460ec rbd91ff4e 21 21 22 22 #include <bsp.h> 23 #if defined(BSP_KBD_IOBASE) 23 24 #include <bsp/irq.h> 24 25 … … 300 301 return c; 301 302 } /* _IBMPC_inch */ 302 303 304 305 306 307 303 #endif -
c/src/lib/libbsp/powerpc/shared/console/reboot.c
rae460ec rbd91ff4e 17 17 CPU_print_stack(); 18 18 /* shutdown and reboot */ 19 #if defined(BSP_KBD_IOBASE) 19 20 kbd_outb(0x4, 0xFE); /* use keyboard controler to do the job... */ 21 #endif 20 22 } /* rtemsReboot */ -
c/src/lib/libbsp/powerpc/shared/console/uart.c
rae460ec rbd91ff4e 133 133 { 134 134 unsigned char tmp; 135 135 136 136 /* Sanity check */ 137 137 SANITY_CHECK(uart); … … 157 157 return; 158 158 } 159 159 160 160 /* Set DLAB bit to 1 */ 161 161 uwrite(uart, LCR, DLAB); 162 162 163 163 /* Set baud rate */ 164 164 uwrite(uart, DLL, (BSPBaseBaud/baud) & 0xff); … … 186 186 uart_data[uart].hwFlow = hwFlow; 187 187 uart_data[uart].baud = baud; 188 188 189 return; 189 190 } … … 202 203 /* 203 204 * This function may be called whenever TERMIOS parameters 204 * are changed, so we have to make s ire that baud change is205 * are changed, so we have to make sure that baud change is 205 206 * indeed required 206 207 */ … … 461 462 uart_isr_is_on(const rtems_irq_connect_data *irq) 462 463 { 463 int uart = (irq->name == BSP_ISA_UART_COM1_IRQ) ? 464 int uart; 465 466 #if defined(mvme2100) 467 uart = BSP_UART_COM1; 468 #else 469 uart = (irq->name == BSP_ISA_UART_COM1_IRQ) ? 464 470 BSP_UART_COM1 : BSP_UART_COM2; 471 #endif 465 472 return uread(uart,IER); 466 473 } … … 470 477 { 471 478 rtems_irq_connect_data d={0}; 479 #if defined(mvme2100) 480 d.name = BSP_UART_COM1_IRQ; 481 #else 472 482 d.name = (uart == BSP_UART_COM1) ? 473 483 BSP_ISA_UART_COM1_IRQ : BSP_ISA_UART_COM2_IRQ; 484 #endif 474 485 d.off = d.on = uart_noop; 475 486 d.isOn = uart_isr_is_on; … … 527 538 528 539 int 540 BSP_uart_termios_write_polled(int minor, const char *buf, int len) 541 { 542 int uart=minor; /* could differ, theoretically */ 543 int nwrite; 544 const char *b = buf; 545 546 assert(buf != NULL); 547 548 for (nwrite=0 ; nwrite < len ; nwrite++) { 549 BSP_uart_polled_write(uart, *b++); 550 } 551 return nwrite; 552 } 553 554 int 529 555 BSP_uart_termios_write_com(int minor, const char *buf, int len) 530 556 { … … 537 563 } 538 564 539 /* If the reTX buffer is busy - something is royally screwed up */565 /* If the TX buffer is busy - something is royally screwed up */ 540 566 /* assert((uread(BSP_UART_COM1, LSR) & THRE) != 0); */ 541 567 -
c/src/lib/libbsp/powerpc/shared/console/uart.h
rae460ec rbd91ff4e 17 17 18 18 void BSP_uart_init(int uart, int baud, int hwFlow); 19 void BSP_uart_set_baud(int aurt, int baud);19 void BSP_uart_set_baud(int uart, int baud); 20 20 void BSP_uart_intr_ctrl(int uart, int cmd); 21 21 void BSP_uart_throttle(int uart); … … 32 32 int BSP_uart_install_isr(int uart, rtems_irq_hdl handler); 33 33 int BSP_uart_remove_isr(int uart, rtems_irq_hdl handler); 34 int BSP_uart_termios_write_polled(int minor, const char *buf, int len); 34 35 int BSP_uart_get_break_cb(int uart, rtems_libio_ioctl_args_t *arg); 35 36 int BSP_uart_set_break_cb(int uart, rtems_libio_ioctl_args_t *arg); -
c/src/lib/libbsp/powerpc/shared/include/bsp.h
rae460ec rbd91ff4e 27 27 */ 28 28 29 #if defined(mvme2100) 30 #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 1 31 #else 29 32 #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 33 #endif 34 30 35 #define CONFIGURE_INTERRUPT_STACK_MEMORY (16 * 1024) 31 36 32 /* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */ 33 #define _IO_BASE PREP_ISA_IO_BASE 37 /* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */ 38 #if defined(mvme2100) 39 #define _IO_BASE CHRP_ISA_IO_BASE 40 #define _ISA_MEM_BASE CHRP_ISA_MEM_BASE 41 /* address of our ram on the PCI bus */ 42 #define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET 43 #define PCI_MEM_BASE 0x80000000 44 #define PCI_MEM_BASE_ADJUSTMENT 0 45 46 #else 47 #define _IO_BASE PREP_ISA_IO_BASE 34 48 #define _ISA_MEM_BASE PREP_ISA_MEM_BASE 35 49 /* address of our ram on the PCI bus */ … … 37 51 /* offset of pci memory as seen from the CPU */ 38 52 #define PCI_MEM_BASE PREP_ISA_MEM_BASE 39 40 /* 41 * base address definitions for several devices 42 * 43 */ 53 #define PCI_MEM_BASE_ADJUSTMENT PREP_ISA_MEM_BASE 54 #endif 55 56 /* 57 * Base address definitions for several devices 58 * 59 * MVME2100 is very similar but has fewer devices and uses on-CPU EPIC 60 * implementation of OpenPIC controller. It also cannot be probed to 61 * find out what it is which is VERY different from other Motorola boards. 62 */ 63 64 #if defined(mvme2100) 65 #define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x01e10000) 66 /* #define BSP_UART_IOBASE_COM1 (0xffe10000) */ 67 #define BSP_OPEN_PIC_BASE_OFFSET 0x40000 68 69 #define MVME_HAS_DEC21140 70 #else 44 71 #define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x3f8) 45 72 #define BSP_UART_IOBASE_COM2 ((_IO_BASE)+0x2f8) 73 46 74 #define BSP_KBD_IOBASE ((_IO_BASE)+0x60) 47 75 #define BSP_VGA_IOBASE ((_IO_BASE)+0x3c0) 48 76 77 #if defined(mvme2300) 78 #define MVME_HAS_DEC21140 79 #endif 80 #endif 81 82 #define BSP_UART_BAUD_BASE 115200 49 83 #define BSP_CONSOLE_PORT BSP_UART_COM1 50 #define BSP_UART_BAUD_BASE 115200 84 85 #if defined(MVME_HAS_DEC21140) 86 struct rtems_bsdnet_ifconfig; 87 int rtems_dec21140_driver_attach (struct rtems_bsdnet_ifconfig *, int); 88 89 #define RTEMS_BSP_NETWORK_DRIVER_NAME "dc1" 90 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_dec21140_driver_attach 91 #endif 51 92 52 93 #include <bsp/openpic.h> -
c/src/lib/libbsp/powerpc/shared/irq/irq.c
rae460ec rbd91ff4e 22 22 #include <libcpu/io.h> 23 23 #include <bsp/vectors.h> 24 #include <stdlib.h> 24 25 25 26 #include <rtems/bspIo.h> /* for printk */ … … 29 30 * pointer to the mask representing the additionnal irq vectors 30 31 * that must be disabled when a particular entry is activated. 31 * They will be dynamically computed from t eh prioruty table given32 * They will be dynamically computed from the priority table given 32 33 * in BSP_rtems_irq_mngt_set(); 33 34 * CAUTION : this table is accessed directly by interrupt routine … … 68 69 69 70 /* 70 * Check if IRQ is a P orcessor IRQ71 * Check if IRQ is a Processor IRQ 71 72 */ 72 73 static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine) … … 127 128 unsigned int level; 128 129 rtems_irq_connect_data* vchain; 129 130 130 131 if (!isValidInterrupt(irq->name)) { 131 132 printk("Invalid interrupt vector %d\n",irq->name); … … 192 193 { 193 194 unsigned int level; 194 195 195 196 if (!isValidInterrupt(irq->name)) { 196 197 printk("Invalid interrupt vector %d\n",irq->name); … … 364 365 365 366 /* 366 * ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------367 * RTEMS Global Interrupt Handler Management Routines 367 368 */ 368 369 … … 518 519 register unsigned new_msr; 519 520 520 521 521 if (excNum == ASM_DEC_VECTOR) { 522 522 _CPU_MSR_GET(msr); … … 528 528 _CPU_MSR_SET(msr); 529 529 return; 530 531 } 530 } 531 532 532 irq = openpic_irq(0); 533 533 if (irq == OPENPIC_VEC_SPURIOUS) { -
c/src/lib/libbsp/powerpc/shared/irq/irq.h
rae460ec rbd91ff4e 2 2 * 3 3 * This include file describe the data structure and the functions implemented 4 * by rtemsto write interrupt handlers.5 * 6 * Copy Right (C) 1999 valette@crf.canon.fr4 * by RTEMS to write interrupt handlers. 5 * 6 * Copyright (C) 1999 valette@crf.canon.fr 7 7 * 8 8 * This code is heavilly inspired by the public specification of STREAM V2 … … 21 21 #ifndef LIBBSP_POWERPC_MCP750_IRQ_IRQ_H 22 22 #define LIBBSP_POWERPC_MCP750_IRQ_IRQ_H 23 24 23 25 24 /* … … 66 65 67 66 /* 68 * Symb lolic IRQ names and related definitions.67 * Symbolic IRQ names and related definitions. 69 68 */ 70 69 71 70 typedef enum { 72 71 /* Base vector for our ISA IRQ handlers. */ 73 BSP_ISA_IRQ_VECTOR_BASE = 72 BSP_ISA_IRQ_VECTOR_BASE = BSP_ASM_IRQ_VECTOR_BASE, 74 73 /* 75 74 * ISA IRQ handler related definitions 76 75 */ 77 BSP_ISA_IRQ_NUMBER = 78 BSP_ISA_IRQ_LOWEST_OFFSET = 79 BSP_ISA_IRQ_MAX_OFFSET = 76 BSP_ISA_IRQ_NUMBER = 16, 77 BSP_ISA_IRQ_LOWEST_OFFSET = 0, 78 BSP_ISA_IRQ_MAX_OFFSET = BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1, 80 79 /* 81 80 * PCI IRQ handlers related definitions 82 81 * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE 83 82 */ 84 BSP_PCI_IRQ_NUMBER = 85 BSP_PCI_IRQ_LOWEST_OFFSET = 86 BSP_PCI_IRQ_MAX_OFFSET = 87 /* 88 * PowerP c exceptions handled as interrupt where a rtemsmanaged interrupt83 BSP_PCI_IRQ_NUMBER = 16, 84 BSP_PCI_IRQ_LOWEST_OFFSET = BSP_ISA_IRQ_NUMBER, 85 BSP_PCI_IRQ_MAX_OFFSET = BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1, 86 /* 87 * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt 89 88 * handler might be connected 90 89 */ 91 BSP_PROCESSOR_IRQ_NUMBER = 92 BSP_PROCESSOR_IRQ_LOWEST_OFFSET = 93 BSP_PROCESSOR_IRQ_MAX_OFFSET = 90 BSP_PROCESSOR_IRQ_NUMBER = 1, 91 BSP_PROCESSOR_IRQ_LOWEST_OFFSET = BSP_PCI_IRQ_MAX_OFFSET + 1, 92 BSP_PROCESSOR_IRQ_MAX_OFFSET = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1, 94 93 /* Misc vectors for OPENPIC irqs (IPI, timers) 95 94 */ 96 BSP_MISC_IRQ_NUMBER = 97 BSP_MISC_IRQ_LOWEST_OFFSET = 98 BSP_MISC_IRQ_MAX_OFFSET = 95 BSP_MISC_IRQ_NUMBER = 8, 96 BSP_MISC_IRQ_LOWEST_OFFSET = BSP_PROCESSOR_IRQ_MAX_OFFSET + 1, 97 BSP_MISC_IRQ_MAX_OFFSET = BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1, 99 98 /* 100 99 * Summary 101 100 */ 102 BSP_IRQ_NUMBER = 103 BSP_LOWEST_OFFSET = 104 BSP_MAX_OFFSET = 101 BSP_IRQ_NUMBER = BSP_MISC_IRQ_MAX_OFFSET + 1, 102 BSP_LOWEST_OFFSET = BSP_ISA_IRQ_LOWEST_OFFSET, 103 BSP_MAX_OFFSET = BSP_MISC_IRQ_MAX_OFFSET, 105 104 /* 106 105 * Some ISA IRQ symbolic name definition 107 */ 108 BSP_ISA_PERIODIC_TIMER = 0, 109 110 BSP_ISA_KEYBOARD = 1, 111 112 BSP_ISA_UART_COM2_IRQ = 3, 113 114 BSP_ISA_UART_COM1_IRQ = 4, 115 116 BSP_ISA_RT_TIMER1 = 8, 117 118 BSP_ISA_RT_TIMER3 = 10, 106 */ 107 BSP_ISA_PERIODIC_TIMER = 0, 108 BSP_ISA_KEYBOARD = 1, 109 BSP_ISA_UART_COM2_IRQ = 3, 110 BSP_ISA_UART_COM1_IRQ = 4, 111 BSP_ISA_RT_TIMER1 = 8, 112 BSP_ISA_RT_TIMER3 = 10, 119 113 /* 120 114 * Some PCI IRQ symbolic name definition 121 115 */ 122 BSP_PCI_IRQ0 = BSP_PCI_IRQ_LOWEST_OFFSET, 123 BSP_PCI_ISA_BRIDGE_IRQ = BSP_PCI_IRQ0, 116 BSP_PCI_IRQ0 = BSP_PCI_IRQ_LOWEST_OFFSET, 117 BSP_PCI_ISA_BRIDGE_IRQ = BSP_PCI_IRQ0, 118 119 #if defined(mvme2100) 120 BSP_DEC21143_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 1, 121 BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 2, 122 BSP_PCMIP_TYPE1_SLOT1_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 3, 123 BSP_PCMIP_TYPE2_SLOT0_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 4, 124 BSP_PCMIP_TYPE2_SLOT1_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 5, 125 BSP_PCI_INTA_UNIVERSE_LINT0_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 7, 126 BSP_PCI_INTB_UNIVERSE_LINT1_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 8, 127 BSP_PCI_INTC_UNIVERSE_LINT2_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 9, 128 BSP_PCI_INTD_UNIVERSE_LINT3_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 10, 129 BSP_UART_COM1_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 13, 130 BSP_FRONT_PANEL_ABORT_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 14, 131 BSP_RTC_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 15, 132 #endif 133 124 134 /* 125 * Some Processor ex ecption handled as rtemsIRQ symbolic name definition135 * Some Processor exception handled as RTEMS IRQ symbolic name definition 126 136 */ 127 BSP_DECREMENTER = BSP_PROCESSOR_IRQ_LOWEST_OFFSET 128 129 }rtems_irq_symbolic_name; 130 131 132 137 BSP_DECREMENTER = BSP_PROCESSOR_IRQ_LOWEST_OFFSET 138 139 } rtems_irq_symbolic_name; 133 140 134 141 /* … … 163 170 * RTEMS may well need such a function when restoring normal interrupt 164 171 * processing after a debug session. 165 *166 172 */ 167 173 rtems_irq_enable on; … … 206 212 /* 207 213 * software priorities associated with interrupts. 208 * if irqPrio [i] > intrPrio [j] it means that 214 * if irqPrio [i] > intrPrio [j] it means that 209 215 * interrupt handler hdl connected for interrupt name i 210 216 * will not be interrupted by the handler connected for interrupt j … … 237 243 int BSP_irq_enable_at_i8259s (const rtems_irq_symbolic_name irqLine); 238 244 /* 239 * function to ackno ledge a particular irq at 8259 level. After calling245 * function to acknowledge a particular irq at 8259 level. After calling 240 246 * this function, if a device asserts an enabled interrupt line it will 241 * be propagated further to the processor. Mainly useful lfor people242 * writ ting raw handlers as this is automagically done for rtemsmanaged247 * be propagated further to the processor. Mainly useful for people 248 * writing raw handlers as this is automagically done for RTEMS managed 243 249 * handlers. 244 250 */ … … 261 267 * 4) modify them to disable the current interrupt at 8259 level (and may 262 268 * be others depending on software priorities) 263 * 5) a knowledge the i8259s',269 * 5) acknowledge the i8259s', 264 270 * 6) demask the processor, 265 271 * 7) call the application handler … … 268 274 * 269 275 * a) can perfectly be written is C, 270 * b) may also well directly call the part of the RTEMS API that can be used271 * 272 * c) It only responsible for handling the jobs that need to be done at273 * the device level including (aknowledging/re-enabling the interrupt at device,274 * 276 * b) may also well directly call the part of the RTEMS API that can be 277 * used from interrupt level, 278 * c) It is only responsible for handling the jobs that need to be done at 279 * the device level including (acknowledging/re-enabling the interrupt 280 * at the device level, getting the data,...) 275 281 * 276 282 * When returning from the function, the following will be performed by … … 283 289 * 5) restore the C scratch registers... 284 290 * 6) restore initial execution flow 285 *286 291 */ 287 292 int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*); … … 297 302 /* 298 303 * function to get disconnect the RTEMS irq handler for ptr->name. 299 * This function checks that the value given is the current one for safety reason. 304 * This function checks that the value given is the current one for safety 305 * reasons. 300 306 * The user can use the previous function to get it. 301 307 */ … … 330 336 */ 331 337 int BSP_rtems_irq_mngt_get(rtems_irq_global_settings**); 332 338 333 339 extern void BSP_rtems_irq_mng_init(unsigned cpuId); 334 340 extern void BSP_i8259s_init(void); -
c/src/lib/libbsp/powerpc/shared/irq/irq_init.c
rae460ec rbd91ff4e 29 29 #include <bsp/motorola.h> 30 30 #include <rtems/bspIo.h> 31 32 /*33 #define SHOW_ISA_PCI_BRIDGE_SETTINGS34 */35 31 36 32 typedef struct { … … 69 65 static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={ 70 66 /* 71 * actual rpiorities for interrupt :67 * actual priorities for interrupt : 72 68 * 0 means that only current interrupt is masked 73 69 * 255 means all other interrupts are masked … … 76 72 * ISA interrupts. 77 73 * The second entry has a priority of 255 because 78 * it is the slave pic entry and isshould always remain74 * it is the slave pic entry and should always remain 79 75 * unmasked. 80 76 */ … … 92 88 }; 93 89 90 #if defined(mvme2100) 91 static unsigned char mvme2100_openpic_initpolarities[16] = { 92 0, /* Not used - should be disabled */ 93 0, /* DEC21143 Controller */ 94 0, /* PMC/PC-MIP Type I Slot 0 */ 95 0, /* PC-MIP Type I Slot 1 */ 96 0, /* PC-MIP Type II Slot 0 */ 97 0, /* PC-MIP Type II Slot 1 */ 98 0, /* Not used - should be disabled */ 99 0, /* PCI Expansion Interrupt A/Universe II (LINT0) */ 100 0, /* PCI Expansion Interrupt B/Universe II (LINT1) */ 101 0, /* PCI Expansion Interrupt C/Universe II (LINT2) */ 102 0, /* PCI Expansion Interrupt D/Universe II (LINT3) */ 103 0, /* Not used - should be disabled */ 104 0, /* Not used - should be disabled */ 105 1, /* 16550 UART */ 106 0, /* Front panel Abort Switch */ 107 0, /* RTC IRQ */ 108 }; 109 110 static unsigned char mvme2100_openpic_initsenses[] = { 111 0, /* Not used - should be disabled */ 112 1, /* DEC21143 Controller */ 113 1, /* PMC/PC-MIP Type I Slot 0 */ 114 1, /* PC-MIP Type I Slot 1 */ 115 1, /* PC-MIP Type II Slot 0 */ 116 1, /* PC-MIP Type II Slot 1 */ 117 0, /* Not used - should be disabled */ 118 1, /* PCI Expansion Interrupt A/Universe II (LINT0) */ 119 1, /* PCI Expansion Interrupt B/Universe II (LINT1) */ 120 1, /* PCI Expansion Interrupt C/Universe II (LINT2) */ 121 1, /* PCI Expansion Interrupt D/Universe II (LINT3) */ 122 0, /* Not used - should be disabled */ 123 0, /* Not used - should be disabled */ 124 1, /* 16550 UART */ 125 0, /* Front panel Abort Switch */ 126 1, /* RTC IRQ */ 127 }; 128 #else 94 129 static unsigned char mcp750_openpic_initpolarities[16] = { 95 130 1, /* 8259 cascade */ … … 115 150 1, /* MCP750_INT_PCI_BUS2_INTD */ 116 151 }; 152 #endif 117 153 118 154 void VIA_isa_bridge_interrupts_setup(void) … … 227 263 void BSP_rtems_irq_mng_init(unsigned cpuId) 228 264 { 265 #if !defined(mvme2100) 266 int known_cpi_isa_bridge = 0; 267 #endif 229 268 rtems_raw_except_connect_data vectorDesc; 230 int known_cpi_isa_bridge = 0;231 269 int i; 232 270 … … 234 272 * First initialize the Interrupt management hardware 235 273 */ 236 #ifdef TRACE_IRQ_INIT 274 #if defined(mvme2100) 275 #ifdef TRACE_IRQ_INIT 276 printk("Going to initialize EPIC interrupt controller (openpic compliant)\n"); 277 #endif 278 openpic_init(1, mvme2100_openpic_initpolarities, mvme2100_openpic_initsenses); 279 #else 280 #ifdef TRACE_IRQ_INIT 237 281 printk("Going to initialize raven interrupt controller (openpic compliant)\n"); 238 #endif 282 #endif 239 283 openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses); 284 #endif 285 286 #if !defined(mvme2100) 240 287 #ifdef TRACE_IRQ_INIT 241 288 printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n"); … … 262 309 printk("Going to initialize the ISA PC legacy IRQ management hardware\n"); 263 310 #endif 311 264 312 BSP_i8259s_init(); 265 /* 266 * Initialize Rtems management interrupt table 313 #endif 314 315 /* 316 * Initialize RTEMS management interrupt table 267 317 */ 268 318 /* … … 310 360 BSP_panic("Unable to initialize RTEMS external raw exception\n"); 311 361 } 312 #ifdef TRACE_IRQ_INIT 313 printk("RTEMS IRQ management is now operation nal\n");362 #ifdef TRACE_IRQ_INIT 363 printk("RTEMS IRQ management is now operational\n"); 314 364 #endif 315 365 } -
c/src/lib/libbsp/powerpc/shared/motorola/motorola.c
rae460ec rbd91ff4e 13 13 */ 14 14 15 15 #include <bsp.h> 16 16 #include <bsp/motorola.h> 17 17 #include <rtems/bspIo.h> … … 21 21 22 22 /* 23 ** Board-specific table that maps interrupt names to onboard pci24 ** peripherals as well as local pcibusses. This table is used at23 ** Board-specific table that maps interrupt names to onboard PCI 24 ** peripherals as well as local PCI busses. This table is used at 25 25 ** bspstart() to configure the interrupt name & pin for all devices that 26 26 ** do not have it already specified. If the device is already … … 117 117 NULL_INTMAP }; 118 118 119 120 121 122 123 124 119 static struct _int_map mvme2100_intmap[] = { 120 {0, 0, 0, {{1, {16,-1,-1,-1}}, /* something shows up in slot 0 and OpenPIC */ 121 /* 0 is unused. This hushes the init code. */ 122 NULL_PINMAP}}, 123 124 {0, 13, 0, {{1, {23,24,25,26}}, /* PCI INT[A-D]/Universe Lint[0-3] */ 125 NULL_PINMAP}}, 126 127 {0, 14, 0, {{1, {17,-1,-1,-1}}, /* onboard ethernet */ 128 NULL_PINMAP}}, 129 130 NULL_INTMAP }; 125 131 126 132 /* … … 141 147 return prep_pci_intpins[ slot % 4 ][ pin-1 ]; 142 148 } 143 144 145 146 147 148 149 150 151 149 152 150 typedef struct { … … 163 161 int (*swizzler)(int, int); 164 162 } mot_info_t; 165 166 163 167 164 static const mot_info_t mot_boards[] = { … … 186 183 {0x1E0, 0xFE, "MVME 3600 with MVME761", NULL, NULL}, 187 184 {0x1E0, 0xFF, "MVME 1600-001 or 1600-011", NULL, NULL}, 188 {0x000, 0x00, ""} 185 {0x000, 0x00, ""}, /* end of probeable values for automatic scan */ 186 {0x000, 0x00, "MVME 2100", mvme2100_intmap, prep_pci_swizzle}, 189 187 }; 190 188 191 192 193 189 prep_t currentPrepType; 194 motorolaBoard currentBoard; 190 motorolaBoard currentBoard; 191 195 192 prep_t checkPrepBoardType(RESIDUAL *res) 196 193 { … … 214 211 } 215 212 216 motorolaBoard getMotorolaBoard() 217 { 213 motorolaBoard getMotorolaBoard() 214 { 215 /* 216 * At least the MVME2100 does not have the CPU Type and Base Type Registers, 217 * so it cannot be probed. 218 * 219 * NOTE: Every path must set currentBoard. 220 */ 221 #if defined(mvme2100) 222 currentBoard = (motorolaBoard) MVME_2100; 223 #else 218 224 unsigned char cpu_type; 219 225 unsigned char base_mod; 220 226 int entry; 221 227 int mot_entry = -1; 222 228 223 229 cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0; 224 230 base_mod = inb(MOTOROLA_BASETYPE_REG); … … 235 241 if (mot_boards[entry].base_type != base_mod) 236 242 continue; 237 else {243 else { 238 244 mot_entry = entry; 239 245 break; … … 248 254 } 249 255 currentBoard = (motorolaBoard) mot_entry; 256 #endif 250 257 return currentBoard; 251 258 } … … 262 269 { 263 270 if (board == MOTOROLA_UNKNOWN) return NULL; 271 /* printk( "IntMap board %d 0x%08x\n", board, mot_boards[board].intmap ); */ 264 272 return mot_boards[board].intmap; 265 273 } -
c/src/lib/libbsp/powerpc/shared/motorola/motorola.h
rae460ec rbd91ff4e 53 53 MVME_3600_W_MVME761 = 18, 54 54 MVME_1600 = 19, 55 /* In the table, slot 20 is the marker for end of automatic probe and scan */ 56 MVME_2100 = 21, 55 57 MOTOROLA_UNKNOWN = 255 56 58 } motorolaBoard; … … 60 62 HOST_BRIDGE_HAWK = 1, 61 63 HOST_BRIDGE_UNKNOWN = 255 62 } motorolaHostBridge;64 } motorolaHostBridge; 63 65 64 66 #define MOTOROLA_CPUTYPE_REG 0x800 -
c/src/lib/libbsp/powerpc/shared/openpic/openpic.c
rae460ec rbd91ff4e 21 21 22 22 #include <rtems.h> 23 #include <bsp.h> 23 24 #include <rtems/bspIo.h> 24 25 #include <bsp/openpic.h> … … 26 27 #include <libcpu/io.h> 27 28 #include <libcpu/byteorder.h> 28 #include <bsp.h>29 29 #include <rtems/bspIo.h> 30 30 … … 199 199 200 200 /* Kludge for the Raven */ 201 /* 201 202 pci_read_config_dword(0, 0, 0, 0, &t); 203 */ 202 204 if (t == PCI_VENDOR_ID_MOTOROLA + (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) { 203 205 vendor = "Motorola"; … … 480 482 void openpic_initirq(unsigned int irq, unsigned int pri, unsigned int vec, int pol, int sense) 481 483 { 484 #if 0 485 printk("openpic_initirq: irq=%d pri=%d vec=%d pol=%d sense=%d\n", 486 irq, pri, vec, pol, sense); 487 #endif 488 482 489 check_arg_irq(irq); 483 490 check_arg_pri(pri); -
c/src/lib/libbsp/powerpc/shared/openpic/openpic.h
rae460ec rbd91ff4e 38 38 #define _RTEMS_OPENPIC_H 39 39 40 41 40 /* 42 41 * OpenPIC supports up to 2048 interrupt sources and up to 32 processors 43 42 */ 44 43 44 #if defined(mpc8240) || defined(mpc8245) 45 #define OPENPIC_MAX_SOURCES (2048 - 16) 46 #else 45 47 #define OPENPIC_MAX_SOURCES 2048 48 #endif 46 49 #define OPENPIC_MAX_PROCESSORS 32 47 50 … … 158 161 OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS]; 159 162 char Pad1[0xee00]; 163 #if defined(mpc8240) || defined(mpc8245) 164 char Pad2[0x0200]; 165 #endif 160 166 } OpenPIC_Global; 161 167 -
c/src/lib/libbsp/powerpc/shared/pci/detect_raven_bridge.c
rae460ec rbd91ff4e 13 13 14 14 #include <rtems/bspIo.h> 15 #include <libcpu/cpuIdent.h> 15 16 16 #define RAVEN_MPIC_IOSPACE_ENABLE 0x117 #define RAVEN_MPIC_MEMSPACE_ENABLE 0x218 #define RAVEN_MASTER_ENABLE 0x419 #define RAVEN_PARITY_CHECK_ENABLE 0x4020 #define RAVEN_SYSTEM_ERROR_ENABLE 0x10021 #define RAVEN_CLEAR_EVENTS_MASK 17 #define RAVEN_MPIC_IOSPACE_ENABLE 0x0001 18 #define RAVEN_MPIC_MEMSPACE_ENABLE 0x0002 19 #define RAVEN_MASTER_ENABLE 0x0004 20 #define RAVEN_PARITY_CHECK_ENABLE 0x0040 21 #define RAVEN_SYSTEM_ERROR_ENABLE 0x0100 22 #define RAVEN_CLEAR_EVENTS_MASK 0xf9000000 22 23 23 #define RAVEN_MPIC_MEREN 24 #define RAVEN_MPIC_MERST 24 #define RAVEN_MPIC_MEREN ((volatile unsigned *)0xfeff0020) 25 #define RAVEN_MPIC_MERST ((volatile unsigned *)0xfeff0024) 25 26 /* enable machine check on all conditions */ 26 #define MEREN_VAL 27 #define MEREN_VAL 0x2f00 27 28 28 29 #define pci BSP_pci_configuration 30 extern unsigned int EUMBBAR; 29 31 30 32 extern const pci_config_access_functions pci_direct_functions; … … 36 38 unsigned merst; 37 39 38 39 40 40 merst = in_be32(RAVEN_MPIC_MERST); 41 /* write back value to clear status */ 42 out_be32(RAVEN_MPIC_MERST, merst); 41 43 42 43 44 45 46 47 48 49 50 51 52 44 if (enableMCP) { 45 if (!quiet) 46 printk("Enabling MCP generation on hostbridge errors\n"); 47 out_be32(RAVEN_MPIC_MEREN, MEREN_VAL); 48 } else { 49 out_be32(RAVEN_MPIC_MEREN, 0); 50 if ( !quiet && enableMCP ) { 51 printk("leaving MCP interrupt disabled\n"); 52 } 53 } 54 return (merst & 0xffff); 53 55 } 54 56 55 57 void detect_host_bridge() 56 58 { 59 #if (defined(mpc8240) || defined(mpc8245)) 60 /* 61 * If the processor is an 8240 or an 8245 then the PIC is built 62 * in instead of being on the PCI bus. The MVME2100 is using Processor 63 * Address Map B (CHRP) although the Programmer's Reference Guide says 64 * it defaults to Map A. 65 */ 66 /* We have an EPIC Interrupt Controller */ 67 OpenPIC = (volatile struct OpenPIC *) (EUMBBAR + BSP_OPEN_PIC_BASE_OFFSET); 68 pci.pci_functions = &pci_indirect_functions; 69 pci.pci_config_addr = (volatile unsigned char *) 0xfec00000; 70 pci.pci_config_data = (volatile unsigned char *) 0xfee00000; 71 #else 72 57 73 PPC_DEVICE *hostbridge; 58 74 unsigned int id0; 59 75 unsigned int tmp; 60 76 61 77 /* 62 78 * This code assumes that the host bridge is located at … … 65 81 * (still used in BSD source code) works. 66 82 */ 67 hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL, 68 BridgeController, 69 PCIBridge, -1, 0); 83 hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL, 84 BridgeController, 85 PCIBridge, -1, 0); 86 70 87 if (hostbridge) { 71 88 if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) { 72 89 pci.pci_functions=&pci_indirect_functions; 73 /* Should be extracted from residual data, 90 /* Should be extracted from residual data, 74 91 * indeed MPC106 in CHRP mode is different, 75 92 * but we should not use residual data in 76 * this case anyway. 93 * this case anyway. 77 94 */ 78 pci.pci_config_addr = ((volatile unsigned char *) 79 95 pci.pci_config_addr = ((volatile unsigned char *) 96 (ptr_mem_map->io_base+0xcf8)); 80 97 pci.pci_config_data = ptr_mem_map->io_base+0xcfc; 81 98 } else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) { … … 88 105 pci.pci_functions = &pci_direct_functions; 89 106 /* On all direct bridges I know the host bridge itself 90 * appears as device 0 function 0. 91 107 * appears as device 0 function 0. 108 */ 92 109 pci_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &id0); 93 110 if (id0==~0U) { 94 111 pci.pci_functions = &pci_indirect_functions; 95 pci.pci_config_addr = ((volatile unsigned char*) 96 (ptr_mem_map->io_base+0xcf8)); 97 pci.pci_config_data = ((volatile unsigned char*)ptr_mem_map->io_base+0xcfc); 112 pci.pci_config_addr = (volatile unsigned char*) 113 (ptr_mem_map->io_base+0xcf8); 114 pci.pci_config_data = (volatile unsigned char*) 115 (ptr_mem_map->io_base+0xcfc); 98 116 } 99 117 /* Here we should check that the host bridge is actually … … 103 121 } 104 122 pci_read_config_dword(0, 0, 0, 0, &id0); 123 105 124 if(id0 == PCI_VENDOR_ID_MOTOROLA + 106 125 (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) { … … 109 128 */ 110 129 pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0); 111 #ifdef SHOW_RAVEN_SETTING 130 #ifdef SHOW_RAVEN_SETTING 112 131 printk("RAVEN PCI command register = %x\n",id0); 113 #endif 132 #endif 114 133 id0 |= RAVEN_CLEAR_EVENTS_MASK; 115 134 pci_write_config_dword(0, 0, 0, PCI_COMMAND, id0); 116 135 pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0); 117 #ifdef SHOW_RAVEN_SETTING 136 #ifdef SHOW_RAVEN_SETTING 118 137 printk("After error clearing RAVEN PCI command register = %x\n",id0); 119 #endif 120 138 #endif 139 121 140 if (id0 & RAVEN_MPIC_IOSPACE_ENABLE) { 122 141 pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_0, &tmp); 123 #ifdef SHOW_RAVEN_SETTING 124 printk("Raven MPIC is accessed via IO Space Access at address : %x\n",(tmp & ~0x1)); 125 #endif 142 #ifdef SHOW_RAVEN_SETTING 143 printk("Raven MPIC is accessed via IO Space Access at address : %x\n", 144 (tmp & ~0x1)); 145 #endif 126 146 } 127 147 if (id0 & RAVEN_MPIC_MEMSPACE_ENABLE) { 128 148 pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_1, &tmp); 129 #ifdef SHOW_RAVEN_SETTING 130 printk("Raven MPIC is accessed via memory Space Access at address : %x\n", tmp); 131 #endif 149 #ifdef SHOW_RAVEN_SETTING 150 printk("Raven MPIC is accessed via memory Space Access" 151 "at address : %x\n", tmp) 152 #endif 132 153 OpenPIC=(volatile struct OpenPIC *) (tmp + PREP_ISA_MEM_BASE); 133 printk("OpenPIC found at %x.\n", 134 OpenPIC); 154 printk("OpenPIC found at %x.\n", OpenPIC); 135 155 } 136 156 } 157 #endif 137 158 if (OpenPIC == (volatile struct OpenPIC *)0) { 138 159 BSP_panic("OpenPic Not found\n"); 139 160 } 140 141 161 } -
c/src/lib/libbsp/powerpc/shared/pci/pci.c
rae460ec rbd91ff4e 2 2 * pci.c : this file contains basic PCI Io functions. 3 3 * 4 * Copy Right (C) 1999 valette@crf.canon.fr4 * Copyright (C) 1999 valette@crf.canon.fr 5 5 * 6 * This code is heavil ly inspired by the public specification of STREAM V26 * This code is heavily inspired by the public specification of STREAM V2 7 7 * that can be found at : 8 8 * … … 218 218 219 219 220 221 222 223 224 225 226 227 228 229 230 231 220 #define PRINT_MSG() \ 232 221 printk("pci : Device %d:%02x routed to interrupt_line %d\n", pbus, pslot, int_name ) … … 237 226 ** the names defined in the routing record. 238 227 */ 239 static int test_intname( struct _int_map *row, int pbus, int pslot, int int_pin, int int_name ) 228 static int test_intname( 229 const struct _int_map *row, 230 int pbus, 231 int pslot, 232 int int_pin, 233 int int_name 234 ) 240 235 { 241 int j, k;236 int j, k; 242 237 int _nopin= -1, _noname= -1; 243 238 … … 334 329 335 330 336 void FixupPCI( struct _int_map *bspmap, int (*swizzler)(int,int) )331 void FixupPCI( const struct _int_map *bspmap, int (*swizzler)(int,int) ) 337 332 { 338 333 unsigned char cvalue; -
c/src/lib/libbsp/powerpc/shared/pci/pci.h
rae460ec rbd91ff4e 1165 1165 }; 1166 1166 1167 void FixupPCI( struct _int_map *, int (*swizzler)(int,int) );1167 void FixupPCI( const struct _int_map *, int (*swizzler)(int,int) ); 1168 1168 1169 1169 -
c/src/lib/libbsp/powerpc/shared/start/start.S
rae460ec rbd91ff4e 15 15 #include <rtems/score/cpu.h> 16 16 #include <libcpu/io.h> 17 #include <bspopts.h> 17 18 18 19 #define SYNC \ … … 29 30 sc 30 31 31 32 32 .text 33 33 .globl __rtems_entry_point … … 68 68 */ 69 69 lis r11,KERNELBASE@h 70 ori r11,r11,0x1ffe /* set up BAT registers for 604 */ 70 /* set up BAT registers for 604 */ 71 ori r11,r11,0x1ffe 71 72 li r8,2 /* R/W access */ 72 73 isync 74 #if defined(mvme2100) 75 /* BSP_vme_config() wants to use BAT0, this board will use the 76 * available BAT1 to map RAM. 77 */ 78 mtspr DBAT1L,r8 /* N.B. 6xx (not 601) have valid */ 79 mtspr DBAT1U,r11 /* bit in upper BAT register */ 80 mtspr IBAT1L,r8 81 mtspr IBAT1U,r11 82 #else 73 83 mtspr DBAT0L,r8 /* N.B. 6xx (not 601) have valid */ 74 84 mtspr DBAT0U,r11 /* bit in upper BAT register */ 75 85 mtspr IBAT0L,r8 76 86 mtspr IBAT0U,r11 87 #endif 77 88 isync 78 89 … … 88 99 enter_C_code: 89 100 bl MMUon 90 bl __eabi /* setup EABI and SYSV environment */101 bl __eabi /* setup EABI and SYSV environment */ 91 102 bl zero_bss 92 103 /* … … 106 117 mr r1, r9 107 118 /* 108 * We are know in a environment that is totally independent from bootloader setup. 119 * We are now in a environment that is totally independent from 120 * bootloader setup. 109 121 */ 110 122 lis r5,environ@ha … … 114 126 bl boot_card 115 127 bl _return_to_ppcbug 116 128 117 129 .globl MMUon 118 130 .type MMUon,@function 119 MMUon: 131 MMUon: 120 132 mfmsr r0 133 ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP 134 #if defined(mvme2100) 135 /* Data addr translation is broken for the mvme2100, disable it here */ 136 xori r0,r0, MSR_DR 137 #endif 121 138 #if (PPC_HAS_FPU == 0) 122 ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP123 139 xori r0, r0, MSR_EE | MSR_IP | MSR_FP 124 140 #else 125 ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP126 141 xori r0, r0, MSR_EE | MSR_IP | MSR_FE0 | MSR_FE1 127 142 #endif … … 131 146 SYNC 132 147 rfi 133 148 134 149 .globl MMUoff 135 150 .type MMUoff,@function 136 MMUoff: 151 MMUoff: 137 152 mfmsr r0 138 153 ori r0,r0,MSR_IR| MSR_DR | MSR_IP -
c/src/lib/libbsp/powerpc/shared/startup/bspstart.c
rae460ec rbd91ff4e 20 20 #include <string.h> 21 21 22 #include <bsp.h> 22 23 #include <rtems/libio.h> 23 24 #include <rtems/libcsupport.h> … … 29 30 #include <bsp/irq.h> 30 31 #include <bsp/VME.h> 31 #include <bsp.h>32 32 #include <libcpu/bat.h> 33 33 #include <libcpu/pte121.h> … … 49 49 SPR_RW(SPRG1) 50 50 51 #if defined(DEBUG_BATS) 52 void printBAT( int bat, unsigned32 upper, unsigned32 lower ) 53 { 54 unsigned32 lowest_addr; 55 unsigned32 size; 56 57 printk("BAT%d raw(upper=0x%08x, lower=0x%08x) ", bat, upper, lower ); 58 59 lowest_addr = (upper & 0xFFFE0000); 60 size = (((upper & 0x00001FFC) >> 2) + 1) * (128 * 1024); 61 printk(" range(0x%08x, 0x%08x) %s%s %s%s%s%s %s\n", 62 lowest_addr, 63 lowest_addr + (size - 1), 64 (upper & 0x01) ? "P" : "p", 65 (upper & 0x02) ? "S" : "s", 66 (lower & 0x08) ? "G" : "g", 67 (lower & 0x10) ? "M" : "m", 68 (lower & 0x20) ? "I" : "i", 69 (lower & 0x40) ? "W" : "w", 70 (lower & 0x01) ? "Read Only" : 71 ((lower & 0x02) ? "Read/Write" : "No Access") 72 ); 73 } 74 75 void ShowBATS(){ 76 unsigned32 lower; 77 unsigned32 upper; 78 79 __MFSPR(536, upper); __MFSPR(537, lower); printBAT( 0, upper, lower ); 80 __MFSPR(538, upper); __MFSPR(539, lower); printBAT( 1, upper, lower ); 81 __MFSPR(540, upper); __MFSPR(541, lower); printBAT( 2, upper, lower ); 82 __MFSPR(542, upper); __MFSPR(543, lower); printBAT( 3, upper, lower ); 83 } 84 #endif 85 51 86 /* 52 87 * Copy of residuals passed by firmware … … 131 166 void bsp_pretasking_hook(void) 132 167 { 133 134 135 136 137 138 heap_start = ((rtems_unsigned32) __rtems_end) +INIT_STACK_SIZE + INTR_STACK_SIZE;139 if (heap_start & (CPU_ALIGNMENT-1))140 heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);141 142 heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size; 143 144 168 rtems_unsigned32 heap_start; 169 rtems_unsigned32 heap_size; 170 rtems_unsigned32 heap_sbrk_spared; 171 extern rtems_unsigned32 _bsp_sbrk_init(rtems_unsigned32, rtems_unsigned32*); 172 173 heap_start = ((rtems_unsigned32) __rtems_end) + 174 INIT_STACK_SIZE + INTR_STACK_SIZE; 175 if (heap_start & (CPU_ALIGNMENT-1)) 176 heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); 177 178 heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size; 179 heap_sbrk_spared=_bsp_sbrk_init(heap_start, &heap_size); 145 180 146 181 #ifdef SHOW_MORE_INIT_SETTINGS 147 printk(" HEAP start %x size %x (%x bytes spared for sbrk)\n", heap_start, heap_size, heap_sbrk_spared); 182 printk( "HEAP start %x size %x (%x bytes spared for sbrk)\n", 183 heap_start, heap_size, heap_sbrk_spared); 148 184 #endif 149 185 150 bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared); 151 186 bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared); 152 187 153 188 #ifdef RTEMS_DEBUG 154 189 rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); 155 190 #endif 156 191 } … … 174 209 } 175 210 211 #if defined(mpc8240) || defined(mpc8245) 212 unsigned int EUMBBAR; 213 214 /* 215 * Return the current value of the Embedded Utilities Memory Block Base Address 216 * Register (EUMBBAR) as read from the processor configuration register using 217 * Processor Address Map B (CHRP). 218 */ 219 unsigned int get_eumbbar() { 220 register int a, e; 221 222 asm volatile( "lis %0,0xfec0; ori %0,%0,0x0000": "=r" (a) ); 223 asm volatile("sync"); 224 225 asm volatile("lis %0,0x8000; ori %0,%0,0x0078": "=r"(e) ); 226 asm volatile("stwbrx %0,0x0,%1": "=r"(e): "r"(a)); 227 asm volatile("sync"); 228 229 asm volatile("lis %0,0xfee0; ori %0,%0,0x0000": "=r" (a) ); 230 asm volatile("sync"); 231 232 asm volatile("lwbrx %0,0x0,%1": "=r" (e): "r" (a)); 233 asm volatile("isync"); 234 return e; 235 } 236 #endif 237 176 238 /* 177 239 * bsp_start … … 182 244 void bsp_start( void ) 183 245 { 184 int err;185 246 unsigned char *stack; 247 #if !defined(mpc8240) && !defined(mpc8245) 186 248 unsigned l2cr; 249 #endif 187 250 register unsigned char* intrStack; 188 251 unsigned char *work_space_start; … … 192 255 motorolaBoard myBoard; 193 256 Triv121PgTbl pt=0; 194 /* 195 * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function 196 * store the result in global variables so that it can be used latter... 257 258 select_console(CONSOLE_SERIAL); 259 /* 260 * Get CPU identification dynamically. Note that the get_ppc_cpu_type() 261 * function store the result in global variables so that it can be used 262 * later... 197 263 */ 198 264 myCpu = get_ppc_cpu_type(); 199 265 myCpuRevision = get_ppc_cpu_revision(); 266 267 #if defined(mvme2100) 268 EUMBBAR = get_eumbbar(); 269 270 Cpu_table.exceptions_in_RAM = TRUE; 271 { unsigned v = 0x3000 ; _CPU_MSR_SET(v); } 272 #endif 273 274 #if !defined(mpc8240) && !defined(mpc8245) 200 275 /* 201 276 * enables L1 Cache. Note that the L1_caches_enables() codes checks for … … 203 278 */ 204 279 L1_caches_enables(); 280 205 281 /* 206 282 * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for … … 213 289 if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1)) 214 290 set_L2CR(0xb9A14000); 215 /* 216 * the initial stack has aready been set to this value in start.S 291 #endif 292 293 /* 294 * the initial stack has already been set to this value in start.S 217 295 * so there is no need to set it in r1 again... It is just for info 218 296 * so that It can be printed without accessing R1. 219 297 */ 220 stack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE; 221 222 /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */ 298 stack = ((unsigned char*) __rtems_end) + 299 INIT_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE; 300 301 /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */ 223 302 *((unsigned32 *)stack) = 0; 224 303 … … 227 306 * SPRG1 = software managed IRQ stack 228 307 * 229 * This could be done lat ter (e.g in IRQ_INIT) but it helps to understand308 * This could be done later (e.g in IRQ_INIT) but it helps to understand 230 309 * some settings below... 231 310 */ 232 intrStack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE; 311 intrStack = ((unsigned char*) __rtems_end) + 312 INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE; 233 313 234 314 /* make sure it's properly aligned */ … … 244 324 245 325 /* 246 * Initialize default raw exception han lders. See vectors/vectors_init.c326 * Initialize default raw exception handlers. See vectors/vectors_init.c 247 327 */ 248 328 initialize_exceptions(); 249 /* 250 * Init MMU block address translation to enable hardware 251 * access 252 */ 253 /* 254 * PC legacy IO space used for inb/outb and all PC 255 * compatible hardware 256 */ 257 setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE); 258 /* 259 * PCI devices memory area. Needed to access OPENPIC features 260 * provided by the RAVEN 261 */ 262 /* T. Straumann: give more PCI address space */ 263 setdbat(2, PCI_MEM_BASE, PCI_MEM_BASE, 0x10000000, IO_PAGE); 264 /* 265 * Must have acces to open pic PCI ACK registers 266 * provided by the RAVEN 267 * 329 330 /* 331 * Init MMU block address translation to enable hardware access 332 */ 333 #if !defined(mvme2100) 334 /* 335 * PC legacy IO space used for inb/outb and all PC compatible hardware 336 */ 337 setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE); 338 #endif 339 340 /* 341 * PCI devices memory area. Needed to access OpenPIC features 342 * provided by the Raven 343 * 344 * T. Straumann: give more PCI address space 345 */ 346 setdbat(2, PCI_MEM_BASE, PCI_MEM_BASE, 0x10000000, IO_PAGE); 347 348 /* 349 * Must have access to OpenPIC PCI ACK registers provided by the Raven 268 350 */ 269 351 setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE); … … 271 353 select_console(CONSOLE_LOG); 272 354 273 /* We check that the keyboard is present and immediately 355 /* 356 * We check that the keyboard is present and immediately 274 357 * select the serial console if not. 275 358 */ 276 err = kbdreset(); 277 if (err) select_console(CONSOLE_SERIAL); 359 #if defined(BSP_KBD_IOBASE) 360 { int err; 361 err = kbdreset(); 362 if (err) select_console(CONSOLE_SERIAL); 363 } 364 #else 365 select_console(CONSOLE_SERIAL); 366 #endif 278 367 279 368 boardManufacturer = checkPrepBoardType(&residualCopy); … … 285 374 286 375 printk("-----------------------------------------\n"); 287 printk("Welcome to %s on %s\n", _RTEMS_version, motorolaBoardToString(myBoard)); 376 printk("Welcome to %s on %s\n", _RTEMS_version, 377 motorolaBoardToString(myBoard)); 288 378 printk("-----------------------------------------\n"); 289 379 #ifdef SHOW_MORE_INIT_SETTINGS … … 309 399 InitializePCI(); 310 400 311 {312 struct _int_map *bspmap= motorolaIntMap(currentBoard);313 if( bspmap ) 314 {315 printk("pci : Configuring interrupt routing for '%s'\n",motorolaBoardToString(currentBoard));401 { 402 const struct _int_map *bspmap = motorolaIntMap(currentBoard); 403 if( bspmap ) { 404 printk("pci : Configuring interrupt routing for '%s'\n", 405 motorolaBoardToString(currentBoard)); 316 406 FixupPCI(bspmap, motorolaIntSwizzle(currentBoard) ); 317 407 } … … 320 410 } 321 411 322 323 412 #ifdef SHOW_MORE_INIT_SETTINGS 324 413 printk("Number of PCI buses found is : %d\n", BusCountPCI()); … … 331 420 __asm__ __volatile ("sc"); 332 421 /* 333 * Check we can still catch exceptions and return ed coorectly.422 * Check we can still catch exceptions and return correctly. 334 423 */ 335 424 printk("Testing exception handling Part 2\n"); 336 425 __asm__ __volatile ("sc"); 426 427 /* 428 * Somehow doing the above seems to clobber SPRG0 on the mvme2100. It 429 * is probably a not so subtle hint that you do not want to use PPCBug 430 * once RTEMS is up and running. Anyway, we still needs to indicate 431 * that we have fixed PR288. Eventually, this should go away. 432 */ 433 _write_SPRG0(PPC_BSP_HAS_FIXED_PR288); 337 434 #endif 338 435 339 340 BSP_mem_size = residualCopy.TotalMemory; 341 BSP_bus_frequency = residualCopy.VitalProductData.ProcessorBusHz; 342 BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz; 343 BSP_time_base_divisor = (residualCopy.VitalProductData.TimeBaseDivisor? 344 residualCopy.VitalProductData.TimeBaseDivisor : 4000); 436 BSP_mem_size = residualCopy.TotalMemory; 437 BSP_bus_frequency = residualCopy.VitalProductData.ProcessorBusHz; 438 BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz; 439 BSP_time_base_divisor = (residualCopy.VitalProductData.TimeBaseDivisor? 440 residualCopy.VitalProductData.TimeBaseDivisor : 4000); 345 441 346 442 /* clear hostbridge errors but leave MCP disabled - … … 348 444 */ 349 445 _BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/); 350 351 446 352 447 /* Allocate and set up the page table mappings … … 359 454 pt = BSP_pgtbl_setup(&BSP_mem_size); 360 455 361 if (!pt || 362 TRIV121_MAP_SUCCESS != triv121PgTblMap( 363 pt, 364 TRIV121_121_VSID, 365 0xfeff0000, 366 1, 367 TRIV121_ATTR_IO_PAGE, 368 TRIV121_PP_RW_PAGE 369 )) { 370 printk("WARNING: unable to setup page tables VME bridge must share PCI space\n"); 456 if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap( 457 pt, TRIV121_121_VSID, 0xfeff0000, 1, 458 TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) { 459 printk("WARNING: unable to setup page tables VME " 460 "bridge must share PCI space\n"); 371 461 } 372 462 373 463 /* 374 464 * Set up our hooks … … 385 475 386 476 #ifdef SHOW_MORE_INIT_SETTINGS 387 printk("BSP_Configuration.work_space_size = %x\n", BSP_Configuration.work_space_size); 477 printk("BSP_Configuration.work_space_size = %x\n", 478 BSP_Configuration.work_space_size); 388 479 #endif 389 480 work_space_start = 390 481 (unsigned char *)BSP_mem_size - BSP_Configuration.work_space_size; 391 482 392 if ( work_space_start <= ((unsigned char *)__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE) { 483 if ( work_space_start <= 484 ((unsigned char *)__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE) { 393 485 printk( "bspstart: Not enough RAM!!!\n" ); 394 486 bsp_cleanup(); … … 402 494 BSP_rtems_irq_mng_init(0); 403 495 404 405 496 /* Activate the page table mappings only after 406 497 * initializing interrupts because the irq_mng_init() … … 412 503 #endif 413 504 BSP_pgtbl_activate(pt); 414 415 505 /* finally, switch off DBAT3 */ 506 setdbat(3, 0, 0, 0, 0); 416 507 } 417 508 418 509 /* 419 * Initialize VME bridge - needs working PCI 420 * and IRQ subsystems... 510 * Initialize VME bridge - needs working PCI and IRQ subsystems... 421 511 */ 422 512 #ifdef SHOW_MORE_INIT_SETTINGS 423 513 printk("Going to initialize VME bridge\n"); 424 514 #endif 425 /* VME initialization is in a separate file so apps which don't use426 * VME or want a different configuration may link against a customized427 * routine.515 /* 516 * VME initialization is in a separate file so apps which don't use VME or 517 * want a different configuration may link against a customized routine. 428 518 */ 429 519 BSP_vme_config(); 520 521 522 #if defined(DEBUG_BATS) 523 ShowBATS(); 524 #endif 430 525 431 526 #ifdef SHOW_MORE_INIT_SETTINGS -
c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c
rae460ec rbd91ff4e 176 176 BSP_panic("Exception handling initialization failed\n"); 177 177 } 178 #ifdef RTEMS_DEBUG 178 179 else { 179 180 printk("Exception handling initialization done\n"); 180 181 } 182 #endif 181 183 } -
c/src/lib/libbsp/powerpc/shared/vme/vmeconfig.c
rae460ec rbd91ff4e 35 35 } dbat0u; 36 36 37 if (currentBoard < MVME_2300 || currentBoard >= MVME_1600) {38 printk("VME bridge for this board is unknown - if it's a Tundra Universe, add the board to 'shared/vme/vmeconfig.c'\n");39 printk("Skipping VME initialization...\n");40 return;41 }42 43 37 vmeUniverseInit(); 44 38 vmeUniverseReset(); 45 46 39 /* setup a PCI area to map the VME bus */ 47 40 … … 50 43 /* if we have page tables, BAT0 is available */ 51 44 if (dbat0u.bat.vs || dbat0u.bat.vp) { 52 printk("WARNING: BAT0 is taken (no pagetables?); VME bridge must share PCI range for VME access\n"); 53 printk("Skipping VME initialization...\n"); 45 printk("WARNING: BAT0 is taken (no pagetables?); " 46 "VME bridge must share PCI range for VME access\n" 47 "Skipping VME initialization...\n"); 54 48 return; 55 49 }
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