Changeset bd918ff7 in rtems


Ignore:
Timestamp:
Feb 11, 2011, 12:19:29 PM (9 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.11, master
Children:
7922b39c
Parents:
bd6cbca3
Message:

2011-02-11 Ralf Corsépius <ralf.corsepius@…>

  • shared/console/polled_io.c, shared/flash/spansionFlash.c, shared/startup/bspidle.c, shared/startup/probeMemEnd.c: Use "asm" instead of "asm" for improved c99-compliance.
Location:
c/src/lib/libbsp/powerpc
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/ChangeLog

    rbd6cbca3 rbd918ff7  
     12011-02-11      Ralf Corsépius <ralf.corsepius@rtems.org>
     2
     3        * shared/console/polled_io.c, shared/flash/spansionFlash.c,
     4        shared/startup/bspidle.c, shared/startup/probeMemEnd.c:
     5        Use "__asm__" instead of "asm" for improved c99-compliance.
     6
    172011-02-02      Ralf Corsépius <ralf.corsepius@rtems.org>
    28
  • c/src/lib/libbsp/powerpc/shared/console/polled_io.c

    rbd6cbca3 rbd918ff7  
    910910#define div10(num, rmd)                                                  \
    911911do {    uint32_t t1, t2, t3;                                                     \
    912         asm("lis %4,0xcccd; "                                            \
     912        __asm__ ("lis %4,0xcccd; "                                               \
    913913            "addi %4,%4,0xffffcccd; "   /* Build 0xcccccccd */           \
    914914            "mulhwu %3,%0+1,%4; "       /* (num.l*cst.l).h  */           \
  • c/src/lib/libbsp/powerpc/shared/flash/spansionFlash.c

    rbd6cbca3 rbd918ff7  
    7878
    7979#ifdef __PPC__
    80 #define IOSYNC(mem)     do { asm volatile("eieio"); } while (0)
     80#define IOSYNC(mem)     do { __asm__ volatile("eieio"); } while (0)
    8181#else
    8282#define IOSYNC(mem)     do { } while (0)
  • c/src/lib/libbsp/powerpc/shared/startup/bspidle.c

    rbd6cbca3 rbd918ff7  
    2828{
    2929  for( ; ; ) {
    30     asm volatile(
     30    __asm__ volatile(
    3131      "mfmsr 3; oris 3,3,4; sync; mtmsr 3; isync; ori 3,3,0; ori 3,3,0"
    3232    );
  • c/src/lib/libbsp/powerpc/shared/startup/probeMemEnd.c

    rbd6cbca3 rbd918ff7  
    124124        if ( _read_MSR() & MSR_VE ) {
    125125#define DSSALL  0x7e00066c  /* dssall opcode */
    126         asm volatile("  .long %0"::"i"(DSSALL));
     126        __asm__ volatile("  .long %0"::"i"(DSSALL));
    127127#undef  DSSALL
    128128        }
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