Changeset bd750c9e in rtems


Ignore:
Timestamp:
May 27, 2020, 7:24:54 AM (7 weeks ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
e845873
Parents:
934cbe7
git-author:
Sebastian Huber <sebastian.huber@…> (05/27/20 07:24:54)
git-committer:
Sebastian Huber <sebastian.huber@…> (05/27/20 08:25:12)
Message:

arm: Fix ARMv7-M exception handler

Store the stack pointer of the exception context to the exception frame.

Close #3987.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/arm/armv7m-exception-default.c

    r934cbe7 rbd750c9e  
    4141    "tst lr, #4\n"          /* Check if bit 2 of LR is zero. If so, PSR.Z = 1 */
    4242    "itte eq\n"             /* IF bit 2 of LR is zero... (PSR.Z == 1) */
    43     "mrseq r0, msp\n"       /* THEN we were using MSP. */
    44     "addeq r0, %[cpufsz]\n" /* THEN, set r0 = old MSP value. */
    45     "mrsne r0, psp\n"       /* ELSE it's not zero; we were using PSP. */
    46     "add r2, r0, %[v7mlroff]\n"
    47     "add r1, sp, %[cpulroff]\n"
    48     "ldm r2, {r3-r5}\n"     /* Grab LR, PC and PSR from the stack.. */
    49     "stm r1, {r3-r5}\n"     /* ..and store them in our CPU_Exception_frame. */
     43    "mrseq r3, msp\n"       /* THEN we were using MSP */
     44    "addeq r3, %[cpufsz]\n" /* THEN, set r3 = old MSP value */
     45    "mrsne r3, psp\n"       /* ELSE it is not zero; we were using PSP */
     46    "add r2, r3, %[v7mlroff]\n"
     47    "add r1, sp, %[cpuspoff]\n"
     48    "ldm r2, {r4-r6}\n"     /* Grab LR, PC and xPSR from the stack */
     49    "tst lr, #16\n"         /* Check if we have an FP state on the frame */
     50    "ite eq\n"
     51    "addeq r3, #104\n"      /* Back to previous SP with FP state */
     52    "addne r3, #32\n"       /* Back to previous SP without FP state */
     53    "tst r6, #512\n"        /* Check xPSR if the SP was aligned */
     54    "it ne\n"
     55    "addne r3, #4\n"        /* Undo alignment */
     56    "stm r1, {r3-r6}\n"     /* Store to CPU_Exception_frame */
    5057    "mrs r1, ipsr\n"
    5158    "str r1, [sp, %[cpuvecoff]]\n"
     
    8693    :
    8794    : [cpufsz] "i" (sizeof(CPU_Exception_frame)),
    88       [cpulroff] "i" (offsetof(CPU_Exception_frame, register_lr)),
     95      [cpuspoff] "i" (offsetof(CPU_Exception_frame, register_sp)),
    8996      [v7mlroff] "i" (offsetof(ARMV7M_Exception_frame, register_lr)),
    9097      [cpuvecoff] "J" (offsetof(CPU_Exception_frame, vector)),
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