Ignore:
Timestamp:
Mar 1, 2002, 4:21:12 PM (18 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
0ea3293
Parents:
f9d1afc
Message:

2002-02-27 Greg Menke <gregory.menke@…>

  • cpu_asm.S: Fixed exception return address, modified FP context switch so FPU is properly enabled and also doesn't screw up the exception FP handling.
  • idtcpu.h: Added C0_TAR, the MIPS target address register used for returning from exceptions.
  • iregdef.h: Added R_TAR to the stack frame so the target address can be saved on a per-exception basis. The new entry is past the end of the frame gdb cares about, so doesn't affect gdb or cpu.h stuff.
  • rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it to obtain FPU defines without systax errors generated by the C defintions.
  • cpu.c: Improved interrupt level saves & restores.
File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/mips/rtems/mips/idtcpu.h

    rf9d1afc rbd1ecb0  
    363363 */
    364364#define CAUSE_BD        0x80000000      /* Branch delay slot */
     365#define CAUSE_BT        0x40000000      /* Branch Taken */
    365366#define CAUSE_CEMASK    0x30000000      /* coprocessor error */
    366367#define CAUSE_CESHIFT   28
     
    392393#define C0_PAGEMASK     $5              /* tlb page mask */
    393394#define C0_WIRED        $6              /* number of wired tlb entries */
     395#endif
     396
     397#if  __mips == 1
     398#define C0_TAR          $6
    394399#endif
    395400
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