Changeset bca36d9 in rtems


Ignore:
Timestamp:
Jul 6, 2018, 9:07:20 AM (10 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
31f90a2
Parents:
dd32e2b2
git-author:
Sebastian Huber <sebastian.huber@…> (07/06/18 09:07:20)
git-committer:
Sebastian Huber <sebastian.huber@…> (07/06/18 11:46:46)
Message:

riscv: Add LADDR assembler define

An address must be loaded to a register according to the code model.
Add LADDR define for use in assembler code.

Update #3433.

Files:
3 edited

Legend:

Unmodified
Added
Removed
  • bsps/riscv/riscv/start/start.S

    rdd32e2b2 rbca36d9  
    5151        .option push
    5252        .option norelax
    53         la      gp, __global_pointer$
     53        LADDR   gp, __global_pointer$
    5454        .option pop
    5555
    5656#ifdef RTEMS_SMP
    5757        csrr    s0, mhartid
    58         la      t0, _Per_CPU_Information
     58        LADDR   t0, _Per_CPU_Information
    5959        slli    t1, s0, PER_CPU_CONTROL_SIZE_LOG2
    6060        add     t0, t0, t1
     
    6464
    6565        /* load stack and frame pointers */
    66         la      sp, _Configuration_Interrupt_stack_area_end
     66        LADDR   sp, _Configuration_Interrupt_stack_area_end
    6767
    6868#ifdef BSP_START_COPY_FDT_FROM_U_BOOT
     
    7171#endif
    7272
    73         la      t0, ISR_Handler
     73        LADDR   t0, ISR_Handler
    7474        csrw    mtvec, t0
    7575
    7676        /* Clear .bss */
    77         la      a0, bsp_section_bss_begin
     77        LADDR   a0, bsp_section_bss_begin
    7878        li      a1, 0
    79         la      a2, bsp_section_bss_size
     79        LADDR   a2, bsp_section_bss_size
    8080        call    memset
    8181
    8282#ifdef RTEMS_SMP
    8383        /* Give go to secondary processors */
    84         la      t0, .Lsecondary_processor_go
     84        LADDR   t0, .Lsecondary_processor_go
    8585        fence   iorw,ow
    8686        amoswap.w       zero, zero, 0(t0)
     
    9696        /* Wait for go issued by the boot processor (mhartid == 0) */
    9797.Lwait_for_go:
    98         la      t0, .Lsecondary_processor_go
     98        LADDR   t0, .Lsecondary_processor_go
    9999.Lwait_for_go_again:
    100100        lw      t1, 0(t0)
  • cpukit/score/cpu/riscv/include/rtems/asm.h

    rdd32e2b2 rbca36d9  
    132132#endif /* __riscv_xlen */
    133133
     134#ifdef __riscv_cmodel_medany
     135
     136#define LADDR lla
     137
     138#else /* !__riscv_cmodel_medany */
     139
     140#define LADDR la
     141
     142#endif /* __riscv_cmodel_medany */
     143
    134144#if __riscv_flen == 32
    135145
     
    168178        csrr    \REG, mscratch
    169179#else
    170         la      \REG, _Per_CPU_Information
     180        LADDR   \REG, _Per_CPU_Information
    171181#endif
    172182.endm
  • cpukit/score/cpu/riscv/riscv-exception-handler.S

    rdd32e2b2 rbca36d9  
    129129
    130130        /* calculate the offset */
    131         la      t5, bsp_start_vector_table_begin
     131        LADDR   t5, bsp_start_vector_table_begin
    132132#if     __riscv_xlen == 32
    133133        slli    t6, a0, 2
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