Changeset bca36d9 in rtems

Timestamp:

07/06/18 09:07:20 (5 years ago)

Author:

Sebastian Huber <sebastian.huber@…>

Branches:

5, master

Children:

31f90a2

Parents:

dd32e2b2

git-author:

Sebastian Huber <sebastian.huber@…> (07/06/18 09:07:20)

git-committer:

Sebastian Huber <sebastian.huber@…> (07/06/18 11:46:46)

Message:

riscv: Add LADDR assembler define

An address must be loaded to a register according to the code model.
Add LADDR define for use in assembler code.

Update #3433.

Files:

• bsps/riscv/riscv/start/start.S (modified) (4 diffs)
• cpukit/score/cpu/riscv/include/rtems/asm.h (modified) (2 diffs)
• cpukit/score/cpu/riscv/riscv-exception-handler.S (modified) (1 diff)

bsps/riscv/riscv/start/start.S

@@ -51 +51 @@
         .option push
         .option norelax
-        la      gp, __global_pointer$
+        LADDR   gp, __global_pointer$
         .option pop
 
 #ifdef RTEMS_SMP
         csrr    s0, mhartid
-        la      t0, _Per_CPU_Information
+        LADDR   t0, _Per_CPU_Information
         slli    t1, s0, PER_CPU_CONTROL_SIZE_LOG2
         add     t0, t0, t1
@@ -64 +64 @@
 
         /* load stack and frame pointers */
-        la      sp, _Configuration_Interrupt_stack_area_end
+        LADDR   sp, _Configuration_Interrupt_stack_area_end
 
 #ifdef BSP_START_COPY_FDT_FROM_U_BOOT
@@ -71 +71 @@
 #endif
 
-        la      t0, ISR_Handler
+        LADDR   t0, ISR_Handler
         csrw    mtvec, t0
 
         /* Clear .bss */
-        la      a0, bsp_section_bss_begin
+        LADDR   a0, bsp_section_bss_begin
         li      a1, 0
-        la      a2, bsp_section_bss_size
+        LADDR   a2, bsp_section_bss_size
         call    memset
 
 #ifdef RTEMS_SMP
         /* Give go to secondary processors */
-        la      t0, .Lsecondary_processor_go
+        LADDR   t0, .Lsecondary_processor_go
         fence   iorw,ow
         amoswap.w       zero, zero, 0(t0)
@@ -96 +96 @@
         /* Wait for go issued by the boot processor (mhartid == 0) */
 .Lwait_for_go:
-        la      t0, .Lsecondary_processor_go
+        LADDR   t0, .Lsecondary_processor_go
 .Lwait_for_go_again:
         lw      t1, 0(t0)

cpukit/score/cpu/riscv/include/rtems/asm.h

@@ -132 +132 @@
 #endif /* __riscv_xlen */
 
+#ifdef __riscv_cmodel_medany
+
+#define LADDR lla
+
+#else /* !__riscv_cmodel_medany */
+
+#define LADDR la
+
+#endif /* __riscv_cmodel_medany */
+
 #if __riscv_flen == 32
 
@@ -168 +178 @@
         csrr    \REG, mscratch
 #else
-        la      \REG, _Per_CPU_Information
+        LADDR   \REG, _Per_CPU_Information
 #endif
 .endm

cpukit/score/cpu/riscv/riscv-exception-handler.S

@@ -129 +129 @@
 
         /* calculate the offset */
-        la      t5, bsp_start_vector_table_begin
+        LADDR   t5, bsp_start_vector_table_begin
 #if     __riscv_xlen == 32
         slli    t6, a0, 2