Changeset bc85fd5a in rtems for c/src/lib/libcpu/i960


Ignore:
Timestamp:
Jul 11, 2000, 7:31:04 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
073e2411
Parents:
9e52b29
Message:

Reworked score/cpu/i960 so it can be safely compiled multilib. All
routines and structures that require CPU model specific information
are now in libcpu. This required significant rework of the
score/cpu header files and the creation of multiple header files
and subdirectories in libcpu/i960.

Location:
c/src/lib/libcpu/i960
Files:
17 added
1 moved

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/i960/include/i960RP.h

    r9e52b29 rbc85fd5a  
    1111#define __I960RP_h
    1212
    13 /*----------------------------------------------------------*/
    14 /*  Example 6. Include File (evrp.h)                        */
    15 /*----------------------------------------------------------*/
    16 /* Define JX Core memory mapped register addresses */
    17 /* Common to Jx and RP: */
    18 #define    DLMCON_ADDR    0xff008100
    19 #define    LMAR0_ADDR     0xff008108
    20 #define    LMMR0_ADDR     0xff00810c
    21 #define    LMAR1_ADDR     0xff008110
    22 #define    LMMR1_ADDR     0xff008114
    23 #define    IPB0_ADDR      0xff008400
    24 #define    IPB1_ADDR      0xff008404
    25 #define    DAB0_ADDR      0xff008420
    26 #define    DAB1_ADDR      0xff008424
    27 #define    BPCON_ADDR     0xff008440
    28 #define    IPND_ADDR      0xff008500
    29 #define    IMSK_ADDR      0xff008504
    30 #define    ICON_ADDR      0xff008510
    31 #define    IMAP0_ADDR     0xff008520
    32 #define    IMAP1_ADDR     0xff008524
    33 #define    IMAP2_ADDR     0xff008528
    34 #define    PMCON0_ADDR    0xff008600
    35 #define    PMCON2_ADDR    0xff008608
    36 #define    PMCON4_ADDR    0xff008610
    37 #define    PMCON6_ADDR    0xff008618
    38 #define    PMCON8_ADDR    0xff008620
    39 #define    PMCON10_ADDR   0xff008628
    40 #define    PMCON12_ADDR   0xff008630
    41 #define    PMCON14_ADDR   0xff008638
    42 #define    BCON_ADDR      0xff0086fc
    43 #define    PRCB_ADDR      0xff008700
    44 #define    ISP_ADDR       0xff008704
    45 #define    SSP_ADDR       0xff008708
    46 #define    DEVID_ADDR     0xff008710
    47 #define    TRR0_ADDR      0xff000300
    48 #define    TCR0_ADDR      0xff000304
    49 #define    TMR0_ADDR      0xff000308
    50 #define    TRR1_ADDR      0xff000310
    51 #define    TCR1_ADDR      0xff000314
    52 #define    TMR1_ADDR      0xff000318
     13/* i960RP control structures */
     14
     15/* Intel i960RP Control Table */
     16
     17typedef struct {
     18                            /* Control Group 0 */
     19  unsigned int rsvd00;
     20  unsigned int rsvd01;
     21  unsigned int rsvd02;
     22  unsigned int rsvd03;
     23                            /* Control Group 1 */
     24  unsigned int imap0;             /* interrupt map 0 */
     25  unsigned int imap1;             /* interrupt map 1 */
     26  unsigned int imap2;             /* interrupt map 2 */
     27  unsigned int icon;              /* interrupt control */
     28                            /* Control Group 2 */
     29  unsigned int pmcon0;            /* memory region 0 configuration */
     30  unsigned int rsvd1;
     31  unsigned int pmcon2;            /* memory region 2 configuration */
     32  unsigned int rsvd2;
     33                            /* Control Group 3 */
     34  unsigned int pmcon4;            /* memory region 4 configuration */
     35  unsigned int rsvd3;
     36  unsigned int pmcon6;            /* memory region 6 configuration */
     37  unsigned int rsvd4;
     38                            /* Control Group 4 */
     39  unsigned int pmcon8;            /* memory region 8 configuration */
     40  unsigned int rsvd5;
     41  unsigned int pmcon10;           /* memory region 10 configuration */
     42  unsigned int rsvd6;
     43                            /* Control Group 5 */
     44  unsigned int pmcon12;           /* memory region 12 configuration */
     45  unsigned int rsvd7;
     46  unsigned int pmcon14;           /* memory region 14 configuration */
     47  unsigned int rsvd8;
     48                            /* Control Group 6 */
     49  unsigned int rsvd9;
     50  unsigned int rsvd10;
     51  unsigned int tc;                /* trace control */
     52  unsigned int bcon;              /* bus configuration control */
     53}   i960rp_control_table;
     54
     55/* Intel i960RP Processor Control Block */
     56
     57/* Intel i960RP Processor Control Block */
     58
     59typedef struct { 
     60  unsigned int    *fault_tbl;     /* fault table base address */
     61  i960rp_control_table
     62                  *control_tbl;   /* control table base address */
     63  unsigned int     initial_ac;    /* AC register initial value */
     64  unsigned int     fault_config;  /* fault configuration word */
     65  void           **intr_tbl;      /* interrupt table base address */
     66  void            *sys_proc_tbl;  /* system procedure table
     67                                     base address */
     68  unsigned int     reserved;      /* reserved */
     69  unsigned int    *intr_stack;    /* interrupt stack pointer */
     70  unsigned int     ins_cache_cfg; /* instruction cache
     71                                     configuration word */
     72  unsigned int     reg_cache_cfg; /* register cache configuration word */
     73}   i960rp_PRCB;
     74
     75typedef i960rp_control_table i960_control_table;
     76typedef i960rp_PRCB i960_PRCB;
     77
     78/* Addresses shared with JX */
     79
     80#include <libcpu/i960JX_RP_common.h>
    5381
    5482/* RP-only addresses: */
     
    315343#define RP_PRI_MEM_WIND_BASE    0x80000000
    316344
     345#define i960_unmask_intr( xint ) \
     346 { register unsigned int _mask= (1<<(xint)); \
     347   register unsigned int *_imsk = (int * ) IMSK_ADDR; \
     348   register unsigned int _val= *_imsk; \
     349   asm volatile( "or %0,%2,%0; \
     350                  st %0,(%1)" \
     351                    : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
     352                    : "0" (_val), "1" (_imsk), "2" (_mask) ); \
     353 }
     354
     355#define i960_mask_intr( xint ) \
     356 { register unsigned int _mask= (1<<(xint)); \
     357   register unsigned int *_imsk = (int * ) IMSK_ADDR; \
     358   register unsigned int _val = *_imsk; \
     359   asm volatile( "andnot %2,%0,%0; \
     360                  st %0,(%1)" \
     361                    : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
     362                    : "0" (_val), "1" (_imsk), "2" (_mask) ); \
     363 }
     364#define i960_clear_intr( xint ) \
     365 { register unsigned int _xint=xint; \
     366   register unsigned int _mask=(1<<(xint)); \
     367   register unsigned int *_ipnd = (int * ) IPND_ADDR; \
     368   register unsigned int          _rslt = 0; \
     369asm volatile( "loop_til_cleared: mov 0, %0; \
     370                  atmod %1, %2, %0; \
     371                  bbs    %3,%0, loop_til_cleared" \
     372                  : "=d" (_rslt), "=d" (_ipnd), "=d" (_mask), "=d" (_xint) \
     373                  : "0"  (_rslt), "1"  (_ipnd), "2"  (_mask), "3"  (_xint) ); \
     374 }
     375
     376static inline unsigned int i960_pend_intrs()
     377{ register unsigned int _intr= *(unsigned int *) IPND_ADDR;
     378  /*register unsigned int *_ipnd = (int * ) IPND_ADDR; \
     379   asm volatile( "mov (%0),%1" \
     380                    : "=d" (_ipnd), "=d" (_mask) \
     381                    : "0" (_ipnd), "1" (_mask) ); \ */
     382  return ( _intr );
     383}
     384
     385static inline unsigned int i960_mask_intrs()
     386{ register unsigned int _intr= *(unsigned int *) IMSK_ADDR;
     387  /*asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );*/
     388  return( _intr );
     389}
     390
     391#define I960_SOFT_RESET_COMMAND 0x300
     392
     393#define i960_soft_reset( prcb ) \
     394 { register i960_PRCB    *_prcb = (prcb); \
     395   register unsigned int *_next=0; \
     396   register unsigned int  _cmd  = I960_SOFT_RESET_COMMAND; \
     397   asm volatile( "lda    next,%1; \
     398                  sysctl %0,%1,%2; \
     399            next: mov    g0,g0" \
     400                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
     401                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
     402 }
     403
     404
    317405#endif
    318406/* end of include file */
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