Changeset bc85fd5a in rtems


Ignore:
Timestamp:
Jul 11, 2000, 7:31:04 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
073e2411
Parents:
9e52b29
Message:

Reworked score/cpu/i960 so it can be safely compiled multilib. All
routines and structures that require CPU model specific information
are now in libcpu. This required significant rework of the
score/cpu header files and the creation of multiple header files
and subdirectories in libcpu/i960.

Files:
17 added
26 edited
1 moved

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/i960/Makefile.am

    r9e52b29 rbc85fd5a  
    1111C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
    1212
    13 H_FILES = asm.h i960RP.h
     13H_FILES = asm.h
    1414
    1515S_FILES = cpu_asm.S
  • c/src/exec/score/cpu/i960/cpu.c

    r9e52b29 rbc85fd5a  
    1212 *  $Id$
    1313 */
    14 /*
    15  * 1999/04/26: added support for Intel i960RP
    16  */
    17 
    18 #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
    19 #elif defined(__i960RP__)
    20 #elif defined(__i960KA__)
    21 
    22 #else
    23 #warning "***  ENTIRE FILE IMPLEMENTED & TESTED FOR CA & RP ONLY  ***"
    24 #warning "*** THIS FILE WILL NOT COMPILE ON ANOTHER FAMILY MEMBER ***"
    25 #endif
    2614
    2715#include <rtems/system.h>
     
    6553/*PAGE
    6654 *
    67  *  _CPU_ISR_install_raw_handler
    68  */
    69 
    70 #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
    71 #define i960_vector_caching_enabled( _prcb ) \
    72    ((_prcb)->control_tbl->icon & 0x2000)
    73 #elif defined(__i960RP__)
    74 #define i960_vector_caching_enabled( _prcb ) \
    75    ((*((unsigned int *) ICON_ADDR)) & 0x2000)
    76 #elif defined(__i960KA__)
    77 #define i960_vector_caching_enabled( _prcb ) 0
    78 #endif
    79 
    80 void _CPU_ISR_install_raw_handler(
    81   unsigned32  vector,
    82   proc_ptr    new_handler,
    83   proc_ptr   *old_handler
    84 )
    85 {
    86   i960_PRCB   *prcb = _CPU_Table.Prcb;
    87   proc_ptr    *cached_intr_tbl = NULL;
    88 
    89   /*  The i80960CA does not support vectors 0-7.  The first 9 entries
    90    *  in the Interrupt Table are used to manage pending interrupts.
    91    *  Thus vector 8, the first valid vector number, is actually in
    92    *  slot 9 in the table.
    93    */
    94 
    95   *old_handler = prcb->intr_tbl[ vector + 1 ];
    96 
    97   prcb->intr_tbl[ vector + 1 ] = new_handler;
    98 
    99   if ( i960_vector_caching_enabled( prcb ) )
    100     if ( (vector & 0xf) == 0x2 )       /* cacheable? */
    101       cached_intr_tbl[ vector >> 4 ] = new_handler;
    102 }
    103 
    104 /*PAGE
    105  *
    10655 *  _CPU__ISR_install_vector
    10756 *
     
    13180  _ISR_Vector_table[ vector ] = new_handler;
    13281}
    133 
    134 /*PAGE
    135  *
    136  *  _CPU_Install_interrupt_stack
    137  */
    138 
    139 #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
    140 #define soft_reset( prcb ) \
    141  { register i960_PRCB *_prcb = (prcb); \
    142    register unsigned32  *_next=0; \
    143    register unsigned32   _cmd  = 0x30000; \
    144    asm volatile( "lda    next,%1; \
    145                   sysctl %0,%1,%2; \
    146             next: mov    g0,g0" \
    147                   : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
    148                   : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
    149  }
    150 #elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP)
    151 #define soft_reset( prcb ) \
    152  { register i960_PRCB *_prcb = (prcb); \
    153    register unsigned32  *_next=0; \
    154    register unsigned32   _cmd  = 0x300; \
    155    asm volatile( "lda    next,%1; \
    156                   sysctl %0,%1,%2; \
    157             next: mov    g0,g0" \
    158                   : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
    159                   : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
    160  }
    161 #elif defined(__i960KA__)
    162 #define soft_reset( prcb )
    163 #endif
    164 
    165 void _CPU_Install_interrupt_stack( void )
    166 {
    167   i960_PRCB *prcb = _CPU_Table.Prcb;
    168   unsigned32   level;
    169 #if defined(__i960RP__) || defined(__i960_RP__)
    170   unsigned32 *isp = (int *) ISP_ADDR;
    171 #endif
    172 
    173   /*
    174    *  Set the Interrupt Stack in the PRCB and force a reload of it.
    175    *  Interrupts are disabled for safety.
    176    */
    177 
    178   _CPU_ISR_Disable( level );
    179 
    180   prcb->intr_stack = _CPU_Interrupt_stack_low;
    181 
    182 #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
    183     soft_reset( prcb );
    184 #elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP)
    185     *isp = (unsigned32) prcb->intr_stack;
    186 #endif
    187 
    188   _CPU_ISR_Enable( level );
    189 }
  • c/src/exec/score/cpu/i960/cpu_asm.S

    r9e52b29 rbc85fd5a  
    1 /*  cpu_asm.s
    2  *
    3  *  This file contains all assembly code for the i960CA implementation
    4  *  of RTEMS.
     1/*
     2 *  This file contains all assembly code for the i960 port of RTEMS.
    53 *
    64 *  COPYRIGHT (c) 1989-1999.
     
    1412 */
    1513        .data
    16         .align 4
    17 _soft_reset_reg_save:
    18         .word  0
    19         .word  0
    20         .word  0
    21         .word  0
    2214_ISR_reg_save:
    2315        .word  0
     
    218210        ret
    219211
    220 
    221 #if !defined(__i960KA__)
    222 /*PAGE
    223  *
    224  *  void __i960_soft_reset_asm
    225  *
    226  *  Flush the register cache and save the important (fp, pfp, sp) registers,
    227  *  which are clobbered by the reinit operation. (Not documented, but it happens).
    228  */
    229 
    230                 .globl __i960_soft_reset_asm
    231 __i960_soft_reset_asm:
    232                 flushreg                                                                # flush register cache
    233                 mov                     fp, r4
    234                 mov                     pfp, r5
    235                 mov                     sp, r6
    236                 stt                     r4, _soft_reset_reg_save    # save fp, pfp, sp
    237                 lda                     __i960_reset_done, r4
    238                 ldconst         0x300, r5
    239                 sysctl          r5, r4, g0                  # reinit: clobbers almost all registers
    240 __i960_reset_done:
    241                 ldt             _soft_reset_reg_save, r4    # restore fp, pfp, sp
    242                 mov                     r4, fp
    243                 mov                     r5, pfp
    244                 mov                     r6, sp
    245                 ret
    246 #endif
  • c/src/exec/score/cpu/i960/rtems/score/cpu.h

    r9e52b29 rbc85fd5a  
    166166  void       (*stack_free_hook)( void* );
    167167  /* end of fields required on all CPUs */
    168 
    169   i960_PRCB *Prcb;
    170168}   rtems_cpu_table;
    171169
     
    177175/*
    178176 *  Macros to access i960 specific additions to the CPU Table
    179  */
    180 
    181 #define rtems_cpu_configuration_get_prcb() \
    182    (_CPU_Table.Prcb)
     177 *
     178 *  NONE
     179 */
    183180
    184181/* variables */
  • c/src/exec/score/cpu/i960/rtems/score/i960.h

    r9e52b29 rbc85fd5a  
    3434 */
    3535
    36 #if defined(rtems_multilib)
    37 /*
    38  *  Figure out all CPU Model Feature Flags based upon compiler
    39  *  predefines.
    40  */
    41 
    42 #define CPU_MODEL_NAME  "rtems_multilib"
    43 #define I960_HAS_FPU 0
    44 #define I960_CPU_ALIGNMENT 4
    45 #define I960_SOFT_RESET_COMMAND 0x30000
    46 
    47 #elif defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
    48 
    49 #define CPU_MODEL_NAME  "i960ca"
    50 #define __RTEMS_I960CA__
    51 
    52 #elif defined(__i960KA__)
    53 #define CPU_MODEL_NAME  "i960ka"
    54 
    55 #elif defined(__i960HA__) || defined(__i960_HA__) || defined(__i960HA)
    56 
    57 #define CPU_MODEL_NAME  "i960ha"
    58 #define __RTEMS_I960HA__
    59 
    60 #elif defined(__i960RP__)
    61 
    62 #include <i960RP.h>
    63 #define CPU_MODEL_NAME  "i960rp"
    64 #define __RTEMS_I960RP__
    65 #define I960_CPU_ALIGNMENT 8
    66 #define I960_SOFT_RESET_COMMAND 0x300
    67 
    68 #else
    69 
    70 #error "Unsupported CPU Model"
    71 
    72 #endif
    73 
    74 /*
    75  *  Now default some CPU model variation parameters
    76  */
    77 
    78 #ifndef I960_HAS_FPU
    79 #define I960_HAS_FPU 0
    80 #endif
    81 
    82 #ifndef I960_CPU_ALIGNMENT
    83 #define I960_CPU_ALIGNMENT 4
    84 #endif
    85 
    86 #ifndef I960_SOFT_RESET_COMMAND
    87 #define I960_SOFT_RESET_COMMAND 0x30000
    88 #endif
    89 
    9036/*
    9137 *  Define the name of the CPU family.
     
    9440#define CPU_NAME "Intel i960"
    9541
    96 #ifndef ASM
    97 
    9842/*
    99  * XXX    should have an ifdef here and have stuff for the other
    100  * XXX    family members...
    101  */
    102  
    103 #if defined(__RTEMS_I960CA__)
    104 /*
    105  *  Now default some CPU model variation parameters
     43 *  This should work since most i960 models do not have FPUs. The logic is:
     44 *
     45 *    + If the user specifically asks for soft-float, give it to them
     46 *      regardless of hardware availability.
     47 *    + If the CPU has hardware FPU, then use it.
     48 *    + Otherwise, we have to use soft float.
    10649 */
    10750
    108 #ifndef I960_HAS_FPU
     51#if defined(_SOFT_FLOAT)
     52#define I960_HAS_FPU 0
     53#elif defined(_i960_KB__) || defined(_i960_SB__) || defined(_i960_SB__) || \
     54      defined(_i960_JF__) || defined(_i960_MC__) || defined(_i960_CC__)
     55#define I960_HAS_FPU 1
     56#else
    10957#define I960_HAS_FPU 0
    11058#endif
    11159
    112 #ifndef I960_CPU_ALIGNMENT
     60/*
     61 *  Some of the CPU models may have better performance with
     62 *  alignment of 8 or 16 but we don't know what model we are
     63 *  being compiled for based solely on the information provided
     64 *  when multilibbing.
     65 */
     66
    11367#define I960_CPU_ALIGNMENT 4
     68
     69/*
     70 *  This is not the perfect CPU model name but it is adequate and
     71 *  reflects what we know from multilib.
     72 */
     73
     74#if I960_HAS_FPU
     75#define CPU_MODEL_NAME "i960 w/FPU"
     76#else
     77#define CPU_MODEL_NAME "i960 w/soft-float"
    11478#endif
     79#ifndef ASM
    11580
    116  
    117 /* i960CA control structures */
    118  
    119 /* Intel i960CA Control Table */
    120  
    121 typedef struct {
    122                             /* Control Group 0 */
    123   unsigned int ipb0;              /* IP breakpoint 0 */
    124   unsigned int ipb1;              /* IP breakpoint 1 */
    125   unsigned int dab0;              /* data address breakpoint 0 */
    126   unsigned int dab1;              /* data address breakpoint 1 */
    127                             /* Control Group 1 */
    128   unsigned int imap0;             /* interrupt map 0 */
    129   unsigned int imap1;             /* interrupt map 1 */
    130   unsigned int imap2;             /* interrupt map 2 */
    131   unsigned int icon;              /* interrupt control */
    132                             /* Control Group 2 */
    133   unsigned int mcon0;             /* memory region 0 configuration */
    134   unsigned int mcon1;             /* memory region 1 configuration */
    135   unsigned int mcon2;             /* memory region 2 configuration */
    136   unsigned int mcon3;             /* memory region 3 configuration */
    137                             /* Control Group 3 */
    138   unsigned int mcon4;             /* memory region 4 configuration */
    139   unsigned int mcon5;             /* memory region 5 configuration */
    140   unsigned int mcon6;             /* memory region 6 configuration */
    141   unsigned int mcon7;             /* memory region 7 configuration */
    142                             /* Control Group 4 */
    143   unsigned int mcon8;             /* memory region 8 configuration */
    144   unsigned int mcon9;             /* memory region 9 configuration */
    145   unsigned int mcon10;            /* memory region 10 configuration */
    146   unsigned int mcon11;            /* memory region 11 configuration */
    147                             /* Control Group 5 */
    148   unsigned int mcon12;            /* memory region 12 configuration */
    149   unsigned int mcon13;            /* memory region 13 configuration */
    150   unsigned int mcon14;            /* memory region 14 configuration */
    151   unsigned int mcon15;            /* memory region 15 configuration */
    152                             /* Control Group 6 */
    153   unsigned int reserved;          /* reserved */
    154   unsigned int bpcon;             /* breakpoint control */
    155   unsigned int tc;                /* trace control */
    156   unsigned int bcon;              /* bus configuration control */
    157 }   i960ca_control_table;
    158  
    159 /* Intel i960CA Processor Control Block */
    160  
    161 typedef struct {
    162   unsigned int    *fault_tbl;     /* fault table base address */
    163   i960ca_control_table
    164                   *control_tbl;   /* control table base address */
    165   unsigned int     initial_ac;    /* AC register initial value */
    166   unsigned int     fault_config;  /* fault configuration word */
    167   void           **intr_tbl;      /* interrupt table base address */
    168   void            *sys_proc_tbl;  /* system procedure table
    169                                      base address */
    170   unsigned int     reserved;      /* reserved */
    171   unsigned int    *intr_stack;    /* interrupt stack pointer */
    172   unsigned int     ins_cache_cfg; /* instruction cache
    173                                      configuration word */
    174   unsigned int     reg_cache_cfg; /* register cache configuration word */
    175 }   i960ca_PRCB;
    176 
    177 typedef i960ca_control_table i960_control_table;
    178 typedef i960ca_PRCB i960_PRCB;
    179 
    180 #elif defined(__RTEMS_I960HA__)
    181 
    182 /* i960HA control structures */
    183 
    184 /* Intel i960HA Control Table */
    185 
    186 typedef struct {
    187                             /* Control Group 0 */
    188   unsigned int ipb0;              /* IP breakpoint 0 */
    189   unsigned int ipb1;              /* IP breakpoint 1 */
    190   unsigned int dab0;              /* data address breakpoint 0 */
    191   unsigned int dab1;              /* data address breakpoint 1 */
    192                             /* Control Group 1 */
    193   unsigned int imap0;             /* interrupt map 0 */
    194   unsigned int imap1;             /* interrupt map 1 */
    195   unsigned int imap2;             /* interrupt map 2 */
    196   unsigned int icon;              /* interrupt control */
    197                             /* Control Group 2 */
    198   unsigned int mcon0;             /* memory region 0 configuration */
    199   unsigned int mcon1;             /* memory region 1 configuration */
    200   unsigned int mcon2;             /* memory region 2 configuration */
    201   unsigned int mcon3;             /* memory region 3 configuration */
    202                             /* Control Group 3 */
    203   unsigned int mcon4;             /* memory region 4 configuration */
    204   unsigned int mcon5;             /* memory region 5 configuration */
    205   unsigned int mcon6;             /* memory region 6 configuration */
    206   unsigned int mcon7;             /* memory region 7 configuration */
    207                             /* Control Group 4 */
    208   unsigned int mcon8;             /* memory region 8 configuration */
    209   unsigned int mcon9;             /* memory region 9 configuration */
    210   unsigned int mcon10;            /* memory region 10 configuration */
    211   unsigned int mcon11;            /* memory region 11 configuration */
    212                             /* Control Group 5 */
    213   unsigned int mcon12;            /* memory region 12 configuration */
    214   unsigned int mcon13;            /* memory region 13 configuration */
    215   unsigned int mcon14;            /* memory region 14 configuration */
    216   unsigned int mcon15;            /* memory region 15 configuration */
    217                             /* Control Group 6 */
    218   unsigned int reserved;          /* reserved */
    219   unsigned int bpcon;             /* breakpoint control */
    220   unsigned int tc;                /* trace control */
    221   unsigned int bcon;              /* bus configuration control */
    222 }   i960ha_control_table;
    223 
    224 /* Intel i960HA Processor Control Block */
    225 
    226 typedef struct {
    227   unsigned int    *fault_tbl;     /* fault table base address */
    228   i960ha_control_table
    229                   *control_tbl;   /* control table base address */
    230   unsigned int     initial_ac;    /* AC register initial value */
    231   unsigned int     fault_config;  /* fault configuration word */
    232   void           **intr_tbl;      /* interrupt table base address */
    233   void            *sys_proc_tbl;  /* system procedure table
    234                                      base address */
    235   unsigned int     reserved;      /* reserved */
    236   unsigned int    *intr_stack;    /* interrupt stack pointer */
    237   unsigned int     ins_cache_cfg; /* instruction cache
    238                                      configuration word */
    239   unsigned int     reg_cache_cfg; /* register cache configuration word */
    240 }   i960ha_PRCB;
    241 
    242 typedef i960ha_control_table i960_control_table;
    243 typedef i960ha_PRCB i960_PRCB;
    244 
    245 #elif defined(__RTEMS_I960RP__)
    246 
    247 /* i960RP control structures */
    248 
    249 /* Intel i960RP Control Table */
    250 
    251 typedef struct {
    252                             /* Control Group 0 */
    253   unsigned int rsvd00;
    254   unsigned int rsvd01;
    255   unsigned int rsvd02;
    256   unsigned int rsvd03;
    257                             /* Control Group 1 */
    258   unsigned int imap0;             /* interrupt map 0 */
    259   unsigned int imap1;             /* interrupt map 1 */
    260   unsigned int imap2;             /* interrupt map 2 */
    261   unsigned int icon;              /* interrupt control */
    262                             /* Control Group 2 */
    263   unsigned int pmcon0;            /* memory region 0 configuration */
    264   unsigned int rsvd1;
    265   unsigned int pmcon2;            /* memory region 2 configuration */
    266   unsigned int rsvd2;
    267                             /* Control Group 3 */
    268   unsigned int pmcon4;            /* memory region 4 configuration */
    269   unsigned int rsvd3;
    270   unsigned int pmcon6;            /* memory region 6 configuration */
    271   unsigned int rsvd4;
    272                             /* Control Group 4 */
    273   unsigned int pmcon8;            /* memory region 8 configuration */
    274   unsigned int rsvd5;
    275   unsigned int pmcon10;           /* memory region 10 configuration */
    276   unsigned int rsvd6;
    277                             /* Control Group 5 */
    278   unsigned int pmcon12;           /* memory region 12 configuration */
    279   unsigned int rsvd7;
    280   unsigned int pmcon14;           /* memory region 14 configuration */
    281   unsigned int rsvd8;
    282                             /* Control Group 6 */
    283   unsigned int rsvd9;
    284   unsigned int rsvd10;
    285   unsigned int tc;                /* trace control */
    286   unsigned int bcon;              /* bus configuration control */
    287 }   i960rp_control_table;
    288 
    289 /* Intel i960RP Processor Control Block */
    290 
    291 typedef struct {
    292   unsigned int    *fault_tbl;     /* fault table base address */
    293   i960rp_control_table
    294                   *control_tbl;   /* control table base address */
    295   unsigned int     initial_ac;    /* AC register initial value */
    296   unsigned int     fault_config;  /* fault configuration word */
    297   void           **intr_tbl;      /* interrupt table base address */
    298   void            *sys_proc_tbl;  /* system procedure table
    299                                      base address */
    300   unsigned int     reserved;      /* reserved */
    301   unsigned int    *intr_stack;    /* interrupt stack pointer */
    302   unsigned int     ins_cache_cfg; /* instruction cache
    303                                      configuration word */
    304   unsigned int     reg_cache_cfg; /* register cache configuration word */
    305 }   i960rp_PRCB;
    306 
    307 typedef i960rp_control_table i960_control_table;
    308 typedef i960rp_PRCB i960_PRCB;
    309 
    310 #elif defined(__i960KA__)
    311 
    312 /* i960KA control structures */
    313 
    314 /* Intel i960KA Control Table */
    315 
    316 typedef struct {
    317 int pad0;
    318 }   i960ka_control_table;
    319 
    320 /* Intel i960KA Processor Control Block */
    321 
    322 typedef struct {
    323   void           **intr_tbl;      /* interrupt table base address */
    324   unsigned int    *intr_stack;    /* interrupt stack pointer */
    325 }   i960ka_PRCB;
    326 
    327 typedef i960ka_control_table i960_control_table;
    328 typedef i960ka_PRCB i960_PRCB;
    329 
    330 #else
    331 #error "invalid processor selection!"
    332 #endif
    33381
    33482/*
     
    33684 */
    33785
    338 #if !defined(__i960KA__)
    33986#define i960_reload_ctl_group( group ) \
    34087 { register int _cmd = ((group)|0x400) ; \
    34188   asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \
    34289 }
    343 #endif
    34490
    34591#define i960_atomic_modify( mask, addr, prev ) \
     
    394140  } while ( 0 )
    395141
    396 #if !defined(__i960KA__)
    397142#define i960_cause_intr( intr ) \
    398143 { register int _intr = (intr); \
    399144   asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \
    400145 }
    401 #endif
    402146
    403147/*
    404148 *  Interrupt Masking Routines
    405149 */
    406 
    407 #if defined(__RTEMS_I960CA__) || defined(__RTEMS_I960HA__)
    408 
    409 #define i960_unmask_intr( xint ) \
    410  { register unsigned int _mask= (1<<(xint)); \
    411    asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \
    412  }
    413 
    414 #define i960_mask_intr( xint ) \
    415  { register unsigned int _mask= (1<<(xint)); \
    416    asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \
    417  }
    418 
    419 #define i960_clear_intr( xint ) \
    420  { register unsigned int _xint=(xint); \
    421 asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \
    422                   bbs    %0,sf0, loop_til_cleared" \
    423                   : "=d" (_xint) : "0" (_xint) ); \
    424  }
    425 
    426 static inline unsigned int i960_pend_intrs()
    427 { register unsigned int _intr=0;
    428   asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) );
    429   return ( _intr );
    430 }
    431 
    432 static inline unsigned int i960_mask_intrs()
    433 { register unsigned int _intr=0;
    434   asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );
    435   return( _intr );
    436 }
    437 
    438 #elif defined(__RTEMS_I960RP__)
    439 
    440 #define i960_unmask_intr( xint ) \
    441  { register unsigned int _mask= (1<<(xint)); \
    442    register unsigned int *_imsk = (int * ) IMSK_ADDR; \
    443    register unsigned int _val= *_imsk; \
    444    asm volatile( "or %0,%2,%0; \
    445                   st %0,(%1)" \
    446                     : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
    447                     : "0" (_val), "1" (_imsk), "2" (_mask) ); \
    448  }
    449 
    450 #define i960_mask_intr( xint ) \
    451  { register unsigned int _mask= (1<<(xint)); \
    452    register unsigned int *_imsk = (int * ) IMSK_ADDR; \
    453    register unsigned int _val = *_imsk; \
    454    asm volatile( "andnot %2,%0,%0; \
    455                   st %0,(%1)" \
    456                     : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
    457                     : "0" (_val), "1" (_imsk), "2" (_mask) ); \
    458  }
    459 #define i960_clear_intr( xint ) \
    460  { register unsigned int _xint=xint; \
    461    register unsigned int _mask=(1<<(xint)); \
    462    register unsigned int *_ipnd = (int * ) IPND_ADDR; \
    463    register unsigned int          _rslt = 0; \
    464 asm volatile( "loop_til_cleared: mov 0, %0; \
    465                   atmod %1, %2, %0; \
    466                   bbs    %3,%0, loop_til_cleared" \
    467                   : "=d" (_rslt), "=d" (_ipnd), "=d" (_mask), "=d" (_xint) \
    468                   : "0"  (_rslt), "1"  (_ipnd), "2"  (_mask), "3"  (_xint) ); \
    469  }
    470 
    471 static inline unsigned int i960_pend_intrs()
    472 { register unsigned int _intr= *(unsigned int *) IPND_ADDR;
    473   /*register unsigned int *_ipnd = (int * ) IPND_ADDR; \
    474    asm volatile( "mov (%0),%1" \
    475                     : "=d" (_ipnd), "=d" (_mask) \
    476                     : "0" (_ipnd), "1" (_mask) ); \ */
    477   return ( _intr );
    478 }
    479 
    480 static inline unsigned int i960_mask_intrs()
    481 { register unsigned int _intr= *(unsigned int *) IMSK_ADDR;
    482   /*asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );*/
    483   return( _intr );
    484 }
    485 #endif
    486150
    487151static inline unsigned int i960_get_fp()
     
    490154  return ( _fp );
    491155}
    492 
    493 /*
    494  *  Soft Reset
    495  */
    496 
    497 #if defined(I960_SOFT_RESET_COMMAND)
    498 #define i960_soft_reset( prcb ) \
    499  { register i960_PRCB    *_prcb = (prcb); \
    500    register unsigned int *_next=0; \
    501    register unsigned int  _cmd  = I960_SOFT_RESET_COMMAND; \
    502    asm volatile( "lda    next,%1; \
    503                   sysctl %0,%1,%2; \
    504             next: mov    g0,g0" \
    505                   : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
    506                   : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
    507  }
    508 
    509 #elif !defined(__i960KA__)
    510 #warning "I960_SOFT_RESET_COMMAND is not defined"
    511 #endif
    512156
    513157/*
  • c/src/lib/libbsp/i960/cvme961/include/bsp.h

    r9e52b29 rbc85fd5a  
    2323
    2424#include <rtems.h>
     25#include <libcpu/i960CA.h>
    2526#include <iosupp.h>
    2627#include <console.h>
  • c/src/lib/libbsp/i960/cvme961/startup/bspstart.c

    r9e52b29 rbc85fd5a  
    109109  Cpu_table.postdriver_hook = bsp_postdriver_hook;
    110110  Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
    111   Cpu_table.Prcb = Prcb;
    112111
    113112  BSP_Configuration.work_space_start = (void *)
  • c/src/lib/libbsp/i960/cvme961/wrapup/Makefile.am

    r9e52b29 rbc85fd5a  
    2020# bummer; have to use $foreach since % pattern subst rules only replace 1x
    2121OBJS = $(foreach piece, $(BSP_FILES), $(wildcard ../$(piece)/$(ARCH)/*.o)) \
    22     $(foreach piece, $(GENERIC_FILES), ../../../$(piece)/$(ARCH)/$(piece).rel)
     22  $(wildcard ../../../../libcpu/$(RTEMS_CPU)/$(RTEMS_CPU_MODEL)/$(ARCH)/*.o) \
     23  $(foreach piece, $(GENERIC_FILES), ../../../$(piece)/$(ARCH)/$(piece).rel)
    2324
    2425LIB = $(ARCH)/libbsp.a
  • c/src/lib/libbsp/i960/i960sim/include/bsp.h

    r9e52b29 rbc85fd5a  
    1414 */
    1515
    16 #ifndef __CVME961_h
    17 #define __CVME961_h
     16#ifndef __I960SIM_h
     17#define __I960SIM_h
    1818
    1919#ifdef __cplusplus
  • c/src/lib/libbsp/i960/i960sim/startup/bspstart.c

    r9e52b29 rbc85fd5a  
    7878 */
    7979
     80#include <libcpu/i960KA.h>
     81
     82i960_PRCB *Prcb; /* to satisfy linking */
     83
    8084void bsp_start( void )
    8185{
     
    8791  Cpu_table.postdriver_hook = bsp_postdriver_hook;
    8892  Cpu_table.interrupt_stack_size = 4096;
    89   Cpu_table.Prcb = 0; /* Prcb; */
    9093
    9194  if ( BSP_Configuration.work_space_size >(512*1024) )
  • c/src/lib/libbsp/i960/i960sim/wrapup/Makefile.am

    r9e52b29 rbc85fd5a  
    1212# bummer; have to use $foreach since % pattern subst rules only replace 1x
    1313OBJS = $(foreach piece, $(BSP_FILES), $(wildcard ../$(piece)/$(ARCH)/*.o)) \
    14     $(foreach piece, $(GENERIC_FILES), ../../../$(piece)/$(ARCH)/$(piece).rel)
     14  $(wildcard ../../../../libcpu/$(RTEMS_CPU)/$(RTEMS_CPU_MODEL)/$(ARCH)/*.o) \
     15  $(foreach piece, $(GENERIC_FILES), ../../../$(piece)/$(ARCH)/$(piece).rel)
    1516
    1617LIB = $(ARCH)/libbsp.a
  • c/src/lib/libbsp/i960/rxgen960/clock/ckinit.c

    r9e52b29 rbc85fd5a  
    2323
    2424#include <bsp.h>
    25 #include <i960RP.h>
    2625#include <rtems/libio.h>
    2726
  • c/src/lib/libbsp/i960/rxgen960/include/bsp.h

    r9e52b29 rbc85fd5a  
    2323
    2424#include <rtems.h>
     25#include <libcpu/i960RP.h>
    2526#include <iosupp.h>
    2627#include <console.h>
  • c/src/lib/libbsp/i960/rxgen960/startup/bspstart.c

    r9e52b29 rbc85fd5a  
    2929#include <fcntl.h>
    3030#include <stdio.h>
    31 #include "i960RP.h"
    3231#include <rtems/libio.h>
    3332 
    34 #ifdef STACK_CHECKER_ON
    35 #include <stackchk.h>
    36 #endif
    37 
    3833#define HEAP_SIZE 1024*1024*2
    3934
     
    8580
    8681
    87 #ifdef STACK_CHECKER_ON
    88     /*
    89      *  Initialize the stack bounds checker
    90      *  We can either turn it on here or from the app.
    91      */
    92  
    93 *(unsigned char *)(0x120f) = 0xe;
    94     Stack_check_Initialize();
    95 #endif
    96  
    9782#ifdef RTEMS_DEBUG
    9883    rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
     
    135120  Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
    136121  Cpu_table.extra_mpci_receive_server_stack = 0;
    137   Cpu_table.Prcb = Prcb;
    138122
    139123  /* just trying to get along */
  • c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.c

    r9e52b29 rbc85fd5a  
    77 */
    88
    9 #include "i960RP.h"
     9#include <bsp.h>
    1010#include "cntrltbl.h"
    1111/*-------------------------------------*/
  • c/src/lib/libbsp/i960/rxgen960/startup/rom_cntrltbl.c

    r9e52b29 rbc85fd5a  
    77 */
    88
    9 #include <i960RP.h>
     9#include <bsp.h>
    1010#include "cntrltbl.h"
    1111/*-------------------------------------*/
  • c/src/lib/libbsp/i960/rxgen960/startup/rom_ibr.c

    r9e52b29 rbc85fd5a  
    1010#include "prcb.h"
    1111#include "cntrltbl.h"
    12 #include <i960RP.h>
     12#include <bsp.h>
    1313#include "../include/rxgen960_config.h"
    1414/*-------------------------------------*/
  • c/src/lib/libbsp/i960/rxgen960/timer/timer.c

    r9e52b29 rbc85fd5a  
    2828
    2929
    30 #include <rtems.h>
    3130#include <bsp.h>
    3231#include <stdlib.h>
    33 #include <i960RP.h>
    3432#include <rtems/libio.h>
    3533
  • c/src/lib/libbsp/i960/rxgen960/wrapup/Makefile.am

    r9e52b29 rbc85fd5a  
    2020# bummer; have to use $foreach since % pattern subst rules only replace 1x
    2121OBJS = $(foreach piece, $(BSP_PIECES), $(wildcard ../$(piece)/$(ARCH)/*.o)) \
    22     $(foreach piece, $(GENERIC_PIECES), ../../../$(piece)/$(ARCH)/$(piece).rel)
     22  $(wildcard ../../../../libcpu/$(RTEMS_CPU)/$(RTEMS_CPU_MODEL)/$(ARCH)/*.o) \
     23  $(foreach piece, $(GENERIC_PIECES), ../../../$(piece)/$(ARCH)/$(piece).rel)
    2324LIB = $(ARCH)/libbsp.a
    2425
  • c/src/lib/libcpu/i960/include/i960RP.h

    r9e52b29 rbc85fd5a  
    1111#define __I960RP_h
    1212
    13 /*----------------------------------------------------------*/
    14 /*  Example 6. Include File (evrp.h)                        */
    15 /*----------------------------------------------------------*/
    16 /* Define JX Core memory mapped register addresses */
    17 /* Common to Jx and RP: */
    18 #define    DLMCON_ADDR    0xff008100
    19 #define    LMAR0_ADDR     0xff008108
    20 #define    LMMR0_ADDR     0xff00810c
    21 #define    LMAR1_ADDR     0xff008110
    22 #define    LMMR1_ADDR     0xff008114
    23 #define    IPB0_ADDR      0xff008400
    24 #define    IPB1_ADDR      0xff008404
    25 #define    DAB0_ADDR      0xff008420
    26 #define    DAB1_ADDR      0xff008424
    27 #define    BPCON_ADDR     0xff008440
    28 #define    IPND_ADDR      0xff008500
    29 #define    IMSK_ADDR      0xff008504
    30 #define    ICON_ADDR      0xff008510
    31 #define    IMAP0_ADDR     0xff008520
    32 #define    IMAP1_ADDR     0xff008524
    33 #define    IMAP2_ADDR     0xff008528
    34 #define    PMCON0_ADDR    0xff008600
    35 #define    PMCON2_ADDR    0xff008608
    36 #define    PMCON4_ADDR    0xff008610
    37 #define    PMCON6_ADDR    0xff008618
    38 #define    PMCON8_ADDR    0xff008620
    39 #define    PMCON10_ADDR   0xff008628
    40 #define    PMCON12_ADDR   0xff008630
    41 #define    PMCON14_ADDR   0xff008638
    42 #define    BCON_ADDR      0xff0086fc
    43 #define    PRCB_ADDR      0xff008700
    44 #define    ISP_ADDR       0xff008704
    45 #define    SSP_ADDR       0xff008708
    46 #define    DEVID_ADDR     0xff008710
    47 #define    TRR0_ADDR      0xff000300
    48 #define    TCR0_ADDR      0xff000304
    49 #define    TMR0_ADDR      0xff000308
    50 #define    TRR1_ADDR      0xff000310
    51 #define    TCR1_ADDR      0xff000314
    52 #define    TMR1_ADDR      0xff000318
     13/* i960RP control structures */
     14
     15/* Intel i960RP Control Table */
     16
     17typedef struct {
     18                            /* Control Group 0 */
     19  unsigned int rsvd00;
     20  unsigned int rsvd01;
     21  unsigned int rsvd02;
     22  unsigned int rsvd03;
     23                            /* Control Group 1 */
     24  unsigned int imap0;             /* interrupt map 0 */
     25  unsigned int imap1;             /* interrupt map 1 */
     26  unsigned int imap2;             /* interrupt map 2 */
     27  unsigned int icon;              /* interrupt control */
     28                            /* Control Group 2 */
     29  unsigned int pmcon0;            /* memory region 0 configuration */
     30  unsigned int rsvd1;
     31  unsigned int pmcon2;            /* memory region 2 configuration */
     32  unsigned int rsvd2;
     33                            /* Control Group 3 */
     34  unsigned int pmcon4;            /* memory region 4 configuration */
     35  unsigned int rsvd3;
     36  unsigned int pmcon6;            /* memory region 6 configuration */
     37  unsigned int rsvd4;
     38                            /* Control Group 4 */
     39  unsigned int pmcon8;            /* memory region 8 configuration */
     40  unsigned int rsvd5;
     41  unsigned int pmcon10;           /* memory region 10 configuration */
     42  unsigned int rsvd6;
     43                            /* Control Group 5 */
     44  unsigned int pmcon12;           /* memory region 12 configuration */
     45  unsigned int rsvd7;
     46  unsigned int pmcon14;           /* memory region 14 configuration */
     47  unsigned int rsvd8;
     48                            /* Control Group 6 */
     49  unsigned int rsvd9;
     50  unsigned int rsvd10;
     51  unsigned int tc;                /* trace control */
     52  unsigned int bcon;              /* bus configuration control */
     53}   i960rp_control_table;
     54
     55/* Intel i960RP Processor Control Block */
     56
     57/* Intel i960RP Processor Control Block */
     58
     59typedef struct { 
     60  unsigned int    *fault_tbl;     /* fault table base address */
     61  i960rp_control_table
     62                  *control_tbl;   /* control table base address */
     63  unsigned int     initial_ac;    /* AC register initial value */
     64  unsigned int     fault_config;  /* fault configuration word */
     65  void           **intr_tbl;      /* interrupt table base address */
     66  void            *sys_proc_tbl;  /* system procedure table
     67                                     base address */
     68  unsigned int     reserved;      /* reserved */
     69  unsigned int    *intr_stack;    /* interrupt stack pointer */
     70  unsigned int     ins_cache_cfg; /* instruction cache
     71                                     configuration word */
     72  unsigned int     reg_cache_cfg; /* register cache configuration word */
     73}   i960rp_PRCB;
     74
     75typedef i960rp_control_table i960_control_table;
     76typedef i960rp_PRCB i960_PRCB;
     77
     78/* Addresses shared with JX */
     79
     80#include <libcpu/i960JX_RP_common.h>
    5381
    5482/* RP-only addresses: */
     
    315343#define RP_PRI_MEM_WIND_BASE    0x80000000
    316344
     345#define i960_unmask_intr( xint ) \
     346 { register unsigned int _mask= (1<<(xint)); \
     347   register unsigned int *_imsk = (int * ) IMSK_ADDR; \
     348   register unsigned int _val= *_imsk; \
     349   asm volatile( "or %0,%2,%0; \
     350                  st %0,(%1)" \
     351                    : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
     352                    : "0" (_val), "1" (_imsk), "2" (_mask) ); \
     353 }
     354
     355#define i960_mask_intr( xint ) \
     356 { register unsigned int _mask= (1<<(xint)); \
     357   register unsigned int *_imsk = (int * ) IMSK_ADDR; \
     358   register unsigned int _val = *_imsk; \
     359   asm volatile( "andnot %2,%0,%0; \
     360                  st %0,(%1)" \
     361                    : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
     362                    : "0" (_val), "1" (_imsk), "2" (_mask) ); \
     363 }
     364#define i960_clear_intr( xint ) \
     365 { register unsigned int _xint=xint; \
     366   register unsigned int _mask=(1<<(xint)); \
     367   register unsigned int *_ipnd = (int * ) IPND_ADDR; \
     368   register unsigned int          _rslt = 0; \
     369asm volatile( "loop_til_cleared: mov 0, %0; \
     370                  atmod %1, %2, %0; \
     371                  bbs    %3,%0, loop_til_cleared" \
     372                  : "=d" (_rslt), "=d" (_ipnd), "=d" (_mask), "=d" (_xint) \
     373                  : "0"  (_rslt), "1"  (_ipnd), "2"  (_mask), "3"  (_xint) ); \
     374 }
     375
     376static inline unsigned int i960_pend_intrs()
     377{ register unsigned int _intr= *(unsigned int *) IPND_ADDR;
     378  /*register unsigned int *_ipnd = (int * ) IPND_ADDR; \
     379   asm volatile( "mov (%0),%1" \
     380                    : "=d" (_ipnd), "=d" (_mask) \
     381                    : "0" (_ipnd), "1" (_mask) ); \ */
     382  return ( _intr );
     383}
     384
     385static inline unsigned int i960_mask_intrs()
     386{ register unsigned int _intr= *(unsigned int *) IMSK_ADDR;
     387  /*asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );*/
     388  return( _intr );
     389}
     390
     391#define I960_SOFT_RESET_COMMAND 0x300
     392
     393#define i960_soft_reset( prcb ) \
     394 { register i960_PRCB    *_prcb = (prcb); \
     395   register unsigned int *_next=0; \
     396   register unsigned int  _cmd  = I960_SOFT_RESET_COMMAND; \
     397   asm volatile( "lda    next,%1; \
     398                  sysctl %0,%1,%2; \
     399            next: mov    g0,g0" \
     400                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
     401                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
     402 }
     403
     404
    317405#endif
    318406/* end of include file */
  • cpukit/score/cpu/i960/Makefile.am

    r9e52b29 rbc85fd5a  
    1111C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
    1212
    13 H_FILES = asm.h i960RP.h
     13H_FILES = asm.h
    1414
    1515S_FILES = cpu_asm.S
  • cpukit/score/cpu/i960/cpu.c

    r9e52b29 rbc85fd5a  
    1212 *  $Id$
    1313 */
    14 /*
    15  * 1999/04/26: added support for Intel i960RP
    16  */
    17 
    18 #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
    19 #elif defined(__i960RP__)
    20 #elif defined(__i960KA__)
    21 
    22 #else
    23 #warning "***  ENTIRE FILE IMPLEMENTED & TESTED FOR CA & RP ONLY  ***"
    24 #warning "*** THIS FILE WILL NOT COMPILE ON ANOTHER FAMILY MEMBER ***"
    25 #endif
    2614
    2715#include <rtems/system.h>
     
    6553/*PAGE
    6654 *
    67  *  _CPU_ISR_install_raw_handler
    68  */
    69 
    70 #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
    71 #define i960_vector_caching_enabled( _prcb ) \
    72    ((_prcb)->control_tbl->icon & 0x2000)
    73 #elif defined(__i960RP__)
    74 #define i960_vector_caching_enabled( _prcb ) \
    75    ((*((unsigned int *) ICON_ADDR)) & 0x2000)
    76 #elif defined(__i960KA__)
    77 #define i960_vector_caching_enabled( _prcb ) 0
    78 #endif
    79 
    80 void _CPU_ISR_install_raw_handler(
    81   unsigned32  vector,
    82   proc_ptr    new_handler,
    83   proc_ptr   *old_handler
    84 )
    85 {
    86   i960_PRCB   *prcb = _CPU_Table.Prcb;
    87   proc_ptr    *cached_intr_tbl = NULL;
    88 
    89   /*  The i80960CA does not support vectors 0-7.  The first 9 entries
    90    *  in the Interrupt Table are used to manage pending interrupts.
    91    *  Thus vector 8, the first valid vector number, is actually in
    92    *  slot 9 in the table.
    93    */
    94 
    95   *old_handler = prcb->intr_tbl[ vector + 1 ];
    96 
    97   prcb->intr_tbl[ vector + 1 ] = new_handler;
    98 
    99   if ( i960_vector_caching_enabled( prcb ) )
    100     if ( (vector & 0xf) == 0x2 )       /* cacheable? */
    101       cached_intr_tbl[ vector >> 4 ] = new_handler;
    102 }
    103 
    104 /*PAGE
    105  *
    10655 *  _CPU__ISR_install_vector
    10756 *
     
    13180  _ISR_Vector_table[ vector ] = new_handler;
    13281}
    133 
    134 /*PAGE
    135  *
    136  *  _CPU_Install_interrupt_stack
    137  */
    138 
    139 #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
    140 #define soft_reset( prcb ) \
    141  { register i960_PRCB *_prcb = (prcb); \
    142    register unsigned32  *_next=0; \
    143    register unsigned32   _cmd  = 0x30000; \
    144    asm volatile( "lda    next,%1; \
    145                   sysctl %0,%1,%2; \
    146             next: mov    g0,g0" \
    147                   : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
    148                   : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
    149  }
    150 #elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP)
    151 #define soft_reset( prcb ) \
    152  { register i960_PRCB *_prcb = (prcb); \
    153    register unsigned32  *_next=0; \
    154    register unsigned32   _cmd  = 0x300; \
    155    asm volatile( "lda    next,%1; \
    156                   sysctl %0,%1,%2; \
    157             next: mov    g0,g0" \
    158                   : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
    159                   : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
    160  }
    161 #elif defined(__i960KA__)
    162 #define soft_reset( prcb )
    163 #endif
    164 
    165 void _CPU_Install_interrupt_stack( void )
    166 {
    167   i960_PRCB *prcb = _CPU_Table.Prcb;
    168   unsigned32   level;
    169 #if defined(__i960RP__) || defined(__i960_RP__)
    170   unsigned32 *isp = (int *) ISP_ADDR;
    171 #endif
    172 
    173   /*
    174    *  Set the Interrupt Stack in the PRCB and force a reload of it.
    175    *  Interrupts are disabled for safety.
    176    */
    177 
    178   _CPU_ISR_Disable( level );
    179 
    180   prcb->intr_stack = _CPU_Interrupt_stack_low;
    181 
    182 #if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
    183     soft_reset( prcb );
    184 #elif defined(__i960RP__) || defined(__i960_RP__) || defined(__i960RP)
    185     *isp = (unsigned32) prcb->intr_stack;
    186 #endif
    187 
    188   _CPU_ISR_Enable( level );
    189 }
  • cpukit/score/cpu/i960/cpu_asm.S

    r9e52b29 rbc85fd5a  
    1 /*  cpu_asm.s
    2  *
    3  *  This file contains all assembly code for the i960CA implementation
    4  *  of RTEMS.
     1/*
     2 *  This file contains all assembly code for the i960 port of RTEMS.
    53 *
    64 *  COPYRIGHT (c) 1989-1999.
     
    1412 */
    1513        .data
    16         .align 4
    17 _soft_reset_reg_save:
    18         .word  0
    19         .word  0
    20         .word  0
    21         .word  0
    2214_ISR_reg_save:
    2315        .word  0
     
    218210        ret
    219211
    220 
    221 #if !defined(__i960KA__)
    222 /*PAGE
    223  *
    224  *  void __i960_soft_reset_asm
    225  *
    226  *  Flush the register cache and save the important (fp, pfp, sp) registers,
    227  *  which are clobbered by the reinit operation. (Not documented, but it happens).
    228  */
    229 
    230                 .globl __i960_soft_reset_asm
    231 __i960_soft_reset_asm:
    232                 flushreg                                                                # flush register cache
    233                 mov                     fp, r4
    234                 mov                     pfp, r5
    235                 mov                     sp, r6
    236                 stt                     r4, _soft_reset_reg_save    # save fp, pfp, sp
    237                 lda                     __i960_reset_done, r4
    238                 ldconst         0x300, r5
    239                 sysctl          r5, r4, g0                  # reinit: clobbers almost all registers
    240 __i960_reset_done:
    241                 ldt             _soft_reset_reg_save, r4    # restore fp, pfp, sp
    242                 mov                     r4, fp
    243                 mov                     r5, pfp
    244                 mov                     r6, sp
    245                 ret
    246 #endif
  • cpukit/score/cpu/i960/rtems/score/cpu.h

    r9e52b29 rbc85fd5a  
    166166  void       (*stack_free_hook)( void* );
    167167  /* end of fields required on all CPUs */
    168 
    169   i960_PRCB *Prcb;
    170168}   rtems_cpu_table;
    171169
     
    177175/*
    178176 *  Macros to access i960 specific additions to the CPU Table
    179  */
    180 
    181 #define rtems_cpu_configuration_get_prcb() \
    182    (_CPU_Table.Prcb)
     177 *
     178 *  NONE
     179 */
    183180
    184181/* variables */
  • cpukit/score/cpu/i960/rtems/score/i960.h

    r9e52b29 rbc85fd5a  
    3434 */
    3535
    36 #if defined(rtems_multilib)
    37 /*
    38  *  Figure out all CPU Model Feature Flags based upon compiler
    39  *  predefines.
    40  */
    41 
    42 #define CPU_MODEL_NAME  "rtems_multilib"
    43 #define I960_HAS_FPU 0
    44 #define I960_CPU_ALIGNMENT 4
    45 #define I960_SOFT_RESET_COMMAND 0x30000
    46 
    47 #elif defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
    48 
    49 #define CPU_MODEL_NAME  "i960ca"
    50 #define __RTEMS_I960CA__
    51 
    52 #elif defined(__i960KA__)
    53 #define CPU_MODEL_NAME  "i960ka"
    54 
    55 #elif defined(__i960HA__) || defined(__i960_HA__) || defined(__i960HA)
    56 
    57 #define CPU_MODEL_NAME  "i960ha"
    58 #define __RTEMS_I960HA__
    59 
    60 #elif defined(__i960RP__)
    61 
    62 #include <i960RP.h>
    63 #define CPU_MODEL_NAME  "i960rp"
    64 #define __RTEMS_I960RP__
    65 #define I960_CPU_ALIGNMENT 8
    66 #define I960_SOFT_RESET_COMMAND 0x300
    67 
    68 #else
    69 
    70 #error "Unsupported CPU Model"
    71 
    72 #endif
    73 
    74 /*
    75  *  Now default some CPU model variation parameters
    76  */
    77 
    78 #ifndef I960_HAS_FPU
    79 #define I960_HAS_FPU 0
    80 #endif
    81 
    82 #ifndef I960_CPU_ALIGNMENT
    83 #define I960_CPU_ALIGNMENT 4
    84 #endif
    85 
    86 #ifndef I960_SOFT_RESET_COMMAND
    87 #define I960_SOFT_RESET_COMMAND 0x30000
    88 #endif
    89 
    9036/*
    9137 *  Define the name of the CPU family.
     
    9440#define CPU_NAME "Intel i960"
    9541
    96 #ifndef ASM
    97 
    9842/*
    99  * XXX    should have an ifdef here and have stuff for the other
    100  * XXX    family members...
    101  */
    102  
    103 #if defined(__RTEMS_I960CA__)
    104 /*
    105  *  Now default some CPU model variation parameters
     43 *  This should work since most i960 models do not have FPUs. The logic is:
     44 *
     45 *    + If the user specifically asks for soft-float, give it to them
     46 *      regardless of hardware availability.
     47 *    + If the CPU has hardware FPU, then use it.
     48 *    + Otherwise, we have to use soft float.
    10649 */
    10750
    108 #ifndef I960_HAS_FPU
     51#if defined(_SOFT_FLOAT)
     52#define I960_HAS_FPU 0
     53#elif defined(_i960_KB__) || defined(_i960_SB__) || defined(_i960_SB__) || \
     54      defined(_i960_JF__) || defined(_i960_MC__) || defined(_i960_CC__)
     55#define I960_HAS_FPU 1
     56#else
    10957#define I960_HAS_FPU 0
    11058#endif
    11159
    112 #ifndef I960_CPU_ALIGNMENT
     60/*
     61 *  Some of the CPU models may have better performance with
     62 *  alignment of 8 or 16 but we don't know what model we are
     63 *  being compiled for based solely on the information provided
     64 *  when multilibbing.
     65 */
     66
    11367#define I960_CPU_ALIGNMENT 4
     68
     69/*
     70 *  This is not the perfect CPU model name but it is adequate and
     71 *  reflects what we know from multilib.
     72 */
     73
     74#if I960_HAS_FPU
     75#define CPU_MODEL_NAME "i960 w/FPU"
     76#else
     77#define CPU_MODEL_NAME "i960 w/soft-float"
    11478#endif
     79#ifndef ASM
    11580
    116  
    117 /* i960CA control structures */
    118  
    119 /* Intel i960CA Control Table */
    120  
    121 typedef struct {
    122                             /* Control Group 0 */
    123   unsigned int ipb0;              /* IP breakpoint 0 */
    124   unsigned int ipb1;              /* IP breakpoint 1 */
    125   unsigned int dab0;              /* data address breakpoint 0 */
    126   unsigned int dab1;              /* data address breakpoint 1 */
    127                             /* Control Group 1 */
    128   unsigned int imap0;             /* interrupt map 0 */
    129   unsigned int imap1;             /* interrupt map 1 */
    130   unsigned int imap2;             /* interrupt map 2 */
    131   unsigned int icon;              /* interrupt control */
    132                             /* Control Group 2 */
    133   unsigned int mcon0;             /* memory region 0 configuration */
    134   unsigned int mcon1;             /* memory region 1 configuration */
    135   unsigned int mcon2;             /* memory region 2 configuration */
    136   unsigned int mcon3;             /* memory region 3 configuration */
    137                             /* Control Group 3 */
    138   unsigned int mcon4;             /* memory region 4 configuration */
    139   unsigned int mcon5;             /* memory region 5 configuration */
    140   unsigned int mcon6;             /* memory region 6 configuration */
    141   unsigned int mcon7;             /* memory region 7 configuration */
    142                             /* Control Group 4 */
    143   unsigned int mcon8;             /* memory region 8 configuration */
    144   unsigned int mcon9;             /* memory region 9 configuration */
    145   unsigned int mcon10;            /* memory region 10 configuration */
    146   unsigned int mcon11;            /* memory region 11 configuration */
    147                             /* Control Group 5 */
    148   unsigned int mcon12;            /* memory region 12 configuration */
    149   unsigned int mcon13;            /* memory region 13 configuration */
    150   unsigned int mcon14;            /* memory region 14 configuration */
    151   unsigned int mcon15;            /* memory region 15 configuration */
    152                             /* Control Group 6 */
    153   unsigned int reserved;          /* reserved */
    154   unsigned int bpcon;             /* breakpoint control */
    155   unsigned int tc;                /* trace control */
    156   unsigned int bcon;              /* bus configuration control */
    157 }   i960ca_control_table;
    158  
    159 /* Intel i960CA Processor Control Block */
    160  
    161 typedef struct {
    162   unsigned int    *fault_tbl;     /* fault table base address */
    163   i960ca_control_table
    164                   *control_tbl;   /* control table base address */
    165   unsigned int     initial_ac;    /* AC register initial value */
    166   unsigned int     fault_config;  /* fault configuration word */
    167   void           **intr_tbl;      /* interrupt table base address */
    168   void            *sys_proc_tbl;  /* system procedure table
    169                                      base address */
    170   unsigned int     reserved;      /* reserved */
    171   unsigned int    *intr_stack;    /* interrupt stack pointer */
    172   unsigned int     ins_cache_cfg; /* instruction cache
    173                                      configuration word */
    174   unsigned int     reg_cache_cfg; /* register cache configuration word */
    175 }   i960ca_PRCB;
    176 
    177 typedef i960ca_control_table i960_control_table;
    178 typedef i960ca_PRCB i960_PRCB;
    179 
    180 #elif defined(__RTEMS_I960HA__)
    181 
    182 /* i960HA control structures */
    183 
    184 /* Intel i960HA Control Table */
    185 
    186 typedef struct {
    187                             /* Control Group 0 */
    188   unsigned int ipb0;              /* IP breakpoint 0 */
    189   unsigned int ipb1;              /* IP breakpoint 1 */
    190   unsigned int dab0;              /* data address breakpoint 0 */
    191   unsigned int dab1;              /* data address breakpoint 1 */
    192                             /* Control Group 1 */
    193   unsigned int imap0;             /* interrupt map 0 */
    194   unsigned int imap1;             /* interrupt map 1 */
    195   unsigned int imap2;             /* interrupt map 2 */
    196   unsigned int icon;              /* interrupt control */
    197                             /* Control Group 2 */
    198   unsigned int mcon0;             /* memory region 0 configuration */
    199   unsigned int mcon1;             /* memory region 1 configuration */
    200   unsigned int mcon2;             /* memory region 2 configuration */
    201   unsigned int mcon3;             /* memory region 3 configuration */
    202                             /* Control Group 3 */
    203   unsigned int mcon4;             /* memory region 4 configuration */
    204   unsigned int mcon5;             /* memory region 5 configuration */
    205   unsigned int mcon6;             /* memory region 6 configuration */
    206   unsigned int mcon7;             /* memory region 7 configuration */
    207                             /* Control Group 4 */
    208   unsigned int mcon8;             /* memory region 8 configuration */
    209   unsigned int mcon9;             /* memory region 9 configuration */
    210   unsigned int mcon10;            /* memory region 10 configuration */
    211   unsigned int mcon11;            /* memory region 11 configuration */
    212                             /* Control Group 5 */
    213   unsigned int mcon12;            /* memory region 12 configuration */
    214   unsigned int mcon13;            /* memory region 13 configuration */
    215   unsigned int mcon14;            /* memory region 14 configuration */
    216   unsigned int mcon15;            /* memory region 15 configuration */
    217                             /* Control Group 6 */
    218   unsigned int reserved;          /* reserved */
    219   unsigned int bpcon;             /* breakpoint control */
    220   unsigned int tc;                /* trace control */
    221   unsigned int bcon;              /* bus configuration control */
    222 }   i960ha_control_table;
    223 
    224 /* Intel i960HA Processor Control Block */
    225 
    226 typedef struct {
    227   unsigned int    *fault_tbl;     /* fault table base address */
    228   i960ha_control_table
    229                   *control_tbl;   /* control table base address */
    230   unsigned int     initial_ac;    /* AC register initial value */
    231   unsigned int     fault_config;  /* fault configuration word */
    232   void           **intr_tbl;      /* interrupt table base address */
    233   void            *sys_proc_tbl;  /* system procedure table
    234                                      base address */
    235   unsigned int     reserved;      /* reserved */
    236   unsigned int    *intr_stack;    /* interrupt stack pointer */
    237   unsigned int     ins_cache_cfg; /* instruction cache
    238                                      configuration word */
    239   unsigned int     reg_cache_cfg; /* register cache configuration word */
    240 }   i960ha_PRCB;
    241 
    242 typedef i960ha_control_table i960_control_table;
    243 typedef i960ha_PRCB i960_PRCB;
    244 
    245 #elif defined(__RTEMS_I960RP__)
    246 
    247 /* i960RP control structures */
    248 
    249 /* Intel i960RP Control Table */
    250 
    251 typedef struct {
    252                             /* Control Group 0 */
    253   unsigned int rsvd00;
    254   unsigned int rsvd01;
    255   unsigned int rsvd02;
    256   unsigned int rsvd03;
    257                             /* Control Group 1 */
    258   unsigned int imap0;             /* interrupt map 0 */
    259   unsigned int imap1;             /* interrupt map 1 */
    260   unsigned int imap2;             /* interrupt map 2 */
    261   unsigned int icon;              /* interrupt control */
    262                             /* Control Group 2 */
    263   unsigned int pmcon0;            /* memory region 0 configuration */
    264   unsigned int rsvd1;
    265   unsigned int pmcon2;            /* memory region 2 configuration */
    266   unsigned int rsvd2;
    267                             /* Control Group 3 */
    268   unsigned int pmcon4;            /* memory region 4 configuration */
    269   unsigned int rsvd3;
    270   unsigned int pmcon6;            /* memory region 6 configuration */
    271   unsigned int rsvd4;
    272                             /* Control Group 4 */
    273   unsigned int pmcon8;            /* memory region 8 configuration */
    274   unsigned int rsvd5;
    275   unsigned int pmcon10;           /* memory region 10 configuration */
    276   unsigned int rsvd6;
    277                             /* Control Group 5 */
    278   unsigned int pmcon12;           /* memory region 12 configuration */
    279   unsigned int rsvd7;
    280   unsigned int pmcon14;           /* memory region 14 configuration */
    281   unsigned int rsvd8;
    282                             /* Control Group 6 */
    283   unsigned int rsvd9;
    284   unsigned int rsvd10;
    285   unsigned int tc;                /* trace control */
    286   unsigned int bcon;              /* bus configuration control */
    287 }   i960rp_control_table;
    288 
    289 /* Intel i960RP Processor Control Block */
    290 
    291 typedef struct {
    292   unsigned int    *fault_tbl;     /* fault table base address */
    293   i960rp_control_table
    294                   *control_tbl;   /* control table base address */
    295   unsigned int     initial_ac;    /* AC register initial value */
    296   unsigned int     fault_config;  /* fault configuration word */
    297   void           **intr_tbl;      /* interrupt table base address */
    298   void            *sys_proc_tbl;  /* system procedure table
    299                                      base address */
    300   unsigned int     reserved;      /* reserved */
    301   unsigned int    *intr_stack;    /* interrupt stack pointer */
    302   unsigned int     ins_cache_cfg; /* instruction cache
    303                                      configuration word */
    304   unsigned int     reg_cache_cfg; /* register cache configuration word */
    305 }   i960rp_PRCB;
    306 
    307 typedef i960rp_control_table i960_control_table;
    308 typedef i960rp_PRCB i960_PRCB;
    309 
    310 #elif defined(__i960KA__)
    311 
    312 /* i960KA control structures */
    313 
    314 /* Intel i960KA Control Table */
    315 
    316 typedef struct {
    317 int pad0;
    318 }   i960ka_control_table;
    319 
    320 /* Intel i960KA Processor Control Block */
    321 
    322 typedef struct {
    323   void           **intr_tbl;      /* interrupt table base address */
    324   unsigned int    *intr_stack;    /* interrupt stack pointer */
    325 }   i960ka_PRCB;
    326 
    327 typedef i960ka_control_table i960_control_table;
    328 typedef i960ka_PRCB i960_PRCB;
    329 
    330 #else
    331 #error "invalid processor selection!"
    332 #endif
    33381
    33482/*
     
    33684 */
    33785
    338 #if !defined(__i960KA__)
    33986#define i960_reload_ctl_group( group ) \
    34087 { register int _cmd = ((group)|0x400) ; \
    34188   asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \
    34289 }
    343 #endif
    34490
    34591#define i960_atomic_modify( mask, addr, prev ) \
     
    394140  } while ( 0 )
    395141
    396 #if !defined(__i960KA__)
    397142#define i960_cause_intr( intr ) \
    398143 { register int _intr = (intr); \
    399144   asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \
    400145 }
    401 #endif
    402146
    403147/*
    404148 *  Interrupt Masking Routines
    405149 */
    406 
    407 #if defined(__RTEMS_I960CA__) || defined(__RTEMS_I960HA__)
    408 
    409 #define i960_unmask_intr( xint ) \
    410  { register unsigned int _mask= (1<<(xint)); \
    411    asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \
    412  }
    413 
    414 #define i960_mask_intr( xint ) \
    415  { register unsigned int _mask= (1<<(xint)); \
    416    asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \
    417  }
    418 
    419 #define i960_clear_intr( xint ) \
    420  { register unsigned int _xint=(xint); \
    421 asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \
    422                   bbs    %0,sf0, loop_til_cleared" \
    423                   : "=d" (_xint) : "0" (_xint) ); \
    424  }
    425 
    426 static inline unsigned int i960_pend_intrs()
    427 { register unsigned int _intr=0;
    428   asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) );
    429   return ( _intr );
    430 }
    431 
    432 static inline unsigned int i960_mask_intrs()
    433 { register unsigned int _intr=0;
    434   asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );
    435   return( _intr );
    436 }
    437 
    438 #elif defined(__RTEMS_I960RP__)
    439 
    440 #define i960_unmask_intr( xint ) \
    441  { register unsigned int _mask= (1<<(xint)); \
    442    register unsigned int *_imsk = (int * ) IMSK_ADDR; \
    443    register unsigned int _val= *_imsk; \
    444    asm volatile( "or %0,%2,%0; \
    445                   st %0,(%1)" \
    446                     : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
    447                     : "0" (_val), "1" (_imsk), "2" (_mask) ); \
    448  }
    449 
    450 #define i960_mask_intr( xint ) \
    451  { register unsigned int _mask= (1<<(xint)); \
    452    register unsigned int *_imsk = (int * ) IMSK_ADDR; \
    453    register unsigned int _val = *_imsk; \
    454    asm volatile( "andnot %2,%0,%0; \
    455                   st %0,(%1)" \
    456                     : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
    457                     : "0" (_val), "1" (_imsk), "2" (_mask) ); \
    458  }
    459 #define i960_clear_intr( xint ) \
    460  { register unsigned int _xint=xint; \
    461    register unsigned int _mask=(1<<(xint)); \
    462    register unsigned int *_ipnd = (int * ) IPND_ADDR; \
    463    register unsigned int          _rslt = 0; \
    464 asm volatile( "loop_til_cleared: mov 0, %0; \
    465                   atmod %1, %2, %0; \
    466                   bbs    %3,%0, loop_til_cleared" \
    467                   : "=d" (_rslt), "=d" (_ipnd), "=d" (_mask), "=d" (_xint) \
    468                   : "0"  (_rslt), "1"  (_ipnd), "2"  (_mask), "3"  (_xint) ); \
    469  }
    470 
    471 static inline unsigned int i960_pend_intrs()
    472 { register unsigned int _intr= *(unsigned int *) IPND_ADDR;
    473   /*register unsigned int *_ipnd = (int * ) IPND_ADDR; \
    474    asm volatile( "mov (%0),%1" \
    475                     : "=d" (_ipnd), "=d" (_mask) \
    476                     : "0" (_ipnd), "1" (_mask) ); \ */
    477   return ( _intr );
    478 }
    479 
    480 static inline unsigned int i960_mask_intrs()
    481 { register unsigned int _intr= *(unsigned int *) IMSK_ADDR;
    482   /*asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );*/
    483   return( _intr );
    484 }
    485 #endif
    486150
    487151static inline unsigned int i960_get_fp()
     
    490154  return ( _fp );
    491155}
    492 
    493 /*
    494  *  Soft Reset
    495  */
    496 
    497 #if defined(I960_SOFT_RESET_COMMAND)
    498 #define i960_soft_reset( prcb ) \
    499  { register i960_PRCB    *_prcb = (prcb); \
    500    register unsigned int *_next=0; \
    501    register unsigned int  _cmd  = I960_SOFT_RESET_COMMAND; \
    502    asm volatile( "lda    next,%1; \
    503                   sysctl %0,%1,%2; \
    504             next: mov    g0,g0" \
    505                   : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
    506                   : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
    507  }
    508 
    509 #elif !defined(__i960KA__)
    510 #warning "I960_SOFT_RESET_COMMAND is not defined"
    511 #endif
    512156
    513157/*
  • make/custom/i960sim.cfg

    r9e52b29 rbc85fd5a  
    88
    99RTEMS_CPU=i960
    10 RTEMS_CPU_MODEL=i960gdbsim
     10RTEMS_CPU_MODEL=i960ka
    1111
    1212# This is the actual bsp directory used during the build process.
  • make/custom/rxgen960.cfg

    r9e52b29 rbc85fd5a  
    1616#  and (hopefully) optimize for it.
    1717#
    18 CPU_CFLAGS = -mrp -D__i960RP__ -D__i960_RP__
     18# CPU_CFLAGS = -mrp -D__i960RP__ -D__i960_RP__
     19CPU_CFLAGS = -mrp
    1920
    2021# -pipe does not work in our local configuration of FSF GCC 2.6.0
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