Changeset bc74b337 in rtems


Ignore:
Timestamp:
May 20, 2010, 2:52:32 PM (9 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.10, 4.11, master
Children:
23f35aa
Parents:
d2137a05
Message:

2010-05-20 Sebastian Huber <sebastian.huber@…>

  • configure.ac: Fixed BSP option.
  • include/lpc32xx.h, startup/bspstarthooks.c: Added PLL setup.
Location:
c/src/lib/libbsp/arm/lpc32xx
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/lpc32xx/ChangeLog

    rd2137a05 rbc74b337  
     12010-05-20      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * configure.ac: Fixed BSP option.
     4        * include/lpc32xx.h, startup/bspstarthooks.c: Added PLL setup.
     5
    162010-05-20      Sebastian Huber <sebastian.huber@embedded-brains.de>
    27
  • c/src/lib/libbsp/arm/lpc32xx/configure.ac

    rd2137a05 rbc74b337  
    6464RTEMS_BSPOPTS_HELP([LPC32XX_CONFIG_UART_CLKMODE],[clock mode configuration for UARTs])
    6565
    66 RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_MMU],[lpc32xx_boot],[1])
     66RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_MMU],[lpc32xx_mzx_boot_int],[1])
    6767RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_MMU],[*],[])
    6868RTEMS_BSPOPTS_HELP([LPC32XX_DISABLE_MMU],[disable MMU])
  • c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h

    rd2137a05 rbc74b337  
    2424
    2525#include <stdint.h>
     26
     27#include <bsp/utility.h>
    2628
    2729/**
     
    201203/** @} */
    202204
     205/**
     206 * @name Power Control Register (PWR_CTRL)
     207 *
     208 * @{
     209 */
     210
     211#define PWR_STOP BIT32(0)
     212#define PWR_HIGHCORE_ALWAYS BIT32(1)
     213#define PWR_NORMAL_RUN_MODE BIT32(2)
     214#define PWR_SYSCLKEN_ALWAYS BIT32(3)
     215#define PWR_SYSCLKEN_HIGH BIT32(4)
     216#define PWR_HIGHCORE_HIGH BIT32(5)
     217#define PWR_SDRAM_AUTO_REFRESH BIT32(7)
     218#define PWR_UPDATE_EMCSREFREQ BIT32(8)
     219#define PWR_EMCSREFREQ BIT32(9)
     220#define PWR_HCLK_USES_PERIPH_CLK BIT32(10)
     221
     222/** @} */
     223
     224/**
     225 * @name HCLK PLL Control Register (HCLKPLL_CTRL)
     226 *
     227 * @{
     228 */
     229
     230#define HCLK_PLL_LOCK BIT32(0)
     231#define HCLK_PLL_M(val) FIELD32(val, 1, 8)
     232#define HCLK_PLL_N(val) FIELD32(val, 9, 2)
     233#define HCLK_PLL_P(val) FIELD32(val, 11, 2)
     234#define HCLK_PLL_FBD_FCLKOUT BIT32(13)
     235#define HCLK_PLL_DIRECT BIT32(14)
     236#define HCLK_PLL_BYPASS BIT32(15)
     237#define HCLK_PLL_POWER BIT32(16)
     238
     239/** @} */
     240
     241/**
     242 * @name HCLK Divider Control Register (HCLKDIV_CTRL)
     243 *
     244 * @{
     245 */
     246
     247#define HCLK_DIV_HCLK(val) FIELD32(val, 0, 2)
     248#define HCLK_DIV_PERIPH_CLK(val) FIELD32(val, 2, 5)
     249#define HCLK_DIV_DDRAM_CLK(val) FIELD32(val, 7, 2)
     250
     251/** @} */
     252
    203253/** @} */
    204254
  • c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c

    rd2137a05 rbc74b337  
    183183}
    184184
     185#if LPC32XX_OSCILLATOR_MAIN != 13000000U
     186  #error "unexpected main oscillator frequency"
     187#endif
     188
     189static void BSP_START_SECTION lpc32xx_pll_setup(void)
     190{
     191  uint32_t pwr_ctrl = LPC32XX_PWR_CTRL;
     192
     193  if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) == 0) {
     194    /* Enable HCLK PLL */
     195    LPC32XX_HCLKPLL_CTRL = HCLK_PLL_POWER | HCLK_PLL_DIRECT | HCLK_PLL_M(16 - 1);
     196    while ((LPC32XX_HCLKPLL_CTRL & HCLK_PLL_LOCK) == 0) {
     197      /* Wait */
     198    }
     199
     200    /* Setup HCLK divider */
     201    LPC32XX_HCLKDIV_CTRL = HCLK_DIV_HCLK(2 - 1) | HCLK_DIV_PERIPH_CLK(16 - 1);
     202
     203    /* Enable HCLK PLL output */
     204    LPC32XX_PWR_CTRL = pwr_ctrl | PWR_NORMAL_RUN_MODE;
     205  }
     206}
     207
    185208void BSP_START_SECTION bsp_start_hook_0(void)
    186209{
     210  lpc32xx_pll_setup();
    187211  lpc32xx_mmu_and_cache_setup();
    188212}
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