Changeset bc5fc7a6 in rtems


Ignore:
Timestamp:
Oct 12, 2001, 5:40:22 PM (19 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
7d953c2
Parents:
f64f1816
Message:

2001-10-12 Alexandra Kossovsky <sasha@…>

  • cpu.c, rtems/score/cpu.h, rtems/score/sh.h: Modified to support SH4. Reviewed by Ralf Corsepius <corsepiu@…> who did the original SH port.
Files:
8 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/sh/ChangeLog

    rf64f1816 rbc5fc7a6  
     12001-10-12      Alexandra Kossovsky <sasha@oktet.ru>
     2
     3        * cpu.c, rtems/score/cpu.h, rtems/score/sh.h: Modified to
     4        support SH4.  Reviewed by Ralf Corsepius <corsepiu@faw.uni-ulm.de>
     5        who did the original SH port.
     6
    172001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    28
  • c/src/exec/score/cpu/sh/cpu.c

    rf64f1816 rbc5fc7a6  
    3030#include <rtems/score/sh.h>
    3131
     32/* FIXME: This should not be here */
     33#if defined(__SH4__)
     34#include <rtems/score/sh4_regs.h>
     35#endif
    3236
    3337/* referenced in start.S */
     
    7680
    7781  /* FP context initialization support goes here */
     82  /* FIXME: When not to use SH4_FPSCR_PR ? */
     83#ifdef __SH4__
     84  _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM | SH4_FPSCR_PR;
     85#endif
     86#ifdef __SH3E__
     87  /* FIXME: Wild guess :) */
     88  _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM;
     89#endif
    7890
    7991  _CPU_Table = *cpu_table;
     
    152164 */
    153165
     166#if defined(sh1) || defined(sh2)
    154167void _CPU_ISR_install_vector(
    155168  unsigned32  vector,
     
    231244{
    232245  _the_context->r15 = (unsigned32*) ((unsigned32) (_stack_base) + (_size) );
     246#if defined(__sh1__) || defined(__sh2__)
    233247  _the_context->sr  = (_isr << 4) & 0x00f0 ;
     248#else
     249  _the_context->sr  = SH4_SR_MD | ((_isr << 4) & 0x00f0);
     250#endif
    234251  _the_context->pr  = (unsigned32*) _entry_point ;
    235 }
     252
     253
     254#if 0 && SH_HAS_FPU
     255   /* Disable FPU if it is non-fp task */
     256  if(!_is_fp)
     257    _the_context->sr |= SH4_SR_FD;
     258#endif
     259}
     260
  • c/src/exec/score/cpu/sh/rtems/score/cpu.h

    rf64f1816 rbc5fc7a6  
    3434#ifndef ASM
    3535#include <rtems/score/shtypes.h>
     36#endif
     37#if 0 && defined(__SH4__)
     38#include <rtems/score/sh4_regs.h>
    3639#endif
    3740
     
    132135 */
    133136
    134 #define CPU_HARDWARE_FP     FALSE
    135 #define CPU_SOFTWARE_FP     FALSE
     137#if SH_HAS_FPU
     138/* FIXME: What about CPU_SOFTWARE_FP ? */
     139#define CPU_HARDWARE_FP TRUE
     140#else
     141#define CPU_SOFTWARE_FP FALSE
     142#define CPU_HARDWARE_FP FALSE
     143#endif
    136144
    137145/*
     
    151159 */
    152160
     161#if SH_HAS_FPU
     162#define CPU_ALL_TASKS_ARE_FP     TRUE
     163#else
    153164#define CPU_ALL_TASKS_ARE_FP     FALSE
     165#endif
    154166
    155167/*
     
    165177 */
    166178
     179#if SH_HAS_FPU
     180#define CPU_IDLE_TASK_IS_FP     TRUE
     181#else
    167182#define CPU_IDLE_TASK_IS_FP      FALSE
     183#endif
    168184
    169185/*
     
    193209 */
    194210
    195 #define CPU_USE_DEFERRED_FP_SWITCH       TRUE
     211#if SH_HAS_FPU
     212#define CPU_USE_DEFERRED_FP_SWITCH      FALSE
     213#else
     214/* FIXME: Is this needed?
     215 * Only here for backward compatibility with previous versions
     216 */
     217#define CPU_USE_DEFERRED_FP_SWITCH      TRUE
     218#endif
    196219
    197220/*
     
    356379
    357380typedef struct {
     381#if SH_HAS_FPU
     382#ifdef SH4_USE_X_REGISTERS
     383  union {
     384    float f[16];
     385    double d[8];
     386  } x;
     387#endif
     388  union {
     389    float f[16];
     390    double d[8];
     391  } r;
     392  float fpul;       /* fp communication register */
     393  unsigned32 fpscr; /* fp control register */
     394#endif /* SH_HAS_FPU */
    358395} Context_Control_fp;
    359396
     
    401438 */
    402439
    403 /*
     440#if SH_HAS_FPU
    404441SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
    405 */
     442#endif
    406443
    407444/*
     
    479516 *  alignment does not take into account the requirements for the stack.
    480517 */
    481 
     518#if defined(__SH4__)
     519/* FIXME: sh3 and SH3E? */
     520#define CPU_ALIGNMENT              8
     521#else
    482522#define CPU_ALIGNMENT              4
     523#endif
    483524
    484525/*
     
    655696 */
    656697
     698#if SH_HAS_FPU
     699#define _CPU_Context_Initialize_fp( _destination ) \
     700  do { \
     701     *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context;\
     702  } while(0)
     703#else
    657704#define _CPU_Context_Initialize_fp( _destination ) \
    658705  {  }
     706#endif
    659707
    660708/* end of Context handler macros */
     
    679727{ \
    680728  asm volatile("mov.l %0,r0"::"m" (_error)); \
     729  asm volatile("mov #1, r4"); \
    681730  asm volatile("trapa #34"); \
    682731}
  • c/src/exec/score/cpu/sh/rtems/score/sh.h

    rf64f1816 rbc5fc7a6  
    3939 *  dependent features are present in a particular member of the family.
    4040 */
    41  
    42 #if defined(rtems_multilib)
    4341
    4442/*
     
    4745 */
    4846
    49 #define CPU_MODEL_NAME  "rtems_multilib"
    50 #define SH_HAS_FPU      0
    51 #define SH_HAS_SEPARATE_STACKS 1
    52 
     47#if defined(__SH3E__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
     48
     49/*
     50 * Define this if you want to use XD-registers.
     51 * Then this registers will be saved/restored on context switch.
     52 * ! They will not be saved/restored on interrupts!
     53 */
     54#define SH4_USE_X_REGISTERS     0
     55
     56#if defined(__LITTLE_ENDIAN__)
     57#define SH_HAS_FPU 1
    5358#else
    54 
    55 #if defined(__sh1__) || defined(__sh2__) || defined(__sh3__)
    56 #define SH_HAS_FPU      0
     59/* FIXME: Context_Control_fp does not support big endian */
     60#warning FPU not supported
     61#define SH_HAS_FPU 0
     62#endif
     63
     64#elif defined(__sh1__) || defined(__sh2__) || defined(__sh3__)
     65#define SH_HAS_FPU 0
    5766#else
    58 #define SH_HAS_FPU      1
     67#warning Cannot detect FPU support, assuming no FPU
     68#define SH_HAS_FPU 0
    5969#endif
    6070
    6171/* this should not be here */
     72#ifndef CPU_MODEL_NAME
    6273#define CPU_MODEL_NAME  "SH-Multilib"
    63 
    64 #endif /* multilib */
     74#endif
    6575
    6676/*
     
    7989
    8090#ifndef ASM
     91
     92#if defined(__sh1__) || defined(__sh2__)
    8193
    8294/*
     
    111123    "nop\n\t" \
    112124    : : "r" (SH_IRQDIS_VALUE), "r" (_level) );
     125
     126#else
     127
     128#define SH_IRQDIS_MASK 0xf0
     129
     130#define sh_disable_interrupts( _level ) \
     131  asm volatile ( \
     132    "stc sr,%0\n\t" \
     133    "mov %0,r5\n\t" \
     134    "or %1,r5\n\t" \
     135    "ldc r5,sr\n\t"\
     136  : "=&r" (_level ) \
     137  : "r" (SH_IRQDIS_MASK) \
     138  : "r5" );
     139
     140#define sh_enable_interrupts( _level ) \
     141  asm volatile( "ldc %0,sr\n\t" \
     142    "nop\n\t" \
     143    :: "r" (_level) );
     144
     145/*
     146 *  This temporarily restores the interrupt to _level before immediately
     147 *  disabling them again.  This is used to divide long RTEMS critical
     148 *  sections into two or more parts.  The parameter _level is not
     149 *  modified.
     150 */
     151     
     152#define sh_flash_interrupts( _level ) \
     153  asm volatile( \
     154    "stc sr,r5\n\t" \
     155    "ldc %1,sr\n\t" \
     156    "nop\n\t" \
     157    "or %0,r5\n\t" \
     158    "ldc r5,sr\n\t" \
     159    "nop\n\t" \
     160    : : "r" (SH_IRQDIS_MASK), "r" (_level) : "r5");
     161
     162#endif
    113163
    114164#define sh_get_interrupt_level( _level ) \
  • cpukit/score/cpu/sh/ChangeLog

    rf64f1816 rbc5fc7a6  
     12001-10-12      Alexandra Kossovsky <sasha@oktet.ru>
     2
     3        * cpu.c, rtems/score/cpu.h, rtems/score/sh.h: Modified to
     4        support SH4.  Reviewed by Ralf Corsepius <corsepiu@faw.uni-ulm.de>
     5        who did the original SH port.
     6
    172001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    28
  • cpukit/score/cpu/sh/cpu.c

    rf64f1816 rbc5fc7a6  
    3030#include <rtems/score/sh.h>
    3131
     32/* FIXME: This should not be here */
     33#if defined(__SH4__)
     34#include <rtems/score/sh4_regs.h>
     35#endif
    3236
    3337/* referenced in start.S */
     
    7680
    7781  /* FP context initialization support goes here */
     82  /* FIXME: When not to use SH4_FPSCR_PR ? */
     83#ifdef __SH4__
     84  _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM | SH4_FPSCR_PR;
     85#endif
     86#ifdef __SH3E__
     87  /* FIXME: Wild guess :) */
     88  _CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM;
     89#endif
    7890
    7991  _CPU_Table = *cpu_table;
     
    152164 */
    153165
     166#if defined(sh1) || defined(sh2)
    154167void _CPU_ISR_install_vector(
    155168  unsigned32  vector,
     
    231244{
    232245  _the_context->r15 = (unsigned32*) ((unsigned32) (_stack_base) + (_size) );
     246#if defined(__sh1__) || defined(__sh2__)
    233247  _the_context->sr  = (_isr << 4) & 0x00f0 ;
     248#else
     249  _the_context->sr  = SH4_SR_MD | ((_isr << 4) & 0x00f0);
     250#endif
    234251  _the_context->pr  = (unsigned32*) _entry_point ;
    235 }
     252
     253
     254#if 0 && SH_HAS_FPU
     255   /* Disable FPU if it is non-fp task */
     256  if(!_is_fp)
     257    _the_context->sr |= SH4_SR_FD;
     258#endif
     259}
     260
  • cpukit/score/cpu/sh/rtems/score/cpu.h

    rf64f1816 rbc5fc7a6  
    3434#ifndef ASM
    3535#include <rtems/score/shtypes.h>
     36#endif
     37#if 0 && defined(__SH4__)
     38#include <rtems/score/sh4_regs.h>
    3639#endif
    3740
     
    132135 */
    133136
    134 #define CPU_HARDWARE_FP     FALSE
    135 #define CPU_SOFTWARE_FP     FALSE
     137#if SH_HAS_FPU
     138/* FIXME: What about CPU_SOFTWARE_FP ? */
     139#define CPU_HARDWARE_FP TRUE
     140#else
     141#define CPU_SOFTWARE_FP FALSE
     142#define CPU_HARDWARE_FP FALSE
     143#endif
    136144
    137145/*
     
    151159 */
    152160
     161#if SH_HAS_FPU
     162#define CPU_ALL_TASKS_ARE_FP     TRUE
     163#else
    153164#define CPU_ALL_TASKS_ARE_FP     FALSE
     165#endif
    154166
    155167/*
     
    165177 */
    166178
     179#if SH_HAS_FPU
     180#define CPU_IDLE_TASK_IS_FP     TRUE
     181#else
    167182#define CPU_IDLE_TASK_IS_FP      FALSE
     183#endif
    168184
    169185/*
     
    193209 */
    194210
    195 #define CPU_USE_DEFERRED_FP_SWITCH       TRUE
     211#if SH_HAS_FPU
     212#define CPU_USE_DEFERRED_FP_SWITCH      FALSE
     213#else
     214/* FIXME: Is this needed?
     215 * Only here for backward compatibility with previous versions
     216 */
     217#define CPU_USE_DEFERRED_FP_SWITCH      TRUE
     218#endif
    196219
    197220/*
     
    356379
    357380typedef struct {
     381#if SH_HAS_FPU
     382#ifdef SH4_USE_X_REGISTERS
     383  union {
     384    float f[16];
     385    double d[8];
     386  } x;
     387#endif
     388  union {
     389    float f[16];
     390    double d[8];
     391  } r;
     392  float fpul;       /* fp communication register */
     393  unsigned32 fpscr; /* fp control register */
     394#endif /* SH_HAS_FPU */
    358395} Context_Control_fp;
    359396
     
    401438 */
    402439
    403 /*
     440#if SH_HAS_FPU
    404441SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
    405 */
     442#endif
    406443
    407444/*
     
    479516 *  alignment does not take into account the requirements for the stack.
    480517 */
    481 
     518#if defined(__SH4__)
     519/* FIXME: sh3 and SH3E? */
     520#define CPU_ALIGNMENT              8
     521#else
    482522#define CPU_ALIGNMENT              4
     523#endif
    483524
    484525/*
     
    655696 */
    656697
     698#if SH_HAS_FPU
     699#define _CPU_Context_Initialize_fp( _destination ) \
     700  do { \
     701     *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context;\
     702  } while(0)
     703#else
    657704#define _CPU_Context_Initialize_fp( _destination ) \
    658705  {  }
     706#endif
    659707
    660708/* end of Context handler macros */
     
    679727{ \
    680728  asm volatile("mov.l %0,r0"::"m" (_error)); \
     729  asm volatile("mov #1, r4"); \
    681730  asm volatile("trapa #34"); \
    682731}
  • cpukit/score/cpu/sh/rtems/score/sh.h

    rf64f1816 rbc5fc7a6  
    3939 *  dependent features are present in a particular member of the family.
    4040 */
    41  
    42 #if defined(rtems_multilib)
    4341
    4442/*
     
    4745 */
    4846
    49 #define CPU_MODEL_NAME  "rtems_multilib"
    50 #define SH_HAS_FPU      0
    51 #define SH_HAS_SEPARATE_STACKS 1
    52 
     47#if defined(__SH3E__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
     48
     49/*
     50 * Define this if you want to use XD-registers.
     51 * Then this registers will be saved/restored on context switch.
     52 * ! They will not be saved/restored on interrupts!
     53 */
     54#define SH4_USE_X_REGISTERS     0
     55
     56#if defined(__LITTLE_ENDIAN__)
     57#define SH_HAS_FPU 1
    5358#else
    54 
    55 #if defined(__sh1__) || defined(__sh2__) || defined(__sh3__)
    56 #define SH_HAS_FPU      0
     59/* FIXME: Context_Control_fp does not support big endian */
     60#warning FPU not supported
     61#define SH_HAS_FPU 0
     62#endif
     63
     64#elif defined(__sh1__) || defined(__sh2__) || defined(__sh3__)
     65#define SH_HAS_FPU 0
    5766#else
    58 #define SH_HAS_FPU      1
     67#warning Cannot detect FPU support, assuming no FPU
     68#define SH_HAS_FPU 0
    5969#endif
    6070
    6171/* this should not be here */
     72#ifndef CPU_MODEL_NAME
    6273#define CPU_MODEL_NAME  "SH-Multilib"
    63 
    64 #endif /* multilib */
     74#endif
    6575
    6676/*
     
    7989
    8090#ifndef ASM
     91
     92#if defined(__sh1__) || defined(__sh2__)
    8193
    8294/*
     
    111123    "nop\n\t" \
    112124    : : "r" (SH_IRQDIS_VALUE), "r" (_level) );
     125
     126#else
     127
     128#define SH_IRQDIS_MASK 0xf0
     129
     130#define sh_disable_interrupts( _level ) \
     131  asm volatile ( \
     132    "stc sr,%0\n\t" \
     133    "mov %0,r5\n\t" \
     134    "or %1,r5\n\t" \
     135    "ldc r5,sr\n\t"\
     136  : "=&r" (_level ) \
     137  : "r" (SH_IRQDIS_MASK) \
     138  : "r5" );
     139
     140#define sh_enable_interrupts( _level ) \
     141  asm volatile( "ldc %0,sr\n\t" \
     142    "nop\n\t" \
     143    :: "r" (_level) );
     144
     145/*
     146 *  This temporarily restores the interrupt to _level before immediately
     147 *  disabling them again.  This is used to divide long RTEMS critical
     148 *  sections into two or more parts.  The parameter _level is not
     149 *  modified.
     150 */
     151     
     152#define sh_flash_interrupts( _level ) \
     153  asm volatile( \
     154    "stc sr,r5\n\t" \
     155    "ldc %1,sr\n\t" \
     156    "nop\n\t" \
     157    "or %0,r5\n\t" \
     158    "ldc r5,sr\n\t" \
     159    "nop\n\t" \
     160    : : "r" (SH_IRQDIS_MASK), "r" (_level) : "r5");
     161
     162#endif
    113163
    114164#define sh_get_interrupt_level( _level ) \
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