Ignore:
Timestamp:
Jan 24, 2017, 10:16:41 AM (4 years ago)
Author:
Martin Aberg <maberg@…>
Branches:
5, master
Children:
7b8a920
Parents:
ad203e58
git-author:
Martin Aberg <maberg@…> (01/24/17 10:16:41)
git-committer:
Daniel Hellstrom <daniel@…> (05/14/17 10:31:57)
Message:

leon, grcan: consistent indentation

This commit does not contain any change of functionality.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/shared/include/grcan.h

    rad203e58 rbc40b4d  
    2424
    2525struct grcan_regs {
    26     volatile unsigned int conf;          /* 0x00 */
    27     volatile unsigned int stat;          /* 0x04 */
    28     volatile unsigned int ctrl;          /* 0x08 */
    29     volatile unsigned int dummy0[3];     /* 0x0C-0x014 */
    30     volatile unsigned int smask;         /* 0x18 */
    31     volatile unsigned int scode;         /* 0x1C */
    32 
    33     volatile unsigned int dummy1[56];    /* 0x20-0xFC */
    34 
    35     volatile unsigned int pimsr;         /* 0x100 */
    36     volatile unsigned int pimr;          /* 0x104 */
    37     volatile unsigned int pisr;          /* 0x108 */
    38     volatile unsigned int pir;           /* 0x10C */
    39     volatile unsigned int imr;           /* 0x110 */
    40     volatile unsigned int picr;          /* 0x114 */
    41 
    42     volatile unsigned int dummy2[58];    /* 0x118-0x1FC */
    43 
    44     volatile unsigned int tx0ctrl;       /* 0x200 */
    45     volatile unsigned int tx0addr;       /* 0x204 */
    46     volatile unsigned int tx0size;       /* 0x208 */
    47     volatile unsigned int tx0wr;         /* 0x20C */
    48     volatile unsigned int tx0rd;         /* 0x210 */
    49     volatile unsigned int tx0irq;        /* 0x214 */
    50 
    51     volatile unsigned int dummy3[58];    /* 0x218-0x2FC */
    52 
    53     volatile unsigned int rx0ctrl;       /* 0x300 */
    54     volatile unsigned int rx0addr;       /* 0x304 */
    55     volatile unsigned int rx0size;       /* 0x308 */
    56     volatile unsigned int rx0wr;         /* 0x30C */
    57     volatile unsigned int rx0rd;         /* 0x310 */
    58     volatile unsigned int rx0irq;        /* 0x314 */
    59     volatile unsigned int rx0mask;       /* 0x318 */
    60     volatile unsigned int rx0code;       /* 0x31C */
     26        volatile unsigned int conf;          /* 0x00 */
     27        volatile unsigned int stat;          /* 0x04 */
     28        volatile unsigned int ctrl;          /* 0x08 */
     29        volatile unsigned int dummy0[3];     /* 0x0C-0x014 */
     30        volatile unsigned int smask;         /* 0x18 */
     31        volatile unsigned int scode;         /* 0x1C */
     32
     33        volatile unsigned int dummy1[56];    /* 0x20-0xFC */
     34
     35        volatile unsigned int pimsr;         /* 0x100 */
     36        volatile unsigned int pimr;          /* 0x104 */
     37        volatile unsigned int pisr;          /* 0x108 */
     38        volatile unsigned int pir;           /* 0x10C */
     39        volatile unsigned int imr;           /* 0x110 */
     40        volatile unsigned int picr;          /* 0x114 */
     41
     42        volatile unsigned int dummy2[58];    /* 0x118-0x1FC */
     43
     44        volatile unsigned int tx0ctrl;       /* 0x200 */
     45        volatile unsigned int tx0addr;       /* 0x204 */
     46        volatile unsigned int tx0size;       /* 0x208 */
     47        volatile unsigned int tx0wr;         /* 0x20C */
     48        volatile unsigned int tx0rd;         /* 0x210 */
     49        volatile unsigned int tx0irq;        /* 0x214 */
     50
     51        volatile unsigned int dummy3[58];    /* 0x218-0x2FC */
     52
     53        volatile unsigned int rx0ctrl;       /* 0x300 */
     54        volatile unsigned int rx0addr;       /* 0x304 */
     55        volatile unsigned int rx0size;       /* 0x308 */
     56        volatile unsigned int rx0wr;         /* 0x30C */
     57        volatile unsigned int rx0rd;         /* 0x310 */
     58        volatile unsigned int rx0irq;        /* 0x314 */
     59        volatile unsigned int rx0mask;       /* 0x318 */
     60        volatile unsigned int rx0code;       /* 0x31C */
    6161};
    6262
     
    6666        unsigned int rxsync_cnt;
    6767        unsigned int txsync_cnt;
    68   unsigned int txloss_cnt;
    69   unsigned int ahberr_cnt;
    70   unsigned int ints;
     68        unsigned int txloss_cnt;
     69        unsigned int ahberr_cnt;
     70        unsigned int ints;
    7171};
    7272
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