Ignore:
Timestamp:
Jan 24, 2017, 10:16:41 AM (4 years ago)
Author:
Martin Aberg <maberg@…>
Branches:
5, master
Children:
7b8a920
Parents:
ad203e58
git-author:
Martin Aberg <maberg@…> (01/24/17 10:16:41)
git-committer:
Daniel Hellstrom <daniel@…> (05/14/17 10:31:57)
Message:

leon, grcan: consistent indentation

This commit does not contain any change of functionality.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/shared/can/grcan.c

    rad203e58 rbc40b4d  
    143143
    144144static unsigned int grcan_hw_read_try(
    145   struct grcan_priv *pDev,
    146   struct grcan_regs *regs,
    147   CANMsg *buffer,
    148   int max);
     145        struct grcan_priv *pDev,
     146        struct grcan_regs *regs,
     147        CANMsg *buffer,
     148        int max);
    149149
    150150static unsigned int grcan_hw_write_try(
    151   struct grcan_priv *pDev,
    152   struct grcan_regs *regs,
    153   CANMsg *buffer,
    154   int count);
     151        struct grcan_priv *pDev,
     152        struct grcan_regs *regs,
     153        CANMsg *buffer,
     154        int count);
    155155
    156156static void grcan_hw_config(
    157   struct grcan_regs *regs,
    158   struct grcan_config *conf);
     157        struct grcan_regs *regs,
     158        struct grcan_config *conf);
    159159
    160160static void grcan_hw_accept(
    161   struct grcan_regs *regs,
    162   struct grcan_filter *afilter);
     161        struct grcan_regs *regs,
     162        struct grcan_filter *afilter);
    163163
    164164static void grcan_hw_sync(
    165   struct grcan_regs *regs,
    166   struct grcan_filter *sfilter);
     165        struct grcan_regs *regs,
     166        struct grcan_filter *sfilter);
    167167
    168168static void grcan_interrupt(void *arg);
     
    379379static rtems_device_driver grcan_hw_start(struct grcan_priv *pDev)
    380380{
    381   /*
    382   * tmp is set but never used. GCC gives a warning for this
    383   * and we need to tell GCC not to complain.
    384   */
    385   unsigned int tmp RTEMS_UNUSED;
    386 
    387   IRQ_GLOBAL_PREPARE(oldLevel);
    388 
    389   FUNCDBG();
    390 
    391   /* Check that memory has been allocated successfully */
    392   if ( !pDev->tx || !pDev->rx )
    393     return RTEMS_NO_MEMORY;
    394 
    395   /* Configure FIFO configuration register
    396   * and Setup timing
    397   */
    398   if ( pDev->config_changed ){
    399     grcan_hw_config(pDev->regs,&pDev->config);
    400     pDev->config_changed = 0;
    401   }
    402 
    403   /* Setup receiver */
    404   pDev->regs->rx0addr = (unsigned int)pDev->_rx_hw;
    405   pDev->regs->rx0size = pDev->rxbuf_size;
    406 
    407   /* Setup Transmitter */
    408   pDev->regs->tx0addr = (unsigned int)pDev->_tx_hw;
    409   pDev->regs->tx0size = pDev->txbuf_size;
    410 
    411   /* Setup acceptance filters */
    412   grcan_hw_accept(pDev->regs,&pDev->afilter);
    413 
    414   /* Sync filters */
    415   grcan_hw_sync(pDev->regs,&pDev->sfilter);
    416 
    417   /* Clear status bits */
    418   tmp = READ_REG(&pDev->regs->stat);
    419   pDev->regs->stat = 0;
    420 
    421   /* Setup IRQ handling */
    422 
    423   /* Clear all IRQs */
    424   tmp = READ_REG(&pDev->regs->pir);
    425   pDev->regs->picr = 0x1ffff;
    426 
    427   /* unmask TxLoss|TxErrCntr|RxErrCntr|TxAHBErr|RxAHBErr|OR|OFF|PASS */
    428   pDev->regs->imr = 0x1601f;
    429 
    430   /* Enable routing of the IRQs */
    431   IRQ_GLOBAL_DISABLE(oldLevel);
    432   IRQ_UNMASK(pDev->irq+GRCAN_IRQ_TXSYNC);
    433   IRQ_UNMASK(pDev->irq+GRCAN_IRQ_RXSYNC);
    434   IRQ_UNMASK(pDev->irq+GRCAN_IRQ_IRQ);
    435   IRQ_GLOBAL_ENABLE(oldLevel);
    436 
    437   /* Reset some software data */
    438   /*pDev->txerror = 0;
    439   pDev->rxerror = 0;*/
    440 
    441   /* Enable receiver/transmitter */
    442   pDev->regs->rx0ctrl = GRCAN_RXCTRL_ENABLE;
    443   pDev->regs->tx0ctrl = GRCAN_TXCTRL_ENABLE;
    444 
    445   /* Enable HurriCANe core */
    446   pDev->regs->ctrl = GRCAN_CTRL_ENABLE;
    447 
    448   /* Leave transmitter disabled, it is enabled when
    449   * trying to send something.
    450   */
    451   return RTEMS_SUCCESSFUL;
     381        /*
     382        * tmp is set but never used. GCC gives a warning for this
     383        * and we need to tell GCC not to complain.
     384        */
     385        unsigned int tmp RTEMS_UNUSED;
     386
     387        IRQ_GLOBAL_PREPARE(oldLevel);
     388
     389        FUNCDBG();
     390
     391        /* Check that memory has been allocated successfully */
     392        if (!pDev->tx || !pDev->rx)
     393                return RTEMS_NO_MEMORY;
     394
     395        /* Configure FIFO configuration register
     396        * and Setup timing
     397        */
     398        if (pDev->config_changed) {
     399                grcan_hw_config(pDev->regs, &pDev->config);
     400                pDev->config_changed = 0;
     401        }
     402
     403        /* Setup receiver */
     404        pDev->regs->rx0addr = (unsigned int)pDev->_rx_hw;
     405        pDev->regs->rx0size = pDev->rxbuf_size;
     406
     407        /* Setup Transmitter */
     408        pDev->regs->tx0addr = (unsigned int)pDev->_tx_hw;
     409        pDev->regs->tx0size = pDev->txbuf_size;
     410
     411        /* Setup acceptance filters */
     412        grcan_hw_accept(pDev->regs, &pDev->afilter);
     413
     414        /* Sync filters */
     415        grcan_hw_sync(pDev->regs, &pDev->sfilter);
     416
     417        /* Clear status bits */
     418        tmp = READ_REG(&pDev->regs->stat);
     419        pDev->regs->stat = 0;
     420
     421        /* Setup IRQ handling */
     422
     423        /* Clear all IRQs */
     424        tmp = READ_REG(&pDev->regs->pir);
     425        pDev->regs->picr = 0x1ffff;
     426
     427        /* unmask TxLoss|TxErrCntr|RxErrCntr|TxAHBErr|RxAHBErr|OR|OFF|PASS */
     428        pDev->regs->imr = 0x1601f;
     429
     430        /* Enable routing of the IRQs */
     431        IRQ_GLOBAL_DISABLE(oldLevel);
     432        IRQ_UNMASK(pDev->irq + GRCAN_IRQ_TXSYNC);
     433        IRQ_UNMASK(pDev->irq + GRCAN_IRQ_RXSYNC);
     434        IRQ_UNMASK(pDev->irq + GRCAN_IRQ_IRQ);
     435        IRQ_GLOBAL_ENABLE(oldLevel);
     436
     437        /* Reset some software data */
     438        /*pDev->txerror = 0;
     439           pDev->rxerror = 0; */
     440
     441        /* Enable receiver/transmitter */
     442        pDev->regs->rx0ctrl = GRCAN_RXCTRL_ENABLE;
     443        pDev->regs->tx0ctrl = GRCAN_TXCTRL_ENABLE;
     444
     445        /* Enable HurriCANe core */
     446        pDev->regs->ctrl = GRCAN_CTRL_ENABLE;
     447
     448        /* Leave transmitter disabled, it is enabled when
     449        * trying to send something.
     450        */
     451        return RTEMS_SUCCESSFUL;
    452452}
    453453
    454454static void grcan_hw_stop(struct grcan_priv *pDev)
    455455{
    456   FUNCDBG();
    457 
    458   /* Mask all IRQs */
    459   pDev->regs->imr = 0;
    460   IRQ_MASK(pDev->irq+GRCAN_IRQ_TXSYNC);
    461   IRQ_MASK(pDev->irq+GRCAN_IRQ_RXSYNC);
    462   IRQ_MASK(pDev->irq+GRCAN_IRQ_IRQ);
    463 
    464   /* Disable receiver & transmitter */
    465   pDev->regs->rx0ctrl = 0;
    466   pDev->regs->tx0ctrl = 0;
    467 
    468   /* Reset semaphores to the initial state and wakeing
    469    * all threads waiting for an IRQ. The threads that
    470    * get woken up must check for RTEMS_UNSATISFIED in
    471    * order to determine that they should return to
    472    * user space with error status.
    473    */
    474   rtems_semaphore_flush(pDev->rx_sem);
    475   rtems_semaphore_flush(pDev->tx_sem);
    476   rtems_semaphore_flush(pDev->txempty_sem);
    477 }
    478 
    479 static void grcan_hw_config(
    480   struct grcan_regs *regs,
    481   struct grcan_config *conf
    482   )
    483 {
    484   unsigned int config=0;
    485 
    486   /* Reset HurriCANe Core */
    487   regs->ctrl = 0;
    488 
    489   if ( conf->silent )
    490     config |= GRCAN_CFG_SILENT;
    491 
    492   if ( conf->abort )
    493     config |= GRCAN_CFG_ABORT;
    494 
    495   if ( conf->selection.selection )
    496     config |= GRCAN_CFG_SELECTION;
    497 
    498   if ( conf->selection.enable0 )
    499     config |= GRCAN_CFG_ENABLE0;
    500 
    501   if ( conf->selection.enable1 )
    502     config |= GRCAN_CFG_ENABLE1;
    503 
    504   /* Timing */
    505   config |= (conf->timing.bpr<<GRCAN_CFG_BPR_BIT) & GRCAN_CFG_BPR;
    506   config |= (conf->timing.rsj<<GRCAN_CFG_RSJ_BIT) & GRCAN_CFG_RSJ;
    507   config |= (conf->timing.ps1<<GRCAN_CFG_PS1_BIT) & GRCAN_CFG_PS1;
    508   config |= (conf->timing.ps2<<GRCAN_CFG_PS2_BIT) & GRCAN_CFG_PS2;
    509   config |= (conf->timing.scaler<<GRCAN_CFG_SCALER_BIT) & GRCAN_CFG_SCALER;
    510 
    511   /* Write configuration */
    512   regs->conf = config;
    513 
    514   /* Enable HurriCANe Core */
    515   regs->ctrl = GRCAN_CTRL_ENABLE;
     456        FUNCDBG();
     457
     458        /* Mask all IRQs */
     459        pDev->regs->imr = 0;
     460        IRQ_MASK(pDev->irq + GRCAN_IRQ_TXSYNC);
     461        IRQ_MASK(pDev->irq + GRCAN_IRQ_RXSYNC);
     462        IRQ_MASK(pDev->irq + GRCAN_IRQ_IRQ);
     463
     464        /* Disable receiver & transmitter */
     465        pDev->regs->rx0ctrl = 0;
     466        pDev->regs->tx0ctrl = 0;
     467
     468        /* Reset semaphores to the initial state and wakeing
     469         * all threads waiting for an IRQ. The threads that
     470         * get woken up must check for RTEMS_UNSATISFIED in
     471         * order to determine that they should return to
     472         * user space with error status.
     473         */
     474        rtems_semaphore_flush(pDev->rx_sem);
     475        rtems_semaphore_flush(pDev->tx_sem);
     476        rtems_semaphore_flush(pDev->txempty_sem);
     477}
     478
     479static void grcan_hw_config(struct grcan_regs *regs, struct grcan_config *conf)
     480{
     481        unsigned int config = 0;
     482
     483        /* Reset HurriCANe Core */
     484        regs->ctrl = 0;
     485
     486        if (conf->silent)
     487                config |= GRCAN_CFG_SILENT;
     488
     489        if (conf->abort)
     490                config |= GRCAN_CFG_ABORT;
     491
     492        if (conf->selection.selection)
     493                config |= GRCAN_CFG_SELECTION;
     494
     495        if (conf->selection.enable0)
     496                config |= GRCAN_CFG_ENABLE0;
     497
     498        if (conf->selection.enable1)
     499                config |= GRCAN_CFG_ENABLE1;
     500
     501        /* Timing */
     502        config |= (conf->timing.bpr << GRCAN_CFG_BPR_BIT) & GRCAN_CFG_BPR;
     503        config |= (conf->timing.rsj << GRCAN_CFG_RSJ_BIT) & GRCAN_CFG_RSJ;
     504        config |= (conf->timing.ps1 << GRCAN_CFG_PS1_BIT) & GRCAN_CFG_PS1;
     505        config |= (conf->timing.ps2 << GRCAN_CFG_PS2_BIT) & GRCAN_CFG_PS2;
     506        config |=
     507            (conf->timing.scaler << GRCAN_CFG_SCALER_BIT) & GRCAN_CFG_SCALER;
     508
     509        /* Write configuration */
     510        regs->conf = config;
     511
     512        /* Enable HurriCANe Core */
     513        regs->ctrl = GRCAN_CTRL_ENABLE;
    516514}
    517515
    518516static void grcan_hw_accept(
    519   struct grcan_regs *regs,
    520   struct grcan_filter *afilter
    521   )
    522 {
    523   /* Disable Sync mask totaly (if we change scode or smask
    524    * in an unfortunate way we may trigger a sync match)
    525    */
    526   regs->rx0mask = 0xffffffff;
    527 
    528   /* Set Sync Filter in a controlled way */
    529   regs->rx0code = afilter->code;
    530   regs->rx0mask = afilter->mask;
    531 }
    532 
    533 static void grcan_hw_sync(
    534   struct grcan_regs *regs,
    535   struct grcan_filter *sfilter
    536   )
    537 {
    538   /* Disable Sync mask totaly (if we change scode or smask
    539    * in an unfortunate way we may trigger a sync match)
    540    */
    541   regs->smask = 0xffffffff;
    542 
    543   /* Set Sync Filter in a controlled way */
    544   regs->scode = sfilter->code;
    545   regs->smask = sfilter->mask;
     517        struct grcan_regs *regs,
     518        struct grcan_filter *afilter
     519)
     520{
     521        /* Disable Sync mask totaly (if we change scode or smask
     522         * in an unfortunate way we may trigger a sync match)
     523         */
     524        regs->rx0mask = 0xffffffff;
     525
     526        /* Set Sync Filter in a controlled way */
     527        regs->rx0code = afilter->code;
     528        regs->rx0mask = afilter->mask;
     529}
     530
     531static void grcan_hw_sync(struct grcan_regs *regs, struct grcan_filter *sfilter)
     532{
     533        /* Disable Sync mask totaly (if we change scode or smask
     534         * in an unfortunate way we may trigger a sync match)
     535         */
     536        regs->smask = 0xffffffff;
     537
     538        /* Set Sync Filter in a controlled way */
     539        regs->scode = sfilter->code;
     540        regs->smask = sfilter->mask;
    546541}
    547542
    548543static unsigned int grcan_hw_rxavail(
    549   unsigned int rp,
    550   unsigned int wp,
    551   unsigned int size
    552   )
    553 {
    554   if ( rp == wp ) {
    555     /* read pointer and write pointer is equal only
    556      * when RX buffer is empty.
    557      */
    558     return 0;
    559   }
    560 
    561   if ( wp > rp ) {
    562     return (wp-rp)/GRCAN_MSG_SIZE;
    563   }else{
    564     return (size-(rp-wp))/GRCAN_MSG_SIZE;
    565   }
     544        unsigned int rp,
     545        unsigned int wp, unsigned int size
     546)
     547{
     548        if (rp == wp) {
     549                /* read pointer and write pointer is equal only
     550                 * when RX buffer is empty.
     551                 */
     552                return 0;
     553        }
     554
     555        if (wp > rp) {
     556                return (wp - rp) / GRCAN_MSG_SIZE;
     557        } else {
     558                return (size - (rp - wp)) / GRCAN_MSG_SIZE;
     559        }
    566560}
    567561
    568562static unsigned int grcan_hw_txspace(
    569   unsigned int rp,
    570   unsigned int wp,
    571   unsigned int size
    572   )
    573 {
    574   unsigned int left;
    575 
    576   if ( rp == wp ) {
    577     /* read pointer and write pointer is equal only
    578     * when TX buffer is empty.
    579     */
    580     return size/GRCAN_MSG_SIZE-WRAP_AROUND_TX_MSGS;
    581   }
    582 
    583   /* size - 4 - abs(read-write) */
    584   if ( wp > rp ) {
    585     left = size-(wp-rp);
    586   }else{
    587     left = rp-wp;
    588   }
    589 
    590   return left/GRCAN_MSG_SIZE-WRAP_AROUND_TX_MSGS;
     563        unsigned int rp,
     564        unsigned int wp,
     565        unsigned int size
     566)
     567{
     568        unsigned int left;
     569
     570        if (rp == wp) {
     571                /* read pointer and write pointer is equal only
     572                * when TX buffer is empty.
     573                */
     574                return size / GRCAN_MSG_SIZE - WRAP_AROUND_TX_MSGS;
     575        }
     576
     577        /* size - 4 - abs(read-write) */
     578        if (wp > rp) {
     579                left = size - (wp - rp);
     580        } else {
     581                left = rp - wp;
     582        }
     583
     584        return left / GRCAN_MSG_SIZE - WRAP_AROUND_TX_MSGS;
    591585}
    592586
    593587static int grcan_hw_rx_ongoing(struct grcan_regs *regs)
    594588{
    595   return READ_REG(&regs->rx0ctrl) & GRCAN_RXCTRL_ONGOING;
    596 };
     589        return READ_REG(&regs->rx0ctrl) & GRCAN_RXCTRL_ONGOING;
     590}
    597591
    598592static int grcan_hw_tx_ongoing(struct grcan_regs *regs)
    599593{
    600   return READ_REG(&regs->tx0ctrl) & GRCAN_TXCTRL_ONGOING;
    601 };
     594        return READ_REG(&regs->tx0ctrl) & GRCAN_TXCTRL_ONGOING;
     595}
    602596
    603597
     
    608602
    609603static int grcan_calc_timing(
    610   unsigned int baud,          /* The requested BAUD to calculate timing for */
    611   unsigned int core_hz,       /* Frequency in Hz of GRCAN Core */
    612   unsigned int sampl_pt,
    613   struct grcan_timing *timing /* result is placed here */
    614   )
     604        unsigned int baud,      /* The requested BAUD to calculate timing for */
     605        unsigned int core_hz,   /* Frequency in Hz of GRCAN Core */
     606        unsigned int sampl_pt,
     607        struct grcan_timing *timing     /* result is placed here */
     608)
    615609{
    616610        int best_error = 1000000000;
    617611        int error;
    618         int best_tseg=0, best_brp=0, brp=0;
    619         int tseg=0, tseg1=0, tseg2=0;
     612        int best_tseg = 0, best_brp = 0, brp = 0;
     613        int tseg = 0, tseg1 = 0, tseg2 = 0;
    620614        int sjw = 1;
    621615
    622   /* Default to 90% */
    623   if ( (sampl_pt < 50) || (sampl_pt>99) ){
    624     sampl_pt = GRCAN_SAMPLING_POINT;
    625   }
    626 
    627         if ( (baud<5000) || (baud>1000000) ){
     616        /* Default to 90% */
     617        if ((sampl_pt < 50) || (sampl_pt > 99)) {
     618                sampl_pt = GRCAN_SAMPLING_POINT;
     619        }
     620
     621        if ((baud < 5000) || (baud > 1000000)) {
    628622                /* invalid speed mode */
    629623                return -1;
     
    632626        /* find best match, return -2 if no good reg
    633627         * combination is available for this frequency
    634   */
     628        */
    635629
    636630        /* some heuristic specials */
     
    642636
    643637        /* tseg even = round down, odd = round up */
    644         for (tseg = (MIN_TSEG1 + MIN_TSEG2 + 2) * 2;
    645              tseg <= (MAX_TSEG2 + MAX_TSEG1 + 2) * 2 + 1;
    646              tseg++)
    647         {
     638        for (
     639                tseg = (MIN_TSEG1 + MIN_TSEG2 + 2) * 2;
     640                tseg <= (MAX_TSEG2 + MAX_TSEG1 + 2) * 2 + 1;
     641                tseg++
     642        ) {
    648643                brp = core_hz / ((1 + tseg / 2) * baud) + tseg % 2;
    649                 if ((brp <= 0) ||
    650         ( (brp > 256*1) && (brp <= 256*2) && (brp&0x1) ) ||
    651         ( (brp > 256*2) && (brp <= 256*4) && (brp&0x3) ) ||
    652         ( (brp > 256*4) && (brp <= 256*8) && (brp&0x7) ) ||
    653         (brp > 256*8)
    654         )
     644                if (
     645                        (brp <= 0) ||
     646                        ((brp > 256 * 1) && (brp <= 256 * 2) && (brp & 0x1)) ||
     647                        ((brp > 256 * 2) && (brp <= 256 * 4) && (brp & 0x3)) ||
     648                        ((brp > 256 * 4) && (brp <= 256 * 8) && (brp & 0x7)) ||
     649                        (brp > 256 * 8)
     650                )
    655651                        continue;
    656652
    657653                error = baud - core_hz / (brp * (1 + tseg / 2));
    658                 if (error < 0)
    659                 {
     654                if (error < 0) {
    660655                        error = -error;
    661656                }
    662657
    663                 if (error <= best_error)
    664                 {
     658                if (error <= best_error) {
    665659                        best_error = error;
    666                         best_tseg = tseg/2;
    667                         best_brp = brp-1;
     660                        best_tseg = tseg / 2;
     661                        best_brp = brp - 1;
    668662                }
    669663        }
    670664
    671         if (best_error && (baud / best_error < 10))
    672         {
     665        if (best_error && (baud / best_error < 10)) {
    673666                return -2;
    674         }else if ( !timing )
    675                 return 0; /* nothing to store result in, but a valid bitrate can be calculated */
     667        } else if (!timing)
     668                return 0;       /* nothing to store result in, but a valid bitrate can be calculated */
    676669
    677670        tseg2 = best_tseg - (sampl_pt * (best_tseg + 1)) / 100;
    678671
    679         if (tseg2 < MIN_TSEG2)
    680         {
     672        if (tseg2 < MIN_TSEG2) {
    681673                tseg2 = MIN_TSEG2;
    682674        }
    683675
    684         if (tseg2 > MAX_TSEG2)
    685         {
     676        if (tseg2 > MAX_TSEG2) {
    686677                tseg2 = MAX_TSEG2;
    687678        }
     
    689680        tseg1 = best_tseg - tseg2 - 2;
    690681
    691         if (tseg1 > MAX_TSEG1)
    692         {
     682        if (tseg1 > MAX_TSEG1) {
    693683                tseg1 = MAX_TSEG1;
    694684                tseg2 = best_tseg - tseg1 - 2;
    695685        }
    696686
    697   /* Get scaler and BRP from pseudo BRP */
    698   if ( best_brp <= 256 ){
    699     timing->scaler = best_brp;
    700     timing->bpr = 0;
    701   }else if ( best_brp <= 256*2 ){
    702     timing->scaler = ((best_brp+1)>>1) -1;
    703     timing->bpr = 1;
    704   }else if ( best_brp <= 256*4 ){
    705     timing->scaler = ((best_brp+1)>>2) -1;
    706     timing->bpr = 2;
    707   }else{
    708     timing->scaler = ((best_brp+1)>>3) -1;
    709     timing->bpr = 3;
    710   }
    711 
    712         timing->ps1    = tseg1+1;
    713         timing->ps2    = tseg2;
    714         timing->rsj    = sjw;
     687        /* Get scaler and BRP from pseudo BRP */
     688        if (best_brp <= 256) {
     689                timing->scaler = best_brp;
     690                timing->bpr = 0;
     691        } else if (best_brp <= 256 * 2) {
     692                timing->scaler = ((best_brp + 1) >> 1) - 1;
     693                timing->bpr = 1;
     694        } else if (best_brp <= 256 * 4) {
     695                timing->scaler = ((best_brp + 1) >> 2) - 1;
     696                timing->bpr = 2;
     697        } else {
     698                timing->scaler = ((best_brp + 1) >> 3) - 1;
     699                timing->bpr = 3;
     700        }
     701
     702        timing->ps1 = tseg1 + 1;
     703        timing->ps2 = tseg2;
     704        timing->rsj = sjw;
    715705
    716706        return 0;
     
    718708
    719709static unsigned int grcan_hw_read_try(
    720   struct grcan_priv *pDev,
    721   struct grcan_regs *regs,
    722   CANMsg *buffer,
    723   int max
    724   )
    725 {
    726   int i,j;
    727   CANMsg *dest;
    728   struct grcan_msg *source,tmp;
    729   unsigned int wp,rp,size,rxmax,addr,trunk_msg_cnt;
    730 
    731   FUNCDBG();
    732 
    733   wp = READ_REG(&regs->rx0wr);
    734   rp = READ_REG(&regs->rx0rd);
    735 
    736   /*
    737    * Due to hardware wrap around simplification write pointer will
    738    * never reach the read pointer, at least a gap of 8 bytes.
    739    * The only time they are equal is when the read pointer has
    740    * reached the write pointer (empty buffer)
    741    *
    742    */
    743   if ( wp != rp ){
    744     /* Not empty, we have received chars...
    745      * Read as much as possible from DMA buffer
    746      */
    747     size = READ_REG(&regs->rx0size);
    748 
    749     /* Get number of bytes available in RX buffer */
    750     trunk_msg_cnt = grcan_hw_rxavail(rp,wp,size);
    751 
    752     /* truncate size if user space buffer hasn't room for
    753      * all received chars.
    754      */
    755     if ( trunk_msg_cnt > max )
    756       trunk_msg_cnt = max;
    757 
    758     /* Read until i is 0 */
    759     i=trunk_msg_cnt;
    760 
    761     addr = (unsigned int)pDev->rx;
    762     source = (struct grcan_msg *)(addr + rp);
    763     dest = buffer;
    764     rxmax = addr + (size-GRCAN_MSG_SIZE);
    765 
    766     /* Read as many can messages as possible */
    767     while(i>0){
    768       /* Read CAN message from DMA buffer */
    769       tmp.head[0] = READ_DMA_WORD(&source->head[0]);
    770       tmp.head[1] = READ_DMA_WORD(&source->head[1]);
    771       /* Convert one grcan CAN message to one "software" CAN message */
    772       dest->extended = tmp.head[0]>>31;
    773       dest->rtr = (tmp.head[0] >>30) & 0x1;
    774       if ( dest->extended ){
    775         dest->id = tmp.head[0] & 0x3fffffff;
    776       }else{
    777         dest->id = (tmp.head[0] >>18) & 0xfff;
    778       }
    779       dest->len = tmp.head[1] >> 28;
    780       for(j=0; j<dest->len; j++)
    781         dest->data[j] = READ_DMA_BYTE(&source->data[j]);
    782 
    783       /* wrap around if neccessary */
    784       source = ( (unsigned int)source >= rxmax ) ? (struct grcan_msg *)addr : source+1;
    785       dest++; /* straight user buffer */
    786       i--;
    787     }
    788     /* Increment Hardware READ pointer (mark read byte as read)
    789      * ! wait for registers to be safely re-configurable
    790      */
    791     regs->rx0ctrl = 0; /* DISABLE RX CHANNEL */
    792     i=0;
    793     while( grcan_hw_rx_ongoing(regs) && (i<1000) ){
    794       i++;
    795     }
    796     regs->rx0rd = (unsigned int)source-addr;
    797     regs->rx0ctrl = GRCAN_RXCTRL_ENABLE; /* ENABLE_RX_CHANNEL */
    798     return trunk_msg_cnt;
    799   }
    800   return 0;
     710        struct grcan_priv *pDev,
     711        struct grcan_regs *regs,
     712        CANMsg * buffer,
     713        int max
     714)
     715{
     716        int i, j;
     717        CANMsg *dest;
     718        struct grcan_msg *source, tmp;
     719        unsigned int wp, rp, size, rxmax, addr, trunk_msg_cnt;
     720
     721        FUNCDBG();
     722
     723        wp = READ_REG(&regs->rx0wr);
     724        rp = READ_REG(&regs->rx0rd);
     725
     726        /*
     727         * Due to hardware wrap around simplification write pointer will
     728         * never reach the read pointer, at least a gap of 8 bytes.
     729         * The only time they are equal is when the read pointer has
     730         * reached the write pointer (empty buffer)
     731         *
     732         */
     733        if (wp != rp) {
     734                /* Not empty, we have received chars...
     735                 * Read as much as possible from DMA buffer
     736                 */
     737                size = READ_REG(&regs->rx0size);
     738
     739                /* Get number of bytes available in RX buffer */
     740                trunk_msg_cnt = grcan_hw_rxavail(rp, wp, size);
     741
     742                /* truncate size if user space buffer hasn't room for
     743                 * all received chars.
     744                 */
     745                if (trunk_msg_cnt > max)
     746                        trunk_msg_cnt = max;
     747
     748                /* Read until i is 0 */
     749                i = trunk_msg_cnt;
     750
     751                addr = (unsigned int)pDev->rx;
     752                source = (struct grcan_msg *)(addr + rp);
     753                dest = buffer;
     754                rxmax = addr + (size - GRCAN_MSG_SIZE);
     755
     756                /* Read as many can messages as possible */
     757                while (i > 0) {
     758                        /* Read CAN message from DMA buffer */
     759                        tmp.head[0] = READ_DMA_WORD(&source->head[0]);
     760                        tmp.head[1] = READ_DMA_WORD(&source->head[1]);
     761                        /* Convert one grcan CAN message to one "software" CAN message */
     762                        dest->extended = tmp.head[0] >> 31;
     763                        dest->rtr = (tmp.head[0] >> 30) & 0x1;
     764                        if (dest->extended) {
     765                                dest->id = tmp.head[0] & 0x3fffffff;
     766                        } else {
     767                                dest->id = (tmp.head[0] >> 18) & 0xfff;
     768                        }
     769                        dest->len = tmp.head[1] >> 28;
     770                        for (j = 0; j < dest->len; j++)
     771                                dest->data[j] = READ_DMA_BYTE(&source->data[j]);
     772
     773                        /* wrap around if neccessary */
     774                        source =
     775                            ((unsigned int)source >= rxmax) ?
     776                            (struct grcan_msg *)addr : source + 1;
     777                        dest++; /* straight user buffer */
     778                        i--;
     779                }
     780                /* Increment Hardware READ pointer (mark read byte as read)
     781                 * ! wait for registers to be safely re-configurable
     782                 */
     783                regs->rx0ctrl = 0;      /* DISABLE RX CHANNEL */
     784                i = 0;
     785                while (grcan_hw_rx_ongoing(regs) && (i < 1000)) {
     786                        i++;
     787                }
     788                regs->rx0rd = (unsigned int)source - addr;
     789                regs->rx0ctrl = GRCAN_RXCTRL_ENABLE;    /* ENABLE_RX_CHANNEL */
     790                return trunk_msg_cnt;
     791        }
     792        return 0;
    801793}
    802794
    803795static unsigned int grcan_hw_write_try(
    804   struct grcan_priv *pDev,
    805   struct grcan_regs *regs,
    806   CANMsg *buffer,
    807   int count
    808   )
    809 {
    810   unsigned int rp, wp, size, txmax, addr, ret;
    811   struct grcan_msg *dest;
    812   CANMsg *source;
    813   int space_left;
    814   unsigned int tmp;
    815   int i;
    816 
    817   DBGC(DBG_TX,"\n");
    818   /*FUNCDBG();*/
    819 
    820   rp = READ_REG(&regs->tx0rd);
    821   wp = READ_REG(&regs->tx0wr);
    822   size = READ_REG(&regs->tx0size);
    823 
    824   space_left = grcan_hw_txspace(rp,wp,size);
    825 
    826   /* is circular fifo full? */
    827   if ( space_left < 1 )
    828     return 0;
    829 
    830   /* Truncate size */
    831   if ( space_left > count )
    832     space_left = count;
    833   ret = space_left;
    834 
    835   addr = (unsigned int)pDev->tx;
    836 
    837   dest = (struct grcan_msg *)(addr + wp);
    838   source = (CANMsg *)buffer;
    839   txmax = addr + (size-GRCAN_MSG_SIZE);
    840 
    841   while ( space_left>0 ) {
    842     /* Convert and write CAN message to DMA buffer */
    843     if ( source->extended ){
    844       tmp = (1<<31) | (source->id & 0x3fffffff);
    845     }else{
    846       tmp = (source->id&0xfff)<<18;
    847     }
    848     if ( source->rtr )
    849       tmp|=(1<<30);
    850     dest->head[0] = tmp;
    851     dest->head[1] = source->len<<28;
    852     for ( i=0; i<source->len; i++)
    853       dest->data[i] = source->data[i];
    854     source++; /* straight user buffer */
    855     dest = ((unsigned int)dest >= txmax) ? (struct grcan_msg *)addr : dest+1;
    856     space_left--;
    857   }
    858 
    859   /* Update write pointer
    860    * ! wait for registers to be safely re-configurable
    861    */
    862   regs->tx0ctrl = 0; /* DISABLE TX CHANNEL */
    863   i=0;
    864   while( (grcan_hw_tx_ongoing(regs)) && i<1000 ){
    865     i++;
    866   }
    867   regs->tx0wr = (unsigned int)dest - addr; /* Update write pointer */
    868   regs->tx0ctrl = GRCAN_TXCTRL_ENABLE; /* ENABLE_TX_CHANNEL */
    869   return ret;
    870 }
    871 
    872 static int grcan_wait_rxdata(
    873   struct grcan_priv *pDev,
    874   int min
    875   )
    876 {
    877   unsigned int wp, rp, size, irq;
    878   unsigned int irq_trunk, dataavail;
    879   int wait;
    880   IRQ_GLOBAL_PREPARE(oldLevel);
    881 
    882   FUNCDBG();
    883 
    884   /*** block until receive IRQ received
    885    * Set up a valid IRQ point so that an IRQ is received
    886    * when one or more messages are received
    887    */
    888   IRQ_GLOBAL_DISABLE(oldLevel);
    889 
    890   size = READ_REG(&pDev->regs->rx0size);
    891   rp = READ_REG(&pDev->regs->rx0rd);
    892   wp = READ_REG(&pDev->regs->rx0wr);
    893 
    894   /**** Calculate IRQ Pointer ****/
    895   irq = wp + min*GRCAN_MSG_SIZE;
    896   /* wrap irq around */
    897   if ( irq >= size ){
    898     irq_trunk = irq-size;
    899   }else
    900     irq_trunk = irq;
    901 
    902   /* init IRQ HW */
    903   pDev->regs->rx0irq = irq_trunk;
    904 
    905   /* Clear pending Rx IRQ */
    906   pDev->regs->picr = GRCAN_RXIRQ_IRQ;
    907 
    908   wp = READ_REG(&pDev->regs->rx0wr);
    909 
    910   /* Calculate messages available */
    911   dataavail = grcan_hw_rxavail(rp,wp,size);
    912 
    913   if ( dataavail < min ){
    914     /* Still empty, proceed with sleep - Turn on IRQ (unmask irq) */
    915     pDev->regs->imr = READ_REG(&pDev->regs->imr) | GRCAN_RXIRQ_IRQ;
    916     wait=1;
    917   }else{
    918     /* enough message has been received, abort sleep - don't unmask interrupt */
    919     wait=0;
    920   }
    921   IRQ_GLOBAL_ENABLE(oldLevel);
    922 
    923     /* Wait for IRQ to fire only if has been triggered */
    924   if ( wait ){
    925     if ( rtems_semaphore_obtain(pDev->rx_sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT) == RTEMS_UNSATISFIED )
    926       return -1; /* Device driver has been closed or stopped, return with error status */
    927   }
    928 
    929   return 0;
     796        struct grcan_priv *pDev,
     797        struct grcan_regs *regs,
     798        CANMsg * buffer,
     799        int count
     800)
     801{
     802        unsigned int rp, wp, size, txmax, addr, ret;
     803        struct grcan_msg *dest;
     804        CANMsg *source;
     805        int space_left;
     806        unsigned int tmp;
     807        int i;
     808
     809        DBGC(DBG_TX, "\n");
     810        /*FUNCDBG(); */
     811
     812        rp = READ_REG(&regs->tx0rd);
     813        wp = READ_REG(&regs->tx0wr);
     814        size = READ_REG(&regs->tx0size);
     815
     816        space_left = grcan_hw_txspace(rp, wp, size);
     817
     818        /* is circular fifo full? */
     819        if (space_left < 1)
     820                return 0;
     821
     822        /* Truncate size */
     823        if (space_left > count)
     824                space_left = count;
     825        ret = space_left;
     826
     827        addr = (unsigned int)pDev->tx;
     828
     829        dest = (struct grcan_msg *)(addr + wp);
     830        source = (CANMsg *) buffer;
     831        txmax = addr + (size - GRCAN_MSG_SIZE);
     832
     833        while (space_left > 0) {
     834                /* Convert and write CAN message to DMA buffer */
     835                if (source->extended) {
     836                        tmp = (1 << 31) | (source->id & 0x3fffffff);
     837                } else {
     838                        tmp = (source->id & 0xfff) << 18;
     839                }
     840                if (source->rtr)
     841                        tmp |= (1 << 30);
     842                dest->head[0] = tmp;
     843                dest->head[1] = source->len << 28;
     844                for (i = 0; i < source->len; i++)
     845                        dest->data[i] = source->data[i];
     846                source++;       /* straight user buffer */
     847                dest =
     848                    ((unsigned int)dest >= txmax) ?
     849                    (struct grcan_msg *)addr : dest + 1;
     850                space_left--;
     851        }
     852
     853        /* Update write pointer
     854         * ! wait for registers to be safely re-configurable
     855         */
     856        regs->tx0ctrl = 0;      /* DISABLE TX CHANNEL */
     857        i = 0;
     858        while ((grcan_hw_tx_ongoing(regs)) && i < 1000) {
     859                i++;
     860        }
     861        regs->tx0wr = (unsigned int)dest - addr;        /* Update write pointer */
     862        regs->tx0ctrl = GRCAN_TXCTRL_ENABLE;    /* ENABLE_TX_CHANNEL */
     863        return ret;
     864}
     865
     866static int grcan_wait_rxdata(struct grcan_priv *pDev, int min)
     867{
     868        unsigned int wp, rp, size, irq;
     869        unsigned int irq_trunk, dataavail;
     870        int wait;
     871        IRQ_GLOBAL_PREPARE(oldLevel);
     872
     873        FUNCDBG();
     874
     875        /*** block until receive IRQ received
     876         * Set up a valid IRQ point so that an IRQ is received
     877         * when one or more messages are received
     878         */
     879        IRQ_GLOBAL_DISABLE(oldLevel);
     880
     881        size = READ_REG(&pDev->regs->rx0size);
     882        rp = READ_REG(&pDev->regs->rx0rd);
     883        wp = READ_REG(&pDev->regs->rx0wr);
     884
     885        /**** Calculate IRQ Pointer ****/
     886        irq = wp + min * GRCAN_MSG_SIZE;
     887        /* wrap irq around */
     888        if (irq >= size) {
     889                irq_trunk = irq - size;
     890        } else
     891                irq_trunk = irq;
     892
     893        /* init IRQ HW */
     894        pDev->regs->rx0irq = irq_trunk;
     895
     896        /* Clear pending Rx IRQ */
     897        pDev->regs->picr = GRCAN_RXIRQ_IRQ;
     898
     899        wp = READ_REG(&pDev->regs->rx0wr);
     900
     901        /* Calculate messages available */
     902        dataavail = grcan_hw_rxavail(rp, wp, size);
     903
     904        if (dataavail < min) {
     905                /* Still empty, proceed with sleep - Turn on IRQ (unmask irq) */
     906                pDev->regs->imr = READ_REG(&pDev->regs->imr) | GRCAN_RXIRQ_IRQ;
     907                wait = 1;
     908        } else {
     909                /* enough message has been received, abort sleep - don't unmask interrupt */
     910                wait = 0;
     911        }
     912        IRQ_GLOBAL_ENABLE(oldLevel);
     913
     914        /* Wait for IRQ to fire only if has been triggered */
     915        if (wait) {
     916                if (
     917                        rtems_semaphore_obtain(
     918                                pDev->rx_sem,
     919                                RTEMS_WAIT,
     920                                RTEMS_NO_TIMEOUT
     921                        ) == RTEMS_UNSATISFIED
     922                )
     923                        return -1;      /* Device driver has been closed or stopped, return with error status */
     924        }
     925
     926        return 0;
    930927}
    931928
     
    937934 *
    938935 */
    939 static int grcan_wait_txspace(
    940   struct grcan_priv *pDev,
    941   int min
    942   )
    943 {
    944   int wait;
    945   unsigned int irq, rp, wp, size, space_left;
    946   unsigned int irq_trunk;
    947   IRQ_GLOBAL_PREPARE(oldLevel);
    948 
    949   DBGC(DBG_TX,"\n");
    950   /*FUNCDBG();*/
    951 
    952   IRQ_GLOBAL_DISABLE(oldLevel);
    953 
    954   pDev->regs->tx0ctrl = GRCAN_TXCTRL_ENABLE;
    955 
    956   size = READ_REG(&pDev->regs->tx0size);
    957   wp = READ_REG(&pDev->regs->tx0wr);
    958 
    959   rp = READ_REG(&pDev->regs->tx0rd);
    960 
    961   /**** Calculate IRQ Pointer ****/
    962   irq = rp + min*GRCAN_MSG_SIZE;
    963   /* wrap irq around */
    964   if ( irq >= size ){
    965     irq_trunk = irq - size;
    966   }else
    967     irq_trunk = irq;
    968 
    969   /* trigger HW to do a IRQ when enough room in buffer */
    970   pDev->regs->tx0irq = irq_trunk;
    971 
    972   /* Clear pending Tx IRQ */
    973   pDev->regs->picr = GRCAN_TXIRQ_IRQ;
    974 
    975   /* One problem, if HW already gone past IRQ place the IRQ will
    976    * never be received resulting in a thread hang. We check if so
    977    * before proceeding.
    978    *
    979    * has the HW already gone past the IRQ generation place?
    980    *  == does min fit info tx buffer?
    981    */
    982   rp = READ_REG(&pDev->regs->tx0rd);
    983 
    984   space_left = grcan_hw_txspace(rp,wp,size);
    985 
    986   if ( space_left < min ){
    987     /* Still too full, proceed with sleep - Turn on IRQ (unmask irq) */
    988     pDev->regs->imr = READ_REG(&pDev->regs->imr) | GRCAN_TXIRQ_IRQ;
    989     wait=1;
    990   }else{
    991     /* There are enough room in buffer, abort wait - don't unmask interrupt */
    992     wait=0;
    993   }
    994   IRQ_GLOBAL_ENABLE(oldLevel);
    995 
    996   /* Wait for IRQ to fire only if it has been triggered */
    997   if ( wait ){
    998     if ( rtems_semaphore_obtain(pDev->tx_sem, RTEMS_WAIT, 100) ==
    999          RTEMS_UNSATISFIED ){
    1000       /* Device driver has flushed us, this may be due to another thread has
    1001        * closed the device, this is to avoid deadlock */
    1002       return -1;
    1003     }
    1004   }
    1005 
    1006   /* At this point the TxIRQ has been masked, we ned not to mask it */
    1007   return 0;
     936static int grcan_wait_txspace(struct grcan_priv *pDev, int min)
     937{
     938        int wait;
     939        unsigned int irq, rp, wp, size, space_left;
     940        unsigned int irq_trunk;
     941        IRQ_GLOBAL_PREPARE(oldLevel);
     942
     943        DBGC(DBG_TX, "\n");
     944        /*FUNCDBG(); */
     945
     946        IRQ_GLOBAL_DISABLE(oldLevel);
     947
     948        pDev->regs->tx0ctrl = GRCAN_TXCTRL_ENABLE;
     949
     950        size = READ_REG(&pDev->regs->tx0size);
     951        wp = READ_REG(&pDev->regs->tx0wr);
     952
     953        rp = READ_REG(&pDev->regs->tx0rd);
     954
     955        /**** Calculate IRQ Pointer ****/
     956        irq = rp + min * GRCAN_MSG_SIZE;
     957        /* wrap irq around */
     958        if (irq >= size) {
     959                irq_trunk = irq - size;
     960        } else
     961                irq_trunk = irq;
     962
     963        /* trigger HW to do a IRQ when enough room in buffer */
     964        pDev->regs->tx0irq = irq_trunk;
     965
     966        /* Clear pending Tx IRQ */
     967        pDev->regs->picr = GRCAN_TXIRQ_IRQ;
     968
     969        /* One problem, if HW already gone past IRQ place the IRQ will
     970         * never be received resulting in a thread hang. We check if so
     971         * before proceeding.
     972         *
     973         * has the HW already gone past the IRQ generation place?
     974         *  == does min fit info tx buffer?
     975         */
     976        rp = READ_REG(&pDev->regs->tx0rd);
     977
     978        space_left = grcan_hw_txspace(rp, wp, size);
     979
     980        if (space_left < min) {
     981                /* Still too full, proceed with sleep - Turn on IRQ (unmask irq) */
     982                pDev->regs->imr = READ_REG(&pDev->regs->imr) | GRCAN_TXIRQ_IRQ;
     983                wait = 1;
     984        } else {
     985                /* There are enough room in buffer, abort wait - don't unmask interrupt */
     986                wait = 0;
     987        }
     988        IRQ_GLOBAL_ENABLE(oldLevel);
     989
     990        /* Wait for IRQ to fire only if it has been triggered */
     991        if (wait) {
     992                if (rtems_semaphore_obtain(pDev->tx_sem, RTEMS_WAIT, 100) ==
     993                    RTEMS_UNSATISFIED) {
     994                        /* Device driver has flushed us, this may be due to another thread has
     995                         * closed the device, this is to avoid deadlock */
     996                        return -1;
     997                }
     998        }
     999
     1000        /* At this point the TxIRQ has been masked, we ned not to mask it */
     1001        return 0;
    10081002}
    10091003
    10101004static int grcan_tx_flush(struct grcan_priv *pDev)
    10111005{
    1012   int wait;
    1013   unsigned int rp, wp;
    1014   IRQ_GLOBAL_PREPARE(oldLevel);
    1015   FUNCDBG();
    1016 
    1017   /* loop until all data in circular buffer has been read by hw.
    1018    * (write pointer != read pointer )
    1019    *
    1020    * Hardware doesn't update write pointer - we do
    1021    */
    1022   while ( (wp=READ_REG(&pDev->regs->tx0wr)) != (rp=READ_REG(&pDev->regs->tx0rd)) ) {
    1023     /* Wait for TX empty IRQ */
    1024     IRQ_GLOBAL_DISABLE(oldLevel);
    1025     /* Clear pending TXEmpty IRQ */
    1026     pDev->regs->picr = GRCAN_TXEMPTY_IRQ;
    1027 
    1028     if ( wp != READ_REG(&pDev->regs->tx0rd) ) {
    1029       /* Still not empty, proceed with sleep - Turn on IRQ (unmask irq) */
    1030       pDev->regs->imr = READ_REG(&pDev->regs->imr) | GRCAN_TXEMPTY_IRQ;
    1031       wait = 1;
    1032     }else{
    1033       /* TX fifo is empty */
    1034       wait = 0;
    1035     }
    1036     IRQ_GLOBAL_ENABLE(oldLevel);
    1037     if ( !wait )
    1038       break;
    1039 
    1040     /* Wait for IRQ to wake us */
    1041     if ( rtems_semaphore_obtain(pDev->txempty_sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT) ==
    1042          RTEMS_UNSATISFIED ) {
    1043       return -1;
    1044     }
    1045   }
    1046   return 0;
     1006        int wait;
     1007        unsigned int rp, wp;
     1008        IRQ_GLOBAL_PREPARE(oldLevel);
     1009        FUNCDBG();
     1010
     1011        /* loop until all data in circular buffer has been read by hw.
     1012         * (write pointer != read pointer )
     1013         *
     1014         * Hardware doesn't update write pointer - we do
     1015         */
     1016        while (
     1017                (wp = READ_REG(&pDev->regs->tx0wr)) !=
     1018                (rp = READ_REG(&pDev->regs->tx0rd))
     1019        ) {
     1020                /* Wait for TX empty IRQ */
     1021                IRQ_GLOBAL_DISABLE(oldLevel);
     1022                /* Clear pending TXEmpty IRQ */
     1023                pDev->regs->picr = GRCAN_TXEMPTY_IRQ;
     1024
     1025                if (wp != READ_REG(&pDev->regs->tx0rd)) {
     1026                        /* Still not empty, proceed with sleep - Turn on IRQ (unmask irq) */
     1027                        pDev->regs->imr =
     1028                            READ_REG(&pDev->regs->imr) | GRCAN_TXEMPTY_IRQ;
     1029                        wait = 1;
     1030                } else {
     1031                        /* TX fifo is empty */
     1032                        wait = 0;
     1033                }
     1034                IRQ_GLOBAL_ENABLE(oldLevel);
     1035                if (!wait)
     1036                        break;
     1037
     1038                /* Wait for IRQ to wake us */
     1039                if (rtems_semaphore_obtain
     1040                    (pDev->txempty_sem, RTEMS_WAIT,
     1041                     RTEMS_NO_TIMEOUT) == RTEMS_UNSATISFIED) {
     1042                        return -1;
     1043                }
     1044        }
     1045        return 0;
    10471046}
    10481047
     
    11441143static void grcan_free_buffers(struct grcan_priv *pDev, int rx, int tx)
    11451144{
    1146   FUNCDBG();
    1147 
    1148   if ( tx && pDev->_tx ){
    1149     free(pDev->_tx);
    1150     pDev->_tx = NULL;
    1151     pDev->tx = NULL;
    1152   }
    1153 
    1154   if ( rx && pDev->_rx ){
    1155     free(pDev->_rx);
    1156     pDev->_rx = NULL;
    1157     pDev->rx = NULL;
    1158   }
     1145        FUNCDBG();
     1146
     1147        if (tx && pDev->_tx) {
     1148                free(pDev->_tx);
     1149                pDev->_tx = NULL;
     1150                pDev->tx = NULL;
     1151        }
     1152
     1153        if (rx && pDev->_rx) {
     1154                free(pDev->_rx);
     1155                pDev->_rx = NULL;
     1156                pDev->rx = NULL;
     1157        }
    11591158}
    11601159
     
    13071306        }
    13081307
    1309         while(count == 0 || (pDev->rxcomplete && (count!=req_cnt)) ){
    1310 
    1311         if ( !pDev->rxcomplete ){
    1312                 left = 1; /* return as soon as there is one message available */
    1313         }else{
    1314                 left = req_cnt - count;     /* return as soon as all data are available */
    1315 
    1316                 /* never wait for more than the half the maximum size of the receive buffer
    1317                  * Why? We need some time to copy buffer before to catch up with hw,
    1318                  * otherwise we would have to copy everything when the data has been
    1319                  * received.
    1320                  */
    1321                 if ( left > ((pDev->rxbuf_size/GRCAN_MSG_SIZE)/2) ){
    1322                         left = (pDev->rxbuf_size/GRCAN_MSG_SIZE)/2;
     1308        while (count == 0 || (pDev->rxcomplete && (count!=req_cnt))) {
     1309                if (!pDev->rxcomplete) {
     1310                        left = 1; /* return as soon as there is one message available */
     1311                } else {
     1312                        left = req_cnt - count;     /* return as soon as all data are available */
     1313
     1314                        /* never wait for more than the half the maximum size of the receive buffer
     1315                         * Why? We need some time to copy buffer before to catch up with hw,
     1316                         * otherwise we would have to copy everything when the data has been
     1317                         * received.
     1318                         */
     1319                        if (left > ((pDev->rxbuf_size/GRCAN_MSG_SIZE) / 2)){
     1320                                left = (pDev->rxbuf_size/GRCAN_MSG_SIZE) / 2;
     1321                        }
    13231322                }
    1324         }
    1325 
    1326         if ( grcan_wait_rxdata(pDev,left) ) {
    1327                 /* The wait has been aborted, probably due to
    1328                  * the device driver has been closed by another
    1329                  * thread.
    1330                  */
    1331                 return count;
    1332         }
    1333 
    1334         /* Try read bytes from circular buffer */
    1335         count += grcan_hw_read_try(
    1336                         pDev,
    1337                         pDev->regs,
    1338                         dest+count,
    1339                         req_cnt-count);
     1323
     1324                if (grcan_wait_rxdata(pDev, left)) {
     1325                        /* The wait has been aborted, probably due to
     1326                         * the device driver has been closed by another
     1327                         * thread.
     1328                         */
     1329                        return count;
     1330                }
     1331
     1332                /* Try read bytes from circular buffer */
     1333                count += grcan_hw_read_try(
     1334                                pDev,
     1335                                pDev->regs,
     1336                                dest+count,
     1337                                req_cnt-count);
    13401338        }
    13411339        /* no need to unmask IRQ as IRQ Handler do that for us. */
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