Changeset bc3bdf2 in rtems


Ignore:
Timestamp:
Jun 28, 2018, 12:59:38 PM (11 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
3be4478f
Parents:
ff7b104
git-author:
Sebastian Huber <sebastian.huber@…> (06/28/18 12:59:38)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/28/18 13:03:20)
Message:

riscv: Optimize and fix interrupt disable/enable

Use the atomic read and clear operation to disable interrupts.

Do not write the complete mstatus. Instead, set only the MIE bit
depending on the level parameter.

Update #3433.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/riscv/include/rtems/score/cpu.h

    rff7b104 rbc3bdf2  
    4949#endif
    5050
     51#define RISCV_MSTATUS_MIE 0x8
     52
    5153#define CPU_INLINE_ENABLE_DISPATCH       FALSE
    5254#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
     
    116118#define _CPU_Initialize_vectors()
    117119
    118 /*
    119  *  Disable all interrupts for an RTEMS critical section.  The previous
    120  *  level is returned in _level.
    121  *
    122  */
    123 
    124 static inline unsigned long riscv_interrupt_disable( void )
    125 {
    126   unsigned long status = read_csr(mstatus);
    127   clear_csr(mstatus, MSTATUS_MIE);
    128   return status;
    129 }
    130 
    131 static inline void riscv_interrupt_enable(unsigned long level)
    132 {
    133   write_csr(mstatus, level);
     120static inline uint32_t riscv_interrupt_disable( void )
     121{
     122  unsigned long mstatus;
     123
     124  __asm__ volatile (
     125    "csrrc %0, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) :
     126      "=&r" ( mstatus )
     127  );
     128
     129  return mstatus & RISCV_MSTATUS_MIE;
     130}
     131
     132static inline void riscv_interrupt_enable( uint32_t level )
     133{
     134  __asm__ volatile ( "csrrs zero, mstatus, %0" : : "r" ( level ) );
    134135}
    135136
     
    148149RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( unsigned long level )
    149150{
    150   return ( level & MSTATUS_MIE ) != 0;
     151  return ( level & RISCV_MSTATUS_MIE ) != 0;
    151152}
    152153
     
    155156  if ( ( level & CPU_MODES_INTERRUPT_MASK) == 0 ) {
    156157    __asm__ volatile (
    157       "csrrs zero, mstatus, " RTEMS_XSTRING( MSTATUS_MIE )
     158      "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE )
    158159    );
    159160  } else {
    160161    __asm__ volatile (
    161       "csrrc zero, mstatus, " RTEMS_XSTRING( MSTATUS_MIE )
     162      "csrrc zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE )
    162163    );
    163164  }
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