Changeset bad8092c in rtems
- Timestamp:
- 03/31/04 03:49:17 (20 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- d352678
- Parents:
- 3f71ac1
- Location:
- c/src/lib/libbsp/powerpc/ppcn_60x
- Files:
-
- 29 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/powerpc/ppcn_60x/ChangeLog
r3f71ac1 rbad8092c 1 2004-03-31 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * clock/clock.c, console/config.c, console/console.c, 4 console/debugio.c, console/i8042.c, console/ns16550cfg.c, 5 console/ns16550cfg.h, console/vga.c, console/vga_p.h, 6 console/z85c30cfg.c, console/z85c30cfg.h, include/bsp.h, 7 include/nvram.h, include/pci.h, network/amd79c970.c, 8 network/amd79c970.h, nvram/mk48t18.h, nvram/nvram.c, 9 nvram/stk11c68.h, pci/pci.c, startup/bspstart.c, startup/genpvec.c, 10 startup/spurious.c, startup/swap.c, timer/timer.c, tod/cmos.h, 11 tod/tod.c, universe/universe.c: Convert to using c99 fixed size 12 types. 13 1 14 2004-02-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> 2 15 -
c/src/lib/libbsp/powerpc/ppcn_60x/clock/clock.c
r3f71ac1 rbad8092c 33 33 */ 34 34 35 volatile rtems_unsigned32Clock_driver_ticks;35 volatile uint32_t Clock_driver_ticks; 36 36 37 37 /* … … 39 39 */ 40 40 41 rtems_unsigned32Clock_Decrementer_value;41 uint32_t Clock_Decrementer_value; 42 42 43 43 rtems_isr_entry Old_ticker; … … 204 204 ) 205 205 { 206 rtems_unsigned32isrlevel;206 uint32_t isrlevel; 207 207 rtems_libio_ioctl_args_t *args = pargp; 208 208 -
c/src/lib/libbsp/powerpc/ppcn_60x/console/config.c
r3f71ac1 rbad8092c 280 280 static boolean config_PMX1553_probe(int minor) 281 281 { 282 u nsigned8ucBusNumber, ucSlotNumber, ucChannel;283 u nsigned8ucIntLine;284 u nsigned32ulPortBase, ulMemBase, ulDeviceID;285 u nsigned8*pucSIO_cir, *pucUart_int_sr, *pucUartDevIntReg;282 uint8_t ucBusNumber, ucSlotNumber, ucChannel; 283 uint8_t ucIntLine; 284 uint32_t ulPortBase, ulMemBase, ulDeviceID; 285 uint8_t *pucSIO_cir, *pucUart_int_sr, *pucUartDevIntReg; 286 286 PSP_WRITE_REGISTERS pNS16550Write; 287 287 … … 330 330 &ulMemBase); 331 331 332 pucUartDevIntReg=(u nsigned8*)(PCI_MEM_BASE+ulMemBase);333 pucUart_int_sr=(u nsigned8*)(PCI_MEM_BASE+ulMemBase+0x10);334 pucSIO_cir=(u nsigned8*)(PCI_MEM_BASE+ulMemBase+0x18);332 pucUartDevIntReg=(uint8_t*)(PCI_MEM_BASE+ulMemBase); 333 pucUart_int_sr=(uint8_t*)(PCI_MEM_BASE+ulMemBase+0x10); 334 pucSIO_cir=(uint8_t*)(PCI_MEM_BASE+ulMemBase+0x18); 335 335 336 336 /* … … 441 441 * Scale requested baud rate for 16 MHz clock 442 442 */ 443 (u nsigned32)Console_Port_Tbl[minor].pDeviceParams*=7373;444 (u nsigned32)Console_Port_Tbl[minor].pDeviceParams/=16000;443 (uint32_t)Console_Port_Tbl[minor].pDeviceParams*=7373; 444 (uint32_t)Console_Port_Tbl[minor].pDeviceParams/=16000; 445 445 #else 446 446 /* 447 447 * Scale requested baud rate for 22.1184 MHz clock 448 448 */ 449 (u nsigned32)Console_Port_Tbl[minor].pDeviceParams/=3;449 (uint32_t)Console_Port_Tbl[minor].pDeviceParams/=3; 450 450 #endif 451 451 /* … … 453 453 * apply a div 4 here rather than in hardware (using MCR bit 7). 454 454 */ 455 (u nsigned32)Console_Port_Tbl[minor].pDeviceParams/=4;455 (uint32_t)Console_Port_Tbl[minor].pDeviceParams/=4; 456 456 457 457 return(TRUE); -
c/src/lib/libbsp/powerpc/ppcn_60x/console/console.c
r3f71ac1 rbad8092c 293 293 { 294 294 char *s; 295 u nsigned32Irql;295 uint32_t Irql; 296 296 297 297 rtems_interrupt_disable(Irql); … … 323 323 void 324 324 DEBUG_puth( 325 u nsigned32ulHexNum325 uint32_t ulHexNum 326 326 ) 327 327 { 328 328 unsigned long i,d; 329 u nsigned32Irql;329 uint32_t Irql; 330 330 331 331 rtems_interrupt_disable(Irql); -
c/src/lib/libbsp/powerpc/ppcn_60x/console/debugio.c
r3f71ac1 rbad8092c 61 61 { 62 62 char *s; 63 u nsigned32Irql;63 uint32_t Irql; 64 64 65 65 rtems_interrupt_disable(Irql); … … 90 90 91 91 void DEBUG_puth( 92 u nsigned32ulHexNum92 uint32_t ulHexNum 93 93 ) 94 94 { 95 95 unsigned long i,d; 96 u nsigned32Irql;96 uint32_t Irql; 97 97 void (*poll)(int minor, char cChar); 98 98 -
c/src/lib/libbsp/powerpc/ppcn_60x/console/i8042.c
r3f71ac1 rbad8092c 84 84 static void i8042_scan_code( 85 85 int minor, 86 u nsigned8ucScan86 uint8_t ucScan 87 87 ); 88 88 #endif … … 108 108 { 109 109 #if CONSOLE_USE_INTERRUPTS 110 u nsigned32Irql;111 u nsigned8ucScan;110 uint32_t Irql; 111 uint8_t ucScan; 112 112 113 113 /* … … 134 134 i8042_outbyte_raw( 135 135 int minor, 136 u nsigned8ucData137 ) 138 { 139 u nsigned32i;140 u nsigned8Status;136 uint8_t ucData 137 ) 138 { 139 uint32_t i; 140 uint8_t Status; 141 141 142 142 #if CONSOLE_USE_INTERRUPTS 143 u nsigned32Irql;143 uint32_t Irql; 144 144 145 145 if(bInterruptsEnabled) … … 180 180 i8042_inbyte_polled( 181 181 int minor, 182 u nsigned8*pucData183 ) 184 { 185 u nsigned8Status;182 uint8_t *pucData 183 ) 184 { 185 uint8_t Status; 186 186 187 187 inport_byte(Console_Port_Tbl[minor].ulCtrlPort1, Status); … … 201 201 i8042_inbyte_raw( 202 202 int minor, 203 u nsigned8*pucData203 uint8_t *pucData 204 204 ) 205 205 { … … 250 250 i8042_outbyte_cmd_polled( 251 251 int minor, 252 u nsigned8ucCommand253 ) 254 { 255 u nsigned32i;256 u nsigned8Status;252 uint8_t ucCommand 253 ) 254 { 255 uint32_t i; 256 uint8_t Status; 257 257 258 258 /* … … 294 294 static void i8042_process_two_code( 295 295 int minor, 296 u nsigned8ucScan,296 uint8_t ucScan, 297 297 boolean bMakenBreak 298 298 ) … … 417 417 418 418 static boolean i8042_process_qualifiers( 419 u nsigned8ucScan,419 uint8_t ucScan, 420 420 boolean bMakenBreak 421 421 ) … … 469 469 static boolean i8042_process_top_row( 470 470 int minor, 471 u nsigned8ucScan471 uint8_t ucScan 472 472 ) 473 473 { … … 475 475 char cASCIIFnCode; 476 476 #if CONSOLE_USE_INTERRUPTS==0 477 u nsigned8ucKeyboardAck;477 uint8_t ucKeyboardAck; 478 478 #endif 479 479 … … 634 634 static boolean i8042_process_keypad( 635 635 int minor, 636 u nsigned8ucScan636 uint8_t ucScan 637 637 ) 638 638 { … … 736 736 static void i8042_scan_code( 737 737 int minor, 738 u nsigned8ucScan738 uint8_t ucScan 739 739 ) 740 740 { … … 871 871 boolean i8042_probe(int minor) 872 872 { 873 u nsigned8ucKeyboardAck;874 u nsigned8ucKeyboardID1, ucKeyboardID2;873 uint8_t ucKeyboardAck; 874 uint8_t ucKeyboardID1, ucKeyboardID2; 875 875 876 876 if(!vga_probe(minor)) … … 921 921 void i8042_init(int minor) 922 922 { 923 u nsigned8ucKeyboardAck;923 uint8_t ucKeyboardAck; 924 924 925 925 vga_init(minor); … … 954 954 ) 955 955 { 956 u nsigned8ucScan;956 uint8_t ucScan; 957 957 char ucData; 958 958 … … 989 989 ) 990 990 { 991 u nsigned8Status;992 u nsigned8ucData;991 uint8_t Status; 992 uint8_t ucData; 993 993 994 994 inport_byte(Console_Port_Tbl[minor].ulCtrlPort1, Status); -
c/src/lib/libbsp/powerpc/ppcn_60x/console/ns16550cfg.c
r3f71ac1 rbad8092c 29 29 #include <bsp.h> 30 30 31 u nsigned8Read_ns16550_register(32 u nsigned32ulCtrlPort,33 u nsigned8ucRegNum31 uint8_t Read_ns16550_register( 32 uint32_t ulCtrlPort, 33 uint8_t ucRegNum 34 34 ) 35 35 { … … 42 42 43 43 void Write_ns16550_register( 44 u nsigned32ulCtrlPort,45 u nsigned8ucRegNum,46 u nsigned8ucData44 uint32_t ulCtrlPort, 45 uint8_t ucRegNum, 46 uint8_t ucData 47 47 ) 48 48 { -
c/src/lib/libbsp/powerpc/ppcn_60x/console/ns16550cfg.h
r3f71ac1 rbad8092c 37 37 */ 38 38 39 u nsigned8Read_ns16550_register(40 u nsigned32ulCtrlPort,41 u nsigned8ucRegNum39 uint8_t Read_ns16550_register( 40 uint32_t ulCtrlPort, 41 uint8_t ucRegNum 42 42 ); 43 43 44 44 void Write_ns16550_register( 45 u nsigned32ulCtrlPort,46 u nsigned8ucRegNum,47 u nsigned8ucData45 uint32_t ulCtrlPort, 46 uint8_t ucRegNum, 47 uint8_t ucData 48 48 ); 49 49 -
c/src/lib/libbsp/powerpc/ppcn_60x/console/vga.c
r3f71ac1 rbad8092c 65 65 +--------------------------------------------------------------------------*/ 66 66 /* Physical address of start of video text memory. */ 67 static u nsigned16 *videoRam = (unsigned16*)VGA_FB;67 static uint16_t *videoRam = (uint16_t*)VGA_FB; 68 68 /* Pointer for current output position in display. */ 69 static u nsigned16 *videoRamPtr = (unsigned16*)VGA_FB;70 static u nsigned8videoRows = VGA_NUM_ROWS; /* Number of rows in display. */71 static u nsigned8videoCols = VGA_NUM_COLS; /* Number of columns in display. */72 static u nsigned8cursRow = 0; /* Current cursor row. */73 static u nsigned8cursCol = 0; /* Current cursor column. */69 static uint16_t *videoRamPtr = (uint16_t*)VGA_FB; 70 static uint8_t videoRows = VGA_NUM_ROWS; /* Number of rows in display. */ 71 static uint8_t videoCols = VGA_NUM_COLS; /* Number of columns in display. */ 72 static uint8_t cursRow = 0; /* Current cursor row. */ 73 static uint8_t cursCol = 0; /* Current cursor column. */ 74 74 75 75 … … 82 82 +--------------------------------------------------------------------------*/ 83 83 static inline void 84 setHardwareCursorPos(u nsigned16videoCursor)84 setHardwareCursorPos(uint16_t videoCursor) 85 85 { 86 86 VGA_WRITE_CRTC(0x0e, (videoCursor >> 8) & 0xff); … … 112 112 +--------------------------------------------------------------------------*/ 113 113 static void 114 scrollUp(u nsigned8lines)114 scrollUp(uint8_t lines) 115 115 { 116 116 /* Number of blank display cells on bottom of window. */ 117 u nsigned16blankCount;117 uint16_t blankCount; 118 118 119 119 /* Source and destination pointers for memory copy operations. */ 120 u nsigned16*ptrDst, *ptrSrc;120 uint16_t *ptrDst, *ptrSrc; 121 121 122 122 if(lines<videoRows) /* Move window's contents up. */ … … 126 126 * of display (total - blank). 127 127 */ 128 u nsigned16nonBlankCount;128 uint16_t nonBlankCount; 129 129 130 130 blankCount = lines * videoCols; … … 337 337 boolean vga_probe(int minor) 338 338 { 339 u nsigned8ucMiscIn;339 uint8_t ucMiscIn; 340 340 341 341 /* -
c/src/lib/libbsp/powerpc/ppcn_60x/console/vga_p.h
r3f71ac1 rbad8092c 22 22 #endif 23 23 24 #define VGA_FB ((u nsigned32)PCI_MEM_BASE+0xb8000)24 #define VGA_FB ((uint32_t)PCI_MEM_BASE+0xb8000) 25 25 #define VGA_NUM_ROWS 25 26 26 #define VGA_NUM_COLS 80 … … 40 40 #define VGA_WRITE_ATT(reg, val) \ 41 41 { \ 42 volatile u nsigned8ucDummy; \42 volatile uint8_t ucDummy; \ 43 43 inport_byte(0x3da, ucDummy); \ 44 44 outport_byte(0x3c0, reg); \ -
c/src/lib/libbsp/powerpc/ppcn_60x/console/z85c30cfg.c
r3f71ac1 rbad8092c 35 35 */ 36 36 37 u nsigned8Read_85c30_register(38 u nsigned32ulCtrlPort,39 u nsigned8ucRegNum37 uint8_t Read_85c30_register( 38 uint32_t ulCtrlPort, 39 uint8_t ucRegNum 40 40 ) 41 41 { 42 u nsigned8ucData;42 uint8_t ucData; 43 43 44 44 outport_byte(ulCtrlPort, ucRegNum); … … 54 54 55 55 void Write_85c30_register( 56 u nsigned32ulCtrlPort,57 u nsigned8ucRegNum,58 u nsigned8ucData56 uint32_t ulCtrlPort, 57 uint8_t ucRegNum, 58 uint8_t ucData 59 59 ) 60 60 { … … 71 71 */ 72 72 73 u nsigned8Read_85c30_data(74 u nsigned32ulDataPort73 uint8_t Read_85c30_data( 74 uint32_t ulDataPort 75 75 ) 76 76 { 77 u nsigned8ucData;77 uint8_t ucData; 78 78 79 79 inport_byte(ulDataPort, ucData); … … 88 88 89 89 void Write_85c30_data( 90 u nsigned32ulDataPort,91 u nsigned8ucData90 uint32_t ulDataPort, 91 uint8_t ucData 92 92 ) 93 93 { -
c/src/lib/libbsp/powerpc/ppcn_60x/console/z85c30cfg.h
r3f71ac1 rbad8092c 37 37 */ 38 38 39 u nsigned8Read_85c30_register(40 u nsigned32ulCtrlPort,41 u nsigned8ucRegNum39 uint8_t Read_85c30_register( 40 uint32_t ulCtrlPort, 41 uint8_t ucRegNum 42 42 ); 43 43 44 44 void Write_85c30_register( 45 u nsigned32ulCtrlPort,46 u nsigned8ucRegNum,47 u nsigned8ucData45 uint32_t ulCtrlPort, 46 uint8_t ucRegNum, 47 uint8_t ucData 48 48 ); 49 49 50 u nsigned8Read_85c30_data(51 u nsigned32ulDataPort50 uint8_t Read_85c30_data( 51 uint32_t ulDataPort 52 52 ); 53 53 54 54 void Write_85c30_data( 55 u nsigned32ulDataPort,56 u nsigned8ucData55 uint32_t ulDataPort, 56 uint8_t ucData 57 57 ); 58 58 -
c/src/lib/libbsp/powerpc/ppcn_60x/include/bsp.h
r3f71ac1 rbad8092c 238 238 * bit transfers 239 239 */ 240 extern u nsigned16 Swap16(unsigned16usVal);241 extern u nsigned32 Swap32(unsigned32ulVal);240 extern uint16_t Swap16(uint16_t usVal); 241 extern uint32_t Swap32(uint32_t ulVal); 242 242 243 243 #define outport_byte(port, val) \ 244 244 EIEIO; \ 245 *(volatile u nsigned8*)(PCI_IO_BASE+ \245 *(volatile uint8_t*)(PCI_IO_BASE+ \ 246 246 (unsigned long)(port))=(val) 247 247 248 248 #define outport_16(port, val) \ 249 249 EIEIO; \ 250 *(volatile u nsigned16*)(PCI_IO_BASE+ \250 *(volatile uint16_t*)(PCI_IO_BASE+ \ 251 251 (unsigned long)(port))=Swap16(val) 252 252 253 253 #define outport_32(port, val) \ 254 254 EIEIO; \ 255 *(volatile u nsigned32*)(PCI_IO_BASE+ \255 *(volatile uint32_t*)(PCI_IO_BASE+ \ 256 256 (unsigned long)(port))=Swap32(val) 257 257 258 258 #define inport_byte(port, val) \ 259 259 EIEIO; \ 260 (val)=*(volatile u nsigned8*)(PCI_IO_BASE+ \260 (val)=*(volatile uint8_t*)(PCI_IO_BASE+ \ 261 261 (unsigned long)(port)) 262 262 263 263 #define inport_16(port, val) \ 264 264 EIEIO; \ 265 (val)=Swap16(*(volatile u nsigned16*)(PCI_IO_BASE+ \265 (val)=Swap16(*(volatile uint16_t*)(PCI_IO_BASE+ \ 266 266 (unsigned long)(port))) 267 267 268 268 #define inport_32(port, val) \ 269 269 EIEIO; \ 270 (val)=Swap32(*(volatile u nsigned32*)(PCI_IO_BASE+ \270 (val)=Swap32(*(volatile uint32_t*)(PCI_IO_BASE+ \ 271 271 (unsigned long)(port))) 272 272 … … 275 275 */ 276 276 typedef volatile struct _PLANARREGISTERS{ 277 u nsigned8Reserved0[0x803]; /* Offset 0x000 */278 u nsigned8SimmId; /* Offset 0x803 */279 u nsigned8SimmPresent; /* Offset 0x804 */280 u nsigned8Reserved1[3];281 u nsigned8HardfileLight; /* Offset 0x808 */282 u nsigned8Reserved2[3];283 u nsigned8EquipmentPresent1; /* Offset 0x80C */284 u nsigned8Reserved3;285 u nsigned8EquipmentPresent2; /* Offset 0x80e */286 u nsigned8Reserved4;287 u nsigned8PasswordProtect1; /* Offset 0x810 */288 u nsigned8Reserved5;289 u nsigned8PasswordProtect2; /* Offset 0x812 */290 u nsigned8Reserved6;291 u nsigned8L2Flush; /* Offset 0x814 */292 u nsigned8Reserved7[3];293 u nsigned8Keylock; /* Offset 0x818 */294 u nsigned8Reserved8[0x3c];295 u nsigned8BoardRevision; /* Offset 0x854 */296 u nsigned8Reserved9[0xf];297 u nsigned8BoardID; /* Offset 0x864 */298 u nsigned8Reserved10;299 u nsigned8MotherboardMemoryType; /* Offset 0x866 */300 u nsigned8Reserved11;301 u nsigned8MezzanineMemoryType; /* Offset 0x868 */277 uint8_t Reserved0[0x803]; /* Offset 0x000 */ 278 uint8_t SimmId; /* Offset 0x803 */ 279 uint8_t SimmPresent; /* Offset 0x804 */ 280 uint8_t Reserved1[3]; 281 uint8_t HardfileLight; /* Offset 0x808 */ 282 uint8_t Reserved2[3]; 283 uint8_t EquipmentPresent1; /* Offset 0x80C */ 284 uint8_t Reserved3; 285 uint8_t EquipmentPresent2; /* Offset 0x80e */ 286 uint8_t Reserved4; 287 uint8_t PasswordProtect1; /* Offset 0x810 */ 288 uint8_t Reserved5; 289 uint8_t PasswordProtect2; /* Offset 0x812 */ 290 uint8_t Reserved6; 291 uint8_t L2Flush; /* Offset 0x814 */ 292 uint8_t Reserved7[3]; 293 uint8_t Keylock; /* Offset 0x818 */ 294 uint8_t Reserved8[0x3c]; 295 uint8_t BoardRevision; /* Offset 0x854 */ 296 uint8_t Reserved9[0xf]; 297 uint8_t BoardID; /* Offset 0x864 */ 298 uint8_t Reserved10; 299 uint8_t MotherboardMemoryType; /* Offset 0x866 */ 300 uint8_t Reserved11; 301 uint8_t MezzanineMemoryType; /* Offset 0x868 */ 302 302 } PLANARREGISTERS, *PPLANARREGISTERS; 303 303 … … 379 379 #define Cause_tm27_intr() \ 380 380 do { \ 381 u nsigned32_clicks = 8; \381 uint32_t _clicks = 8; \ 382 382 asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ 383 383 } while (0) … … 386 386 #define Clear_tm27_intr() \ 387 387 do { \ 388 u nsigned32_clicks = 0xffffffff; \388 uint32_t _clicks = 0xffffffff; \ 389 389 asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ 390 390 } while (0) … … 392 392 #define Lower_tm27_intr() \ 393 393 do { \ 394 u nsigned32_msr = 0; \394 uint32_t _msr = 0; \ 395 395 _ISR_Set_level( 0 ); \ 396 396 asm volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ … … 456 456 */ 457 457 void DEBUG_puts( char *string ); 458 void DEBUG_puth( u nsigned32ulHexNum );458 void DEBUG_puth( uint32_t ulHexNum ); 459 459 460 460 void BSP_fatal_return( void ); … … 464 464 extern rtems_cpu_table Cpu_table; /* owned by BSP */ 465 465 466 extern u nsigned32bsp_isr_level;466 extern uint32_t bsp_isr_level; 467 467 468 468 #endif /* ASM */ -
c/src/lib/libbsp/powerpc/ppcn_60x/include/nvram.h
r3f71ac1 rbad8092c 34 34 * These routines access data in the NvRAM's OS area 35 35 */ 36 extern rtems_status_code ReadNvRAM8(u nsigned32 ulOffset, unsigned8*pucData);37 extern rtems_status_code WriteNvRAM8(u nsigned32 ulOffset, unsigned8ucValue);38 extern rtems_status_code ReadNvRAM16(u nsigned32 ulOffset, unsigned16*pusData);39 extern rtems_status_code WriteNvRAM16(u nsigned32 ulOffset, unsigned16usValue);40 extern rtems_status_code ReadNvRAM32(u nsigned32 ulOffset, unsigned32*pulData);41 extern rtems_status_code WriteNvRAM32(u nsigned32 ulOffset, unsigned32ulValue);36 extern rtems_status_code ReadNvRAM8(uint32_t ulOffset, uint8_t *pucData); 37 extern rtems_status_code WriteNvRAM8(uint32_t ulOffset, uint8_t ucValue); 38 extern rtems_status_code ReadNvRAM16(uint32_t ulOffset, uint16_t *pusData); 39 extern rtems_status_code WriteNvRAM16(uint32_t ulOffset, uint16_t usValue); 40 extern rtems_status_code ReadNvRAM32(uint32_t ulOffset, uint32_t *pulData); 41 extern rtems_status_code WriteNvRAM32(uint32_t ulOffset, uint32_t ulValue); 42 42 rtems_status_code ReadNvRAMBlock( 43 u nsigned32 ulOffset, unsigned8 *pucData, unsigned32length);43 uint32_t ulOffset, uint8_t *pucData, uint32_t length); 44 44 rtems_status_code WriteNvRAMBlock( 45 u nsigned32 ulOffset, unsigned8 *ucValue, unsigned32length);45 uint32_t ulOffset, uint8_t *ucValue, uint32_t length); 46 46 /* 47 47 * This routine returns the size of the NvRAM 48 48 */ 49 extern u nsigned32SizeNvRAM();49 extern uint32_t SizeNvRAM(); 50 50 51 51 /* -
c/src/lib/libbsp/powerpc/ppcn_60x/include/pci.h
r3f71ac1 rbad8092c 268 268 */ 269 269 extern rtems_status_code PCIConfigWrite8( 270 u nsigned8ucBusNumber,271 u nsigned8ucSlotNumber,272 u nsigned8ucFunctionNumber,273 u nsigned8ucOffset,274 u nsigned8ucValue270 uint8_t ucBusNumber, 271 uint8_t ucSlotNumber, 272 uint8_t ucFunctionNumber, 273 uint8_t ucOffset, 274 uint8_t ucValue 275 275 ); 276 276 277 277 extern rtems_status_code PCIConfigWrite16( 278 u nsigned8ucBusNumber,279 u nsigned8ucSlotNumber,280 u nsigned8ucFunctionNumber,281 u nsigned8ucOffset,282 u nsigned16usValue278 uint8_t ucBusNumber, 279 uint8_t ucSlotNumber, 280 uint8_t ucFunctionNumber, 281 uint8_t ucOffset, 282 uint16_t usValue 283 283 ); 284 284 285 285 extern rtems_status_code PCIConfigWrite32( 286 u nsigned8ucBusNumber,287 u nsigned8ucSlotNumber,288 u nsigned8ucFunctionNumber,289 u nsigned8ucOffset,290 u nsigned32ulValue286 uint8_t ucBusNumber, 287 uint8_t ucSlotNumber, 288 uint8_t ucFunctionNumber, 289 uint8_t ucOffset, 290 uint32_t ulValue 291 291 ); 292 292 293 293 extern rtems_status_code PCIConfigRead8( 294 u nsigned8ucBusNumber,295 u nsigned8ucSlotNumber,296 u nsigned8ucFunctionNumber,297 u nsigned8ucOffset,298 u nsigned8*pucValue294 uint8_t ucBusNumber, 295 uint8_t ucSlotNumber, 296 uint8_t ucFunctionNumber, 297 uint8_t ucOffset, 298 uint8_t *pucValue 299 299 ); 300 300 301 301 extern rtems_status_code PCIConfigRead16( 302 u nsigned8ucBusNumber,303 u nsigned8ucSlotNumber,304 u nsigned8ucFunctionNumber,305 u nsigned8ucOffset,306 u nsigned16*pusValue302 uint8_t ucBusNumber, 303 uint8_t ucSlotNumber, 304 uint8_t ucFunctionNumber, 305 uint8_t ucOffset, 306 uint16_t *pusValue 307 307 ); 308 308 309 309 extern rtems_status_code PCIConfigRead32( 310 u nsigned8ucBusNumber,311 u nsigned8ucSlotNumber,312 u nsigned8ucFunctionNumber,313 u nsigned8ucOffset,314 u nsigned32*pulValue310 uint8_t ucBusNumber, 311 uint8_t ucSlotNumber, 312 uint8_t ucFunctionNumber, 313 uint8_t ucOffset, 314 uint32_t *pulValue 315 315 ); 316 316 … … 318 318 * Return the number of PCI busses in the system 319 319 */ 320 extern u nsigned8BusCountPCI();320 extern uint8_t BusCountPCI(); 321 321 322 322 #endif /* _PCI_H_ */ -
c/src/lib/libbsp/powerpc/ppcn_60x/network/amd79c970.c
r3f71ac1 rbad8092c 101 101 initblk_t initBlk; 102 102 pc_net_t *pPCNet; 103 u nsigned32ulIntVector;103 uint32_t ulIntVector; 104 104 struct mbuf **rxMbuf; 105 105 struct mbuf **txMbuf; … … 143 143 amd79c970_isr (rtems_vector_number v) 144 144 { 145 u nsigned32ulCSR0, ulCSR4, ulCSR5;145 uint32_t ulCSR0, ulCSR4, ulCSR5; 146 146 amd79c970Context_t *dp; 147 147 int i; … … 221 221 struct mbuf *bp; 222 222 int i; 223 u nsigned8ucPCIBusCount;224 u nsigned8ucBusNumber;225 u nsigned8ucSlotNumber;226 u nsigned32ulDeviceID;227 u nsigned32ulBAR0;228 u nsigned8ucIntVector;229 u nsigned32ulInitClkPCIAddr;230 u nsigned32ulAPROM;231 u nsigned32ulCSR0;223 uint8_t ucPCIBusCount; 224 uint8_t ucBusNumber; 225 uint8_t ucSlotNumber; 226 uint32_t ulDeviceID; 227 uint32_t ulBAR0; 228 uint8_t ucIntVector; 229 uint32_t ulInitClkPCIAddr; 230 uint32_t ulAPROM; 231 uint32_t ulCSR0; 232 232 233 233 ucPCIBusCount=BusCountPCI(); … … 335 335 bp->data += sizeof (struct iface *); 336 336 dp->rxBdBase[i].rmde_addr= 337 Swap32((u nsigned32)bp->data+PCI_SYS_MEM_BASE);337 Swap32((uint32_t)bp->data+PCI_SYS_MEM_BASE); 338 338 dp->rxBdBase[i].rmde_bcnt= 339 339 Swap16(-(bp->size-sizeof (struct iface *))); … … 370 370 * Set the receive descriptor ring address 371 371 */ 372 dp->initBlk.ib_rdra=Swap32((u nsigned32)&dp->rxBdBase[0]+372 dp->initBlk.ib_rdra=Swap32((uint32_t)&dp->rxBdBase[0]+ 373 373 PCI_SYS_MEM_BASE); 374 374 … … 380 380 * Set the tranmit descriptor ring address 381 381 */ 382 dp->initBlk.ib_tdra=Swap32((u nsigned32)&dp->txBdBase[0]+382 dp->initBlk.ib_tdra=Swap32((uint32_t)&dp->txBdBase[0]+ 383 383 PCI_SYS_MEM_BASE); 384 384 … … 404 404 WR_CSR32(dp, CSR5, 0); 405 405 406 ulInitClkPCIAddr=(u nsigned32)&dp->initBlk+PCI_SYS_MEM_BASE;406 ulInitClkPCIAddr=(uint32_t)&dp->initBlk+PCI_SYS_MEM_BASE; 407 407 /* 408 408 * CSR2 must contain the high order 16 bits of the first word in … … 462 462 amd79c970_retire_tx_bd (amd79c970Context_t *dp) 463 463 { 464 u nsigned16status;465 u nsigned32error;464 uint16_t status; 465 uint32_t error; 466 466 int i; 467 467 int nRetired; … … 526 526 struct mbuf *bp; 527 527 tmde_t *firstTxBd, *txBd; 528 u nsigned16status;528 uint16_t status; 529 529 int nAdded; 530 530 … … 608 608 * Fill in the buffer descriptor 609 609 */ 610 txBd->tmde_addr=Swap32((u nsigned32)bp->data+PCI_SYS_MEM_BASE);610 txBd->tmde_addr=Swap32((uint32_t)bp->data+PCI_SYS_MEM_BASE); 611 611 txBd->tmde_bcnt=Swap16(-bp->cnt); 612 612 dp->txMbuf[dp->txBdHead] = bp; … … 677 677 amd79c970Context_t *dp=(amd79c970Context_t *)p2; 678 678 struct mbuf *bp; 679 rtems_unsigned16status;679 uint16_t status; 680 680 rmde_t *rxBd; 681 681 int rxBdIndex; … … 771 771 bp->data += sizeof (struct iface *); 772 772 rxBd->rmde_addr=Swap32( 773 (u nsigned32)bp->data+PCI_SYS_MEM_BASE);773 (uint32_t)bp->data+PCI_SYS_MEM_BASE); 774 774 rxBd->rmde_bcnt=Swap16( 775 775 -(bp->size-sizeof (struct iface *))); … … 798 798 { 799 799 amd79c970Context_t *dp; 800 u nsigned32ulCSR0;800 uint32_t ulCSR0; 801 801 int i; 802 802 … … 914 914 */ 915 915 pAmd79c970Context[i]=(amd79c970Context_t *) 916 (((u nsigned32)callocw(1,916 (((uint32_t)callocw(1, 917 917 sizeof(amd79c970Context_t)+16)+16) & ~15); 918 918 dp=pAmd79c970Context[i]; -
c/src/lib/libbsp/powerpc/ppcn_60x/network/amd79c970.h
r3f71ac1 rbad8092c 26 26 { 27 27 struct { 28 u nsigned16aprom[8]; /* 0x00 */29 u nsigned16rdp; /* 0x10 */30 u nsigned16rap; /* 0x14 */31 u nsigned16reset; /* 0x18 */32 u nsigned16bdp; /* 0x1C */28 uint16_t aprom[8]; /* 0x00 */ 29 uint16_t rdp; /* 0x10 */ 30 uint16_t rap; /* 0x14 */ 31 uint16_t reset; /* 0x18 */ 32 uint16_t bdp; /* 0x1C */ 33 33 } wio; 34 34 struct { 35 u nsigned32aprom[4]; /* 0x00 */36 u nsigned32rdp; /* 0x10 */37 u nsigned32rap; /* 0x12 */38 u nsigned32reset; /* 0x14 */39 u nsigned32bdp; /* 0x16 */35 uint32_t aprom[4]; /* 0x00 */ 36 uint32_t rdp; /* 0x10 */ 37 uint32_t rap; /* 0x12 */ 38 uint32_t reset; /* 0x14 */ 39 uint32_t bdp; /* 0x16 */ 40 40 } dwio; 41 41 } u; … … 49 49 50 50 typedef struct pc_net_eeprom { 51 u nsigned8EthNumber[6];52 u nsigned16Reserved1; /* Must be 0x0000 */53 u nsigned16Reserved2; /* Must be 0x1000 */54 u nsigned16User1;55 u nsigned16checksum;56 u nsigned16Reserved3; /* Must be 0x5757 */57 u nsigned16bcr16;58 u nsigned16bcr17;59 u nsigned16bcr18;60 u nsigned16bcr2;61 u nsigned16bcr21;62 u nsigned16Reserved4; /* Must be 0x0000 */63 u nsigned16Reserved5; /* Must be 0x0000 */64 u nsigned8Reserved6; /* Must be 0x00 */65 u nsigned8checksumAdjust;66 u nsigned16Reserved7; /* Must be 0x0000 */67 u nsigned16crc; /* CCITT checksum from Serial[] onwards */68 u nsigned8Serial[16]; /* Radstone Serial Number */51 uint8_t EthNumber[6]; 52 uint16_t Reserved1; /* Must be 0x0000 */ 53 uint16_t Reserved2; /* Must be 0x1000 */ 54 uint16_t User1; 55 uint16_t checksum; 56 uint16_t Reserved3; /* Must be 0x5757 */ 57 uint16_t bcr16; 58 uint16_t bcr17; 59 uint16_t bcr18; 60 uint16_t bcr2; 61 uint16_t bcr21; 62 uint16_t Reserved4; /* Must be 0x0000 */ 63 uint16_t Reserved5; /* Must be 0x0000 */ 64 uint8_t Reserved6; /* Must be 0x00 */ 65 uint8_t checksumAdjust; 66 uint16_t Reserved7; /* Must be 0x0000 */ 67 uint16_t crc; /* CCITT checksum from Serial[] onwards */ 68 uint8_t Serial[16]; /* Radstone Serial Number */ 69 69 } pc_net_eeprom_t; 70 70 … … 220 220 typedef volatile struct initblk { 221 221 /* mode can be set in csr15 */ 222 u nsigned16ib_mode; /* Chip's operating parameters */223 u nsigned8ib_rlen; /* rx ring length (power of 2) */224 u nsigned8ib_tlen; /* tx ring length (power of 2) */222 uint16_t ib_mode; /* Chip's operating parameters */ 223 uint8_t ib_rlen; /* rx ring length (power of 2) */ 224 uint8_t ib_tlen; /* tx ring length (power of 2) */ 225 225 /* 226 226 * The bytes must be swapped within the word, so that, for example, … … 230 230 * the bus will swap. 231 231 */ 232 u nsigned8ib_padr[8]; /* physical address */233 u nsigned16ib_ladrf[4]; /* logical address filter */234 u nsigned32ib_rdra; /* rcv ring desc addr */235 u nsigned32ib_tdra; /* xmit ring desc addr */232 uint8_t ib_padr[8]; /* physical address */ 233 uint16_t ib_ladrf[4]; /* logical address filter */ 234 uint32_t ib_rdra; /* rcv ring desc addr */ 235 uint32_t ib_tdra; /* xmit ring desc addr */ 236 236 } initblk_t; 237 237 … … 276 276 277 277 typedef volatile struct rmde { 278 u nsigned32rmde_addr; /* buf addr */279 280 u nsigned16rmde_bcnt;281 u nsigned16rmde_flags;282 283 u nsigned16rmde_mcnt;284 u nsigned16rmde_misc;285 286 u nsigned32align;278 uint32_t rmde_addr; /* buf addr */ 279 280 uint16_t rmde_bcnt; 281 uint16_t rmde_flags; 282 283 uint16_t rmde_mcnt; 284 uint16_t rmde_misc; 285 286 uint32_t align; 287 287 } rmde_t; 288 288 … … 320 320 */ 321 321 typedef volatile struct tmde { 322 u nsigned32tmde_addr; /* buf addr */323 324 u nsigned16tmde_bcnt;325 u nsigned16tmde_status; /* misc error and status bits */326 327 u nsigned32tmde_error;328 329 u nsigned32align;322 uint32_t tmde_addr; /* buf addr */ 323 324 uint16_t tmde_bcnt; 325 uint16_t tmde_status; /* misc error and status bits */ 326 327 uint32_t tmde_error; 328 329 uint32_t align; 330 330 } tmde_t; 331 331 … … 415 415 * Bit definitions for BCR19 416 416 */ 417 #define prom_EDI (u nsigned16)0x0001418 #define prom_EDO (u nsigned16)0x0001419 #define prom_ESK (u nsigned16)0x0002420 #define prom_ECS (u nsigned16)0x0004421 #define prom_EEN (u nsigned16)0x0010422 #define prom_EEDET (u nsigned16)0x2000423 #define prom_PVALID (u nsigned16)0x8000424 #define prom_PREAD (u nsigned16)0x4000417 #define prom_EDI (uint16_t)0x0001 418 #define prom_EDO (uint16_t)0x0001 419 #define prom_ESK (uint16_t)0x0002 420 #define prom_ECS (uint16_t)0x0004 421 #define prom_EEN (uint16_t)0x0010 422 #define prom_EEDET (uint16_t)0x2000 423 #define prom_PVALID (uint16_t)0x8000 424 #define prom_PREAD (uint16_t)0x4000 425 425 426 426 #endif -
c/src/lib/libbsp/powerpc/ppcn_60x/nvram/mk48t18.h
r3f71ac1 rbad8092c 34 34 35 35 typedef struct _MK48T18_CMOS_MAP { 36 u nsigned8SystemDependentArea2[8];37 u nsigned8FeatureByte0[1];38 u nsigned8FeatureByte1[1];39 u nsigned8Century; /* century byte in BCD */40 u nsigned8FeatureByte3[1];41 u nsigned8FeatureByte4[1];42 u nsigned8FeatureByte5[1];43 u nsigned8FeatureByte6[1];44 u nsigned8FeatureByte7[1];45 u nsigned8BootPW[14];46 rtems_unsigned16BootCrc; /* CRC on BootPW */47 u nsigned8ConfigPW[14];48 rtems_unsigned16ConfigCrc; /* CRC on ConfigPW */49 u nsigned8SystemDependentArea1[8];36 uint8_t SystemDependentArea2[8]; 37 uint8_t FeatureByte0[1]; 38 uint8_t FeatureByte1[1]; 39 uint8_t Century; /* century byte in BCD */ 40 uint8_t FeatureByte3[1]; 41 uint8_t FeatureByte4[1]; 42 uint8_t FeatureByte5[1]; 43 uint8_t FeatureByte6[1]; 44 uint8_t FeatureByte7[1]; 45 uint8_t BootPW[14]; 46 uint16_t BootCrc; /* CRC on BootPW */ 47 uint8_t ConfigPW[14]; 48 uint16_t ConfigCrc; /* CRC on ConfigPW */ 49 uint8_t SystemDependentArea1[8]; 50 50 /* 51 51 * The following are the RTC registers 52 52 */ 53 volatile u nsigned8Control;54 volatile u nsigned8Second:7; /* 0-59 */55 volatile u nsigned8Stop:1;56 volatile u nsigned8Minute; /* 0-59 */57 volatile u nsigned8Hour; /* 0-23 */58 volatile u nsigned8Day:3; /* 1-7 */59 volatile u nsigned8Resvd1:3; /* 0 */60 volatile u nsigned8FT:1; /* Frequency test bit - must be 0 */61 volatile u nsigned8Resvd2:1; /* 0 */62 volatile u nsigned8Date; /* 1-31 */63 volatile u nsigned8Month; /* 1-12 */64 volatile u nsigned8Year; /* 0-99 */53 volatile uint8_t Control; 54 volatile uint8_t Second:7; /* 0-59 */ 55 volatile uint8_t Stop:1; 56 volatile uint8_t Minute; /* 0-59 */ 57 volatile uint8_t Hour; /* 0-23 */ 58 volatile uint8_t Day:3; /* 1-7 */ 59 volatile uint8_t Resvd1:3; /* 0 */ 60 volatile uint8_t FT:1; /* Frequency test bit - must be 0 */ 61 volatile uint8_t Resvd2:1; /* 0 */ 62 volatile uint8_t Date; /* 1-31 */ 63 volatile uint8_t Month; /* 1-12 */ 64 volatile uint8_t Year; /* 0-99 */ 65 65 } MK48T18_CMOS_MAP, *PMK48T18_CMOS_MAP; 66 66 … … 74 74 #define MK48T18_NVSIZE 8192-sizeof(MK48T18_CMOS_MAP) 75 75 #define MK48T18_GESIZE (MK48T18_NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER)) 76 #define MK48T18_BASE (PMK48T18_NVRAM_MAP)((u nsigned8*)PCI_MEM_BASE+0x00800000)76 #define MK48T18_BASE (PMK48T18_NVRAM_MAP)((uint8_t*)PCI_MEM_BASE+0x00800000) 77 77 78 78 /* Here is the whole map of the MK48T18 NVRAM */ 79 79 typedef struct _MK48T18_NVRAM_MAP { 80 80 HEADER Header; 81 u nsigned8GEArea[MK48T18_GESIZE];82 u nsigned8OSArea[OSAREASIZE];83 u nsigned8ConfigArea[CONFSIZE];81 uint8_t GEArea[MK48T18_GESIZE]; 82 uint8_t OSArea[OSAREASIZE]; 83 uint8_t ConfigArea[CONFSIZE]; 84 84 MK48T18_CMOS_MAP CMOS; 85 85 } MK48T18_NVRAM_MAP, *PMK48T18_NVRAM_MAP; -
c/src/lib/libbsp/powerpc/ppcn_60x/nvram/nvram.c
r3f71ac1 rbad8092c 29 29 (*PNVRAMWRITE) 30 30 ( 31 u nsigned32ulOffset,32 u nsigned8ucByte31 uint32_t ulOffset, 32 uint8_t ucByte 33 33 ); 34 34 35 35 typedef 36 u nsigned836 uint8_t 37 37 (*PNVRAMREAD) 38 38 ( 39 u nsigned32ulOffset39 uint32_t ulOffset 40 40 ); 41 41 … … 51 51 PNVRAMREAD nvramRead; 52 52 PNVRAMCOMMIT nvramCommit; 53 u nsigned32nvramSize;53 uint32_t nvramSize; 54 54 } NVRAM_ENTRY_TABLE, *PNVRAM_ENTRY_TABLE; 55 55 … … 67 67 * DS1385 specific routines 68 68 */ 69 static void nvramDsWrite(u nsigned32 ulOffset, unsigned8ucByte);70 static u nsigned8 nvramDsRead(unsigned32ulOffset);69 static void nvramDsWrite(uint32_t ulOffset, uint8_t ucByte); 70 static uint8_t nvramDsRead(uint32_t ulOffset); 71 71 72 72 /* 73 73 * MK48T18 specific routines 74 74 */ 75 static void nvramMkWrite(u nsigned32 ulOffset, unsigned8ucByte);76 static u nsigned8 nvramMkRead(unsigned32ulOffset);75 static void nvramMkWrite(uint32_t ulOffset, uint8_t ucByte); 76 static uint8_t nvramMkRead(uint32_t ulOffset); 77 77 78 78 /* … … 129 129 static PNVRAM_ENTRY_TABLE pNvRAMFunc; 130 130 static boolean bNvRAMChanged=FALSE; 131 static u nsigned32ulPRePOSAreaLength;132 static u nsigned32ulPRePOSAreaOffset;131 static uint32_t ulPRePOSAreaLength; 132 static uint32_t ulPRePOSAreaOffset; 133 133 134 134 /* … … 140 140 * These routines support the ds1385 141 141 */ 142 static u nsigned8 nvramDsRead(unsigned32ulOffset)143 { 144 u nsigned8ucTemp;142 static uint8_t nvramDsRead(uint32_t ulOffset) 143 { 144 uint8_t ucTemp; 145 145 146 146 ucTemp = ulOffset & 0xff; … … 154 154 } 155 155 156 static void nvramDsWrite(u nsigned32 ulOffset, unsigned8ucData)157 { 158 u nsigned8ucTemp;159 160 ucTemp = (u nsigned8)(ulOffset & 0xff);161 outport_byte(DS1385_PORT_BASE, (u nsigned8) ucTemp);162 163 ucTemp = (u nsigned8)((ulOffset >> 8) & 0xf);164 outport_byte((DS1385_PORT_BASE + 1) , (u nsigned8)ucTemp);156 static void nvramDsWrite(uint32_t ulOffset, uint8_t ucData) 157 { 158 uint8_t ucTemp; 159 160 ucTemp = (uint8_t)(ulOffset & 0xff); 161 outport_byte(DS1385_PORT_BASE, (uint8_t) ucTemp); 162 163 ucTemp = (uint8_t)((ulOffset >> 8) & 0xf); 164 outport_byte((DS1385_PORT_BASE + 1) , (uint8_t)ucTemp); 165 165 166 166 outport_byte((DS1385_PORT_BASE+3), ucData); … … 170 170 * These routines support the MK48T18 and STK11C68 171 171 */ 172 static u nsigned8 nvramMkRead(unsigned32ulOffset)173 { 174 u nsigned8 *pNvRAM = (unsigned8*)MK48T18_BASE;172 static uint8_t nvramMkRead(uint32_t ulOffset) 173 { 174 uint8_t *pNvRAM = (uint8_t*)MK48T18_BASE; 175 175 176 176 return(pNvRAM[ulOffset]); 177 177 } 178 178 179 static void nvramMkWrite(u nsigned32 ulOffset, unsigned8ucData)180 { 181 u nsigned8 *pNvRAM = (unsigned8*)MK48T18_BASE;179 static void nvramMkWrite(uint32_t ulOffset, uint8_t ucData) 180 { 181 uint8_t *pNvRAM = (uint8_t*)MK48T18_BASE; 182 182 183 183 pNvRAM[ulOffset]=ucData; … … 288 288 * This routine returns the size of the NvRAM 289 289 */ 290 u nsigned32SizeNvRAM()290 uint32_t SizeNvRAM() 291 291 { 292 292 return(ulPRePOSAreaLength); … … 307 307 * This routine reads a byte from the NvRAM 308 308 */ 309 rtems_status_code ReadNvRAM8(u nsigned32 ulOffset, unsigned8*pucData)309 rtems_status_code ReadNvRAM8(uint32_t ulOffset, uint8_t *pucData) 310 310 { 311 311 if(ulOffset>ulPRePOSAreaLength) … … 322 322 * This routine writes a byte to the NvRAM 323 323 */ 324 rtems_status_code WriteNvRAM8(u nsigned32 ulOffset, unsigned8ucValue)324 rtems_status_code WriteNvRAM8(uint32_t ulOffset, uint8_t ucValue) 325 325 { 326 326 if(ulOffset>ulPRePOSAreaLength) … … 339 339 */ 340 340 rtems_status_code ReadNvRAMBlock( 341 u nsigned32 ulOffset, unsigned8 *pucData, unsigned32length)342 { 343 u nsigned32i;341 uint32_t ulOffset, uint8_t *pucData, uint32_t length) 342 { 343 uint32_t i; 344 344 345 345 if((ulOffset + length) > ulPRePOSAreaLength) … … 359 359 */ 360 360 rtems_status_code WriteNvRAMBlock( 361 u nsigned32 ulOffset, unsigned8 *ucValue, unsigned32length)362 { 363 u nsigned32i;361 uint32_t ulOffset, uint8_t *ucValue, uint32_t length) 362 { 363 uint32_t i; 364 364 365 365 if((ulOffset + length) > ulPRePOSAreaLength) … … 380 380 * The NVRAM holds data in Big-Endian format 381 381 */ 382 rtems_status_code ReadNvRAM16 (u nsigned32 ulOffset, unsigned16*pusData)383 { 384 u nsigned32ulTrueOffset=ulPRePOSAreaOffset+ulOffset;382 rtems_status_code ReadNvRAM16 (uint32_t ulOffset, uint16_t *pusData) 383 { 384 uint32_t ulTrueOffset=ulPRePOSAreaOffset+ulOffset; 385 385 386 386 if(ulOffset>ulPRePOSAreaLength) … … 395 395 } 396 396 397 rtems_status_code WriteNvRAM16 (u nsigned32 ulOffset, unsigned16usValue)398 { 399 u nsigned32ulTrueOffset=ulPRePOSAreaOffset+ulOffset;397 rtems_status_code WriteNvRAM16 (uint32_t ulOffset, uint16_t usValue) 398 { 399 uint32_t ulTrueOffset=ulPRePOSAreaOffset+ulOffset; 400 400 401 401 if(ulOffset>ulPRePOSAreaLength) … … 404 404 } 405 405 rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT); 406 pNvRAMFunc->nvramWrite(ulTrueOffset, (u nsigned8) (usValue >> 8));407 pNvRAMFunc->nvramWrite(ulTrueOffset + 1, (u nsigned8) usValue);406 pNvRAMFunc->nvramWrite(ulTrueOffset, (uint8_t) (usValue >> 8)); 407 pNvRAMFunc->nvramWrite(ulTrueOffset + 1, (uint8_t) usValue); 408 408 bNvRAMChanged=TRUE; 409 409 rtems_semaphore_release(semNvRAM); … … 411 411 } 412 412 413 rtems_status_code ReadNvRAM32 (u nsigned32 ulOffset, unsigned32*pulData)414 { 415 u nsigned32ulTrueOffset=ulPRePOSAreaOffset+ulOffset;413 rtems_status_code ReadNvRAM32 (uint32_t ulOffset, uint32_t *pulData) 414 { 415 uint32_t ulTrueOffset=ulPRePOSAreaOffset+ulOffset; 416 416 417 417 if(ulOffset>ulPRePOSAreaLength) … … 428 428 } 429 429 430 rtems_status_code WriteNvRAM32 (u nsigned32 ulOffset, unsigned32ulValue)431 { 432 u nsigned32ulTrueOffset=ulPRePOSAreaOffset+ulOffset;430 rtems_status_code WriteNvRAM32 (uint32_t ulOffset, uint32_t ulValue) 431 { 432 uint32_t ulTrueOffset=ulPRePOSAreaOffset+ulOffset; 433 433 434 434 if(ulOffset>ulPRePOSAreaLength) … … 437 437 } 438 438 rtems_semaphore_obtain(semNvRAM, RTEMS_WAIT, RTEMS_NO_TIMEOUT); 439 pNvRAMFunc->nvramWrite(ulTrueOffset, (u nsigned8) (ulValue >> 24));440 pNvRAMFunc->nvramWrite(ulTrueOffset + 1, (u nsigned8) (ulValue >> 16));441 pNvRAMFunc->nvramWrite(ulTrueOffset + 2, (u nsigned8) (ulValue >> 8));442 pNvRAMFunc->nvramWrite(ulTrueOffset + 3, (u nsigned8) ulValue);439 pNvRAMFunc->nvramWrite(ulTrueOffset, (uint8_t) (ulValue >> 24)); 440 pNvRAMFunc->nvramWrite(ulTrueOffset + 1, (uint8_t) (ulValue >> 16)); 441 pNvRAMFunc->nvramWrite(ulTrueOffset + 2, (uint8_t) (ulValue >> 8)); 442 pNvRAMFunc->nvramWrite(ulTrueOffset + 3, (uint8_t) ulValue); 443 443 bNvRAMChanged=TRUE; 444 444 rtems_semaphore_release(semNvRAM); … … 451 451 PHEADER pNvHeader = (PHEADER)0; 452 452 rtems_status_code sc; 453 u nsigned32ulLength, ulOffset;453 uint32_t ulLength, ulOffset; 454 454 455 455 if(ucSystemType==SYS_TYPE_PPC1) … … 503 503 * Access the header at the start of NvRAM 504 504 */ 505 ReadNvRAM32((u nsigned32)(&pNvHeader->OSAreaLength), &ulLength);506 ReadNvRAM32((u nsigned32)(&pNvHeader->OSAreaAddress), &ulOffset);505 ReadNvRAM32((uint32_t)(&pNvHeader->OSAreaLength), &ulLength); 506 ReadNvRAM32((uint32_t)(&pNvHeader->OSAreaAddress), &ulOffset); 507 507 508 508 /* -
c/src/lib/libbsp/powerpc/ppcn_60x/nvram/stk11c68.h
r3f71ac1 rbad8092c 29 29 #define STK11C68_NVSIZE 8192 30 30 #define STK11C68_GESIZE (STK11C68_NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER)) 31 #define STK11C68_BASE (PSTK11C68_NVRAM_MAP)((u nsigned8*)PCI_MEM_BASE+0x00800000)31 #define STK11C68_BASE (PSTK11C68_NVRAM_MAP)((uint8_t*)PCI_MEM_BASE+0x00800000) 32 32 33 33 /* … … 39 39 typedef struct _STK11C68_NVRAM_MAP { 40 40 HEADER Header; 41 u nsigned8GEArea[STK11C68_GESIZE];42 u nsigned8OSArea[OSAREASIZE];43 u nsigned8ConfigArea[CONFSIZE];41 uint8_t GEArea[STK11C68_GESIZE]; 42 uint8_t OSArea[OSAREASIZE]; 43 uint8_t ConfigArea[CONFSIZE]; 44 44 } STK11C68_NVRAM_MAP, *PSTK11C68_NVRAM_MAP; 45 45 -
c/src/lib/libbsp/powerpc/ppcn_60x/pci/pci.c
r3f71ac1 rbad8092c 49 49 * Private data 50 50 */ 51 static u nsigned8ucMaxPCIBus;51 static uint8_t ucMaxPCIBus; 52 52 53 53 /* … … 55 55 */ 56 56 rtems_status_code PCIConfigWrite8( 57 u nsigned8ucBusNumber,58 u nsigned8ucSlotNumber,59 u nsigned8ucFunctionNumber,60 u nsigned8ucOffset,61 u nsigned8ucValue57 uint8_t ucBusNumber, 58 uint8_t ucSlotNumber, 59 uint8_t ucFunctionNumber, 60 uint8_t ucOffset, 61 uint8_t ucValue 62 62 ) 63 63 { … … 87 87 88 88 rtems_status_code PCIConfigWrite16( 89 u nsigned8ucBusNumber,90 u nsigned8ucSlotNumber,91 u nsigned8ucFunctionNumber,92 u nsigned8ucOffset,93 u nsigned16usValue89 uint8_t ucBusNumber, 90 uint8_t ucSlotNumber, 91 uint8_t ucFunctionNumber, 92 uint8_t ucOffset, 93 uint16_t usValue 94 94 ) 95 95 { … … 119 119 120 120 rtems_status_code PCIConfigWrite32( 121 u nsigned8ucBusNumber,122 u nsigned8ucSlotNumber,123 u nsigned8ucFunctionNumber,124 u nsigned8ucOffset,125 u nsigned32ulValue121 uint8_t ucBusNumber, 122 uint8_t ucSlotNumber, 123 uint8_t ucFunctionNumber, 124 uint8_t ucOffset, 125 uint32_t ulValue 126 126 ) 127 127 { … … 151 151 152 152 rtems_status_code PCIConfigRead8( 153 u nsigned8ucBusNumber,154 u nsigned8ucSlotNumber,155 u nsigned8ucFunctionNumber,156 u nsigned8ucOffset,157 u nsigned8*pucValue153 uint8_t ucBusNumber, 154 uint8_t ucSlotNumber, 155 uint8_t ucFunctionNumber, 156 uint8_t ucOffset, 157 uint8_t *pucValue 158 158 ) 159 159 { … … 183 183 184 184 rtems_status_code PCIConfigRead16( 185 u nsigned8ucBusNumber,186 u nsigned8ucSlotNumber,187 u nsigned8ucFunctionNumber,188 u nsigned8ucOffset,189 u nsigned16*pusValue185 uint8_t ucBusNumber, 186 uint8_t ucSlotNumber, 187 uint8_t ucFunctionNumber, 188 uint8_t ucOffset, 189 uint16_t *pusValue 190 190 ) 191 191 { … … 215 215 216 216 rtems_status_code PCIConfigRead32( 217 u nsigned8ucBusNumber,218 u nsigned8ucSlotNumber,219 u nsigned8ucFunctionNumber,220 u nsigned8ucOffset,221 u nsigned32*pulValue217 uint8_t ucBusNumber, 218 uint8_t ucSlotNumber, 219 uint8_t ucFunctionNumber, 220 uint8_t ucOffset, 221 uint32_t *pulValue 222 222 ) 223 223 { … … 251 251 void InitializePCI() 252 252 { 253 u nsigned8ucSlotNumber, ucFnNumber, ucNumFuncs;254 u nsigned8ucHeader;255 u nsigned8ucBaseClass, ucSubClass, ucMaxSubordinate;256 u nsigned32ulDeviceID;253 uint8_t ucSlotNumber, ucFnNumber, ucNumFuncs; 254 uint8_t ucHeader; 255 uint8_t ucBaseClass, ucSubClass, ucMaxSubordinate; 256 uint32_t ulDeviceID; 257 257 258 258 /* … … 337 337 * Return the number of PCI busses in the system 338 338 */ 339 u nsigned8BusCountPCI()339 uint8_t BusCountPCI() 340 340 { 341 341 return(ucMaxPCIBus+1); -
c/src/lib/libbsp/powerpc/ppcn_60x/startup/bspstart.c
r3f71ac1 rbad8092c 67 67 68 68 rtems_cpu_table Cpu_table; 69 rtems_unsigned32bsp_isr_level;69 uint32_t bsp_isr_level; 70 70 71 71 static int stdin_fd, stdout_fd, stderr_fd; … … 81 81 82 82 void bsp_postdriver_hook(void); 83 void bsp_libc_init( void *, u nsigned32, int );83 void bsp_libc_init( void *, uint32_t, int ); 84 84 85 85 /* … … 92 92 void bsp_pretasking_hook(void) 93 93 { 94 rtems_unsigned32heap_start;95 rtems_unsigned32heap_size;96 97 heap_start = ( rtems_unsigned32) &end;94 uint32_t heap_start; 95 uint32_t heap_size; 96 97 heap_start = (uint32_t) &end; 98 98 if (heap_start & (CPU_ALIGNMENT-1)) 99 99 heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); … … 166 166 unsigned char *work_space_start; 167 167 unsigned char ucBoardRev, ucMothMemType, ucEquipPres1, ucEquipPres2; 168 u nsigned16usPVR=0;169 u nsigned8ucTempl, ucTemph;170 u nsigned8ucBanksPresent;171 u nsigned8ucSimmPresent;172 u nsigned32ulCurBank, ulTopBank;168 uint16_t usPVR=0; 169 uint8_t ucTempl, ucTemph; 170 uint8_t ucBanksPresent; 171 uint8_t ucSimmPresent; 172 uint32_t ulCurBank, ulTopBank; 173 173 174 174 /* -
c/src/lib/libbsp/powerpc/ppcn_60x/startup/genpvec.c
r3f71ac1 rbad8092c 47 47 * Current 8259 masks 48 48 */ 49 u nsigned8ucMaster8259Mask;50 u nsigned8ucSlave8259Mask;49 uint8_t ucMaster8259Mask; 50 uint8_t ucSlave8259Mask; 51 51 52 52 /* … … 66 66 */ 67 67 EE_ISR_Type ISR_Nodes [NUM_LIRQ_HANDLERS]; 68 rtems_unsigned16Nodes_Used;68 uint16_t Nodes_Used; 69 69 Chain_Control ISR_Array [NUM_LIRQ]; 70 70 … … 178 178 ) 179 179 { 180 rtems_unsigned16vec_idx = vector - PPCN_60X_8259_IRQ_BASE;181 rtems_unsigned32index;180 uint16_t vec_idx = vector - PPCN_60X_8259_IRQ_BASE; 181 uint32_t index; 182 182 183 183 assert (Nodes_Used < NUM_LIRQ_HANDLERS); … … 223 223 ) 224 224 { 225 u nsigned16index;226 u nsigned8ucISr;225 uint16_t index; 226 uint8_t ucISr; 227 227 EE_ISR_Type *node; 228 228 229 index = *((volatile u nsigned8*)IRQ_VECTOR_BASE);229 index = *((volatile uint8_t*)IRQ_VECTOR_BASE); 230 230 231 231 /* -
c/src/lib/libbsp/powerpc/ppcn_60x/startup/spurious.c
r3f71ac1 rbad8092c 176 176 void bsp_spurious_initialize() 177 177 { 178 rtems_unsigned32trap;178 uint32_t trap; 179 179 180 180 for ( trap=0 ; trap < PPC_IRQ_LAST ; trap++ ) { -
c/src/lib/libbsp/powerpc/ppcn_60x/startup/swap.c
r3f71ac1 rbad8092c 28 28 29 29 inline unsigned int Swap32( 30 u nsigned32ulValue30 uint32_t ulValue 31 31 ) 32 32 { 33 u nsigned32ulSwapped;33 uint32_t ulSwapped; 34 34 35 35 asm volatile( … … 47 47 48 48 inline unsigned int Swap16( 49 u nsigned16usValue49 uint16_t usValue 50 50 ) 51 51 { 52 u nsigned16usSwapped;52 uint16_t usSwapped; 53 53 54 54 asm volatile( -
c/src/lib/libbsp/powerpc/ppcn_60x/timer/timer.c
r3f71ac1 rbad8092c 22 22 #include <bsp.h> 23 23 24 rtems_unsigned64Timer_driver_Start_time;24 uint64_t Timer_driver_Start_time; 25 25 26 26 rtems_boolean Timer_driver_Find_average_overhead; … … 44 44 int Read_timer() 45 45 { 46 rtems_unsigned64clicks;47 rtems_unsigned64total64;48 rtems_unsigned32total;46 uint64_t clicks; 47 uint64_t total64; 48 uint32_t total; 49 49 50 50 /* approximately CLOCK_SPEED clicks per microsecond */ … … 56 56 total64 = clicks - Timer_driver_Start_time; 57 57 58 assert( total64 <= 0xffffffff ); /* fits into a u nsigned32*/58 assert( total64 <= 0xffffffff ); /* fits into a uint32_t */ 59 59 60 total = ( rtems_unsigned32) total64;60 total = (uint32_t) total64; 61 61 62 62 if ( Timer_driver_Find_average_overhead == 1 ) -
c/src/lib/libbsp/powerpc/ppcn_60x/tod/cmos.h
r3f71ac1 rbad8092c 68 68 69 69 typedef struct _CMOS_MAP { 70 volatile rtems_unsigned8DateAndTime[14];70 volatile uint8_t DateAndTime[14]; 71 71 72 rtems_unsigned8SystemDependentArea1[2];73 rtems_unsigned8SystemDependentArea2[8];74 rtems_unsigned8FeatureByte0[1];75 rtems_unsigned8FeatureByte1[1]; /* 19 = PW Flag;72 uint8_t SystemDependentArea1[2]; 73 uint8_t SystemDependentArea2[8]; 74 uint8_t FeatureByte0[1]; 75 uint8_t FeatureByte1[1]; /* 19 = PW Flag; 76 76 attribute = write protect */ 77 rtems_unsigned8Century[1]; /* century byte in BCD, e.g. 0x19 currently */78 rtems_unsigned8FeatureByte3[1];79 rtems_unsigned8FeatureByte4[1];80 rtems_unsigned8FeatureByte5[1];81 rtems_unsigned8FeatureByte6[1];82 rtems_unsigned8FeatureByte7[1]; /* 1F = Alternate PW Flag;77 uint8_t Century[1]; /* century byte in BCD, e.g. 0x19 currently */ 78 uint8_t FeatureByte3[1]; 79 uint8_t FeatureByte4[1]; 80 uint8_t FeatureByte5[1]; 81 uint8_t FeatureByte6[1]; 82 uint8_t FeatureByte7[1]; /* 1F = Alternate PW Flag; 83 83 attribute = write protect */ 84 rtems_unsigned8BootPW[14]; /* Power-on password needed to boot system;84 uint8_t BootPW[14]; /* Power-on password needed to boot system; 85 85 reset value = 0x00000000000000005a5a5a5a5a5a); 86 86 attribute = lock */ 87 rtems_unsigned8BootCrc[2]; /* CRC on BootPW */88 rtems_unsigned8ConfigPW[14]; /* Configuration Password needed to87 uint8_t BootCrc[2]; /* CRC on BootPW */ 88 uint8_t ConfigPW[14]; /* Configuration Password needed to 89 89 change configuration of system; 90 90 reset value = 0x00000000000000005a5a5a5a5a5a); 91 91 attribute = lock */ 92 rtems_unsigned8ConfigCrc[2]; /* CRC on ConfigPW */92 uint8_t ConfigCrc[2]; /* CRC on ConfigPW */ 93 93 } CMOS_MAP, *PCMOS_MAP; 94 94 -
c/src/lib/libbsp/powerpc/ppcn_60x/tod/tod.c
r3f71ac1 rbad8092c 89 89 * This only works for the Gregorian calendar - i.e. after 1752 (in the UK) 90 90 */ 91 rtems_unsigned891 uint8_t 92 92 GregorianDay(rtems_time_of_day *pTOD) 93 93 { … … 127 127 pTOD->day; 128 128 129 return(( rtems_unsigned8)(day%7));129 return((uint8_t)(day%7)); 130 130 } 131 131 132 132 void 133 133 DsWriteRawClockRegister ( 134 rtems_unsigned8Register,135 rtems_unsigned8Value134 uint8_t Register, 135 uint8_t Value 136 136 ) 137 137 … … 157 157 158 158 { 159 outport_byte(( rtems_unsigned8*)RTC_PORT, Register & 0x7f);159 outport_byte((uint8_t*)RTC_PORT, Register & 0x7f); 160 160 161 161 /* Read the realtime clock register value. */ 162 162 163 outport_byte(( rtems_unsigned8*)(RTC_PORT + 1), Value);163 outport_byte((uint8_t*)(RTC_PORT + 1), Value); 164 164 return; 165 165 } 166 166 167 rtems_unsigned8 167 uint8_t 168 168 DsReadRawClockRegister ( 169 rtems_unsigned8Register169 uint8_t Register 170 170 ) 171 171 … … 191 191 192 192 { 193 rtems_unsigned8ucDataByte;194 195 outport_byte(( rtems_unsigned8*)RTC_PORT, Register & 0x7f);193 uint8_t ucDataByte; 194 195 outport_byte((uint8_t*)RTC_PORT, Register & 0x7f); 196 196 197 197 /* Read the realtime clock register value. */ 198 198 199 inport_byte(( rtems_unsigned8*)(RTC_PORT + 1), ucDataByte);199 inport_byte((uint8_t*)(RTC_PORT + 1), ucDataByte); 200 200 return ucDataByte; 201 201 } … … 203 203 void 204 204 DsWriteClockRegister ( 205 rtems_unsigned8Register,206 rtems_unsigned8Value205 uint8_t Register, 206 uint8_t Value 207 207 ) 208 208 … … 227 227 228 228 { 229 rtems_unsigned8BcdValue;229 uint8_t BcdValue; 230 230 231 231 BcdValue = Bin2BCD(Value); … … 234 234 } 235 235 236 rtems_unsigned8 236 uint8_t 237 237 DsReadClockRegister ( 238 rtems_unsigned8Register238 uint8_t Register 239 239 ) 240 240 … … 256 256 257 257 { 258 rtems_unsigned8BcdValue;258 uint8_t BcdValue; 259 259 260 260 BcdValue = DsReadRawClockRegister(Register); … … 290 290 291 291 { 292 rtems_unsigned8ucDataByte;292 uint8_t ucDataByte; 293 293 PCMOS_MAP pCMOS = (PCMOS_MAP)0; 294 294 … … 308 308 309 309 DsWriteClockRegister(RTC_YEAR, 310 ( rtems_unsigned8)(pTOD->year%100));310 (uint8_t)(pTOD->year%100)); 311 311 if(pTOD->year>=100) 312 312 { 313 DsWriteClockRegister(( rtems_unsigned8)313 DsWriteClockRegister((uint8_t) 314 314 ((unsigned long)&pCMOS->Century), 315 315 pTOD->year/100); 316 316 } 317 317 DsWriteClockRegister(RTC_MONTH, 318 ( rtems_unsigned8)pTOD->month);318 (uint8_t)pTOD->month); 319 319 DsWriteClockRegister(RTC_DAY_OF_MONTH, 320 ( rtems_unsigned8)pTOD->day);320 (uint8_t)pTOD->day); 321 321 DsWriteClockRegister(RTC_DAY_OF_WEEK, 322 ( rtems_unsigned8)322 (uint8_t) 323 323 (GregorianDay(pTOD) + 1)); 324 324 DsWriteClockRegister(RTC_HOUR, 325 ( rtems_unsigned8)pTOD->hour);325 (uint8_t)pTOD->hour); 326 326 DsWriteClockRegister(RTC_MINUTE, 327 ( rtems_unsigned8)pTOD->minute);327 (uint8_t)pTOD->minute); 328 328 DsWriteClockRegister(RTC_SECOND, 329 ( rtems_unsigned8)pTOD->second);329 (uint8_t)pTOD->second); 330 330 331 331 /* Set the realtime clock control to update the time. */ … … 367 367 368 368 { 369 rtems_unsigned8ucDataByte;369 uint8_t ucDataByte; 370 370 PCMOS_MAP pCMOS = (PCMOS_MAP)0; 371 371 … … 386 386 /* Read the realtime clock values. */ 387 387 388 pTOD->year=( rtems_unsigned16)388 pTOD->year=(uint16_t) 389 389 (DsReadClockRegister( 390 ( rtems_unsigned8)390 (uint8_t) 391 391 (unsigned long)&pCMOS->Century) 392 392 *100 + DsReadClockRegister(RTC_YEAR)); … … 444 444 */ 445 445 446 pNvRAM->CMOS.Year = ( rtems_unsigned8)Bin2BCD(pTOD->year%100);446 pNvRAM->CMOS.Year = (uint8_t)Bin2BCD(pTOD->year%100); 447 447 if(pTOD->year>=100) 448 448 { 449 pNvRAM->CMOS.Century=( rtems_unsigned8)449 pNvRAM->CMOS.Century=(uint8_t) 450 450 Bin2BCD(pTOD->year/100); 451 451 } 452 pNvRAM->CMOS.Month = ( rtems_unsigned8)Bin2BCD(pTOD->month);453 pNvRAM->CMOS.Date = ( rtems_unsigned8)Bin2BCD(pTOD->day);454 pNvRAM->CMOS.Day = ( rtems_unsigned8)(GregorianDay(pTOD) + 1);455 pNvRAM->CMOS.Hour = ( rtems_unsigned8)Bin2BCD(pTOD->hour);456 pNvRAM->CMOS.Minute = ( rtems_unsigned8)Bin2BCD(pTOD->minute);457 pNvRAM->CMOS.Second = ( rtems_unsigned8)Bin2BCD(pTOD->second);452 pNvRAM->CMOS.Month = (uint8_t)Bin2BCD(pTOD->month); 453 pNvRAM->CMOS.Date = (uint8_t)Bin2BCD(pTOD->day); 454 pNvRAM->CMOS.Day = (uint8_t)(GregorianDay(pTOD) + 1); 455 pNvRAM->CMOS.Hour = (uint8_t)Bin2BCD(pTOD->hour); 456 pNvRAM->CMOS.Minute = (uint8_t)Bin2BCD(pTOD->minute); 457 pNvRAM->CMOS.Second = (uint8_t)Bin2BCD(pTOD->second); 458 458 459 459 /* … … 505 505 */ 506 506 507 pTOD->year = ( rtems_unsigned16)(100*BCD2Bin(pNvRAM->CMOS.Century)+507 pTOD->year = (uint16_t)(100*BCD2Bin(pNvRAM->CMOS.Century)+ 508 508 BCD2Bin(pNvRAM->CMOS.Year)); 509 pTOD->month = ( rtems_unsigned8)BCD2Bin(pNvRAM->CMOS.Month);510 pTOD->day = ( rtems_unsigned8)BCD2Bin(pNvRAM->CMOS.Date);511 pTOD->hour = ( rtems_unsigned8)BCD2Bin(pNvRAM->CMOS.Hour);512 pTOD->minute = ( rtems_unsigned8)BCD2Bin(pNvRAM->CMOS.Minute);513 pTOD->second = ( rtems_unsigned8)BCD2Bin(pNvRAM->CMOS.Second);509 pTOD->month = (uint8_t)BCD2Bin(pNvRAM->CMOS.Month); 510 pTOD->day = (uint8_t)BCD2Bin(pNvRAM->CMOS.Date); 511 pTOD->hour = (uint8_t)BCD2Bin(pNvRAM->CMOS.Hour); 512 pTOD->minute = (uint8_t)BCD2Bin(pNvRAM->CMOS.Minute); 513 pTOD->second = (uint8_t)BCD2Bin(pNvRAM->CMOS.Second); 514 514 515 515 /* -
c/src/lib/libbsp/powerpc/ppcn_60x/universe/universe.c
r3f71ac1 rbad8092c 35 35 36 36 typedef struct { 37 rtems_unsigned32PCI_ID; /* Offset 0x0000 */38 rtems_unsigned32PCI_CSR; /* Offset 0x0004 */39 rtems_unsigned32PCI_CLASS; /* Offset 0x0008 */40 rtems_unsigned32PCI_MISC0; /* Offset 0x000C */41 rtems_unsigned32PCI_BS; /* Offset 0x0010 */42 rtems_unsigned32Buf_Offset_0x0014[ 0x0A ]; /* Offset 0x0014 */43 rtems_unsigned32PCI_MISC1; /* Offset 0x003C */44 rtems_unsigned32Buf_Offset_0x0040[ 0x30 ]; /* Offset 0x0040 */45 rtems_unsigned32LSI0_CTL; /* Offset 0x0100 */46 rtems_unsigned32LSI0_BS; /* Offset 0x0104 */47 rtems_unsigned32LSI0_BD; /* Offset 0x0108 */48 rtems_unsigned32LSI0_TO; /* Offset 0x010C */49 rtems_unsigned32Buf_Offset_0x0110; /* Offset 0x0110 */50 rtems_unsigned32LSI1_CTL; /* Offset 0x0114 */51 rtems_unsigned32LSI1_BS; /* Offset 0x0118 */52 rtems_unsigned32LSI1_BD; /* Offset 0x011C */53 rtems_unsigned32LSI1_TO; /* Offset 0x0120 */54 rtems_unsigned32Buf_Offset_0x0124; /* Offset 0x0124 */55 rtems_unsigned32LSI2_CTL; /* Offset 0x0128 */56 rtems_unsigned32LSI2_BS; /* Offset 0x012C */57 rtems_unsigned32LSI2_BD; /* Offset 0x0130 */58 rtems_unsigned32LSI2_TO; /* Offset 0x0134 */59 rtems_unsigned32Buf_Offset_0x0138; /* Offset 0x0138 */60 rtems_unsigned32LSI3_CTL; /* Offset 0x013C */61 rtems_unsigned32LSI3_BS; /* Offset 0x0140 */62 rtems_unsigned32LSI3_BD; /* Offset 0x0144 */63 rtems_unsigned32LSI3_TO; /* Offset 0x0148 */64 rtems_unsigned32Buf_Offset_0x014C[ 0x09 ]; /* Offset 0x014C */65 rtems_unsigned32SCYC_CTL; /* Offset 0x0170 */66 rtems_unsigned32SCYC_ADDR; /* Offset 0x0174 */67 rtems_unsigned32SCYC_EN; /* Offset 0x0178 */68 rtems_unsigned32SCYC_CMP; /* Offset 0x017C */69 rtems_unsigned32SCYC_SWP; /* Offset 0x0180 */70 rtems_unsigned32LMISC; /* Offset 0x0184 */71 rtems_unsigned32SLSI; /* Offset 0x0188 */72 rtems_unsigned32L_CMDERR; /* Offset 0x018C */73 rtems_unsigned32LAERR; /* Offset 0x0190 */74 rtems_unsigned32Buf_Offset_0x0194[ 0x1B ]; /* Offset 0x0194 */75 rtems_unsigned32DCTL; /* Offset 0x0200 */76 rtems_unsigned32DTBC; /* Offset 0x0204 */77 rtems_unsigned32DLA; /* Offset 0x0208 */78 rtems_unsigned32Buf_Offset_0x020C; /* Offset 0x020C */79 rtems_unsigned32DVA; /* Offset 0x0210 */80 rtems_unsigned32Buf_Offset_0x0214; /* Offset 0x0214 */81 rtems_unsigned32DCPP; /* Offset 0x0218 */82 rtems_unsigned32Buf_Offset_0x021C; /* Offset 0x021C */83 rtems_unsigned32DGCS; /* Offset 0x0220 */84 rtems_unsigned32D_LLUE; /* Offset 0x0224 */85 rtems_unsigned32Buf_Offset_0x0228[ 0x36 ]; /* Offset 0x0228 */86 rtems_unsigned32LINT_EN; /* Offset 0x0300 */87 rtems_unsigned32LINT_STAT; /* Offset 0x0304 */88 rtems_unsigned32LINT_MAP0; /* Offset 0x0308 */89 rtems_unsigned32LINT_MAP1; /* Offset 0x030C */90 rtems_unsigned32VINT_EN; /* Offset 0x0310 */91 rtems_unsigned32VINT_STAT; /* Offset 0x0314 */92 rtems_unsigned32VINT_MAP0; /* Offset 0x0318 */93 rtems_unsigned32VINT_MAP1; /* Offset 0x031C */94 rtems_unsigned32STATID; /* Offset 0x0320 */95 rtems_unsigned32V1_STATID; /* Offset 0x0324 */96 rtems_unsigned32V2_STATID; /* Offset 0x0328 */97 rtems_unsigned32V3_STATID; /* Offset 0x032C */98 rtems_unsigned32V4_STATID; /* Offset 0x0330 */99 rtems_unsigned32V5_STATID; /* Offset 0x0334 */100 rtems_unsigned32V6_STATID; /* Offset 0x0338 */101 rtems_unsigned32V7_STATID; /* Offset 0x033C */102 rtems_unsigned32Buf_Offset_0x0340[ 0x30 ]; /* Offset 0x0340 */103 rtems_unsigned32MAST_CTL; /* Offset 0x0400 */104 rtems_unsigned32MISC_CTL; /* Offset 0x0404 */105 rtems_unsigned32MISC_STAT; /* Offset 0x0408 */106 rtems_unsigned32USER_AM; /* Offset 0x040C */107 rtems_unsigned32Buf_Offset_0x0410[ 0x2bc ];/* Offset 0x0410 */108 rtems_unsigned32VSI0_CTL; /* Offset 0x0F00 */109 rtems_unsigned32VSI0_BS; /* Offset 0x0F04 */110 rtems_unsigned32VSI0_BD; /* Offset 0x0F08 */111 rtems_unsigned32VSI0_TO; /* Offset 0x0F0C */112 rtems_unsigned32Buf_Offset_0x0f10; /* Offset 0x0F10 */113 rtems_unsigned32VSI1_CTL; /* Offset 0x0F14 */114 rtems_unsigned32VSI1_BS; /* Offset 0x0F18 */115 rtems_unsigned32VSI1_BD; /* Offset 0x0F1C */116 rtems_unsigned32VSI1_TO; /* Offset 0x0F20 */117 rtems_unsigned32Buf_Offset_0x0F24; /* Offset 0x0F24 */118 rtems_unsigned32VSI2_CTL; /* Offset 0x0F28 */119 rtems_unsigned32VSI2_BS; /* Offset 0x0F2C */120 rtems_unsigned32VSI2_BD; /* Offset 0x0F30 */121 rtems_unsigned32VSI2_TO; /* Offset 0x0F34 */122 rtems_unsigned32Buf_Offset_0x0F38; /* Offset 0x0F38 */123 rtems_unsigned32VSI3_CTL; /* Offset 0x0F3C */124 rtems_unsigned32VSI3_BS; /* Offset 0x0F40 */125 rtems_unsigned32VSI3_BD; /* Offset 0x0F44 */126 rtems_unsigned32VSI3_TO; /* Offset 0x0F48 */127 rtems_unsigned32Buf_Offset_0x0F4C[ 0x9 ]; /* Offset 0x0F4C */128 rtems_unsigned32VRAI_CTL; /* Offset 0x0F70 */129 rtems_unsigned32VRAI_BS; /* Offset 0x0F74 */130 rtems_unsigned32Buf_Offset_0x0F78[ 0x2 ]; /* Offset 0x0F78 */131 rtems_unsigned32VCSR_CTL; /* Offset 0x0F80 */132 rtems_unsigned32VCSR_TO; /* Offset 0x0F84 */133 rtems_unsigned32V_AMERR; /* Offset 0x0F88 */134 rtems_unsigned32VAERR; /* Offset 0x0F8C */135 rtems_unsigned32Buf_Offset_0x0F90[ 0x19 ]; /* Offset 0x0F90 */136 rtems_unsigned32VCSR_CLR; /* Offset 0x0FF4 */137 rtems_unsigned32VCSR_SET; /* Offset 0x0FF8 */138 rtems_unsigned32VCSR_BS; /* Offset 0x0FFC */37 uint32_t PCI_ID; /* Offset 0x0000 */ 38 uint32_t PCI_CSR; /* Offset 0x0004 */ 39 uint32_t PCI_CLASS; /* Offset 0x0008 */ 40 uint32_t PCI_MISC0; /* Offset 0x000C */ 41 uint32_t PCI_BS; /* Offset 0x0010 */ 42 uint32_t Buf_Offset_0x0014[ 0x0A ]; /* Offset 0x0014 */ 43 uint32_t PCI_MISC1; /* Offset 0x003C */ 44 uint32_t Buf_Offset_0x0040[ 0x30 ]; /* Offset 0x0040 */ 45 uint32_t LSI0_CTL; /* Offset 0x0100 */ 46 uint32_t LSI0_BS; /* Offset 0x0104 */ 47 uint32_t LSI0_BD; /* Offset 0x0108 */ 48 uint32_t LSI0_TO; /* Offset 0x010C */ 49 uint32_t Buf_Offset_0x0110; /* Offset 0x0110 */ 50 uint32_t LSI1_CTL; /* Offset 0x0114 */ 51 uint32_t LSI1_BS; /* Offset 0x0118 */ 52 uint32_t LSI1_BD; /* Offset 0x011C */ 53 uint32_t LSI1_TO; /* Offset 0x0120 */ 54 uint32_t Buf_Offset_0x0124; /* Offset 0x0124 */ 55 uint32_t LSI2_CTL; /* Offset 0x0128 */ 56 uint32_t LSI2_BS; /* Offset 0x012C */ 57 uint32_t LSI2_BD; /* Offset 0x0130 */ 58 uint32_t LSI2_TO; /* Offset 0x0134 */ 59 uint32_t Buf_Offset_0x0138; /* Offset 0x0138 */ 60 uint32_t LSI3_CTL; /* Offset 0x013C */ 61 uint32_t LSI3_BS; /* Offset 0x0140 */ 62 uint32_t LSI3_BD; /* Offset 0x0144 */ 63 uint32_t LSI3_TO; /* Offset 0x0148 */ 64 uint32_t Buf_Offset_0x014C[ 0x09 ]; /* Offset 0x014C */ 65 uint32_t SCYC_CTL; /* Offset 0x0170 */ 66 uint32_t SCYC_ADDR; /* Offset 0x0174 */ 67 uint32_t SCYC_EN; /* Offset 0x0178 */ 68 uint32_t SCYC_CMP; /* Offset 0x017C */ 69 uint32_t SCYC_SWP; /* Offset 0x0180 */ 70 uint32_t LMISC; /* Offset 0x0184 */ 71 uint32_t SLSI; /* Offset 0x0188 */ 72 uint32_t L_CMDERR; /* Offset 0x018C */ 73 uint32_t LAERR; /* Offset 0x0190 */ 74 uint32_t Buf_Offset_0x0194[ 0x1B ]; /* Offset 0x0194 */ 75 uint32_t DCTL; /* Offset 0x0200 */ 76 uint32_t DTBC; /* Offset 0x0204 */ 77 uint32_t DLA; /* Offset 0x0208 */ 78 uint32_t Buf_Offset_0x020C; /* Offset 0x020C */ 79 uint32_t DVA; /* Offset 0x0210 */ 80 uint32_t Buf_Offset_0x0214; /* Offset 0x0214 */ 81 uint32_t DCPP; /* Offset 0x0218 */ 82 uint32_t Buf_Offset_0x021C; /* Offset 0x021C */ 83 uint32_t DGCS; /* Offset 0x0220 */ 84 uint32_t D_LLUE; /* Offset 0x0224 */ 85 uint32_t Buf_Offset_0x0228[ 0x36 ]; /* Offset 0x0228 */ 86 uint32_t LINT_EN; /* Offset 0x0300 */ 87 uint32_t LINT_STAT; /* Offset 0x0304 */ 88 uint32_t LINT_MAP0; /* Offset 0x0308 */ 89 uint32_t LINT_MAP1; /* Offset 0x030C */ 90 uint32_t VINT_EN; /* Offset 0x0310 */ 91 uint32_t VINT_STAT; /* Offset 0x0314 */ 92 uint32_t VINT_MAP0; /* Offset 0x0318 */ 93 uint32_t VINT_MAP1; /* Offset 0x031C */ 94 uint32_t STATID; /* Offset 0x0320 */ 95 uint32_t V1_STATID; /* Offset 0x0324 */ 96 uint32_t V2_STATID; /* Offset 0x0328 */ 97 uint32_t V3_STATID; /* Offset 0x032C */ 98 uint32_t V4_STATID; /* Offset 0x0330 */ 99 uint32_t V5_STATID; /* Offset 0x0334 */ 100 uint32_t V6_STATID; /* Offset 0x0338 */ 101 uint32_t V7_STATID; /* Offset 0x033C */ 102 uint32_t Buf_Offset_0x0340[ 0x30 ]; /* Offset 0x0340 */ 103 uint32_t MAST_CTL; /* Offset 0x0400 */ 104 uint32_t MISC_CTL; /* Offset 0x0404 */ 105 uint32_t MISC_STAT; /* Offset 0x0408 */ 106 uint32_t USER_AM; /* Offset 0x040C */ 107 uint32_t Buf_Offset_0x0410[ 0x2bc ];/* Offset 0x0410 */ 108 uint32_t VSI0_CTL; /* Offset 0x0F00 */ 109 uint32_t VSI0_BS; /* Offset 0x0F04 */ 110 uint32_t VSI0_BD; /* Offset 0x0F08 */ 111 uint32_t VSI0_TO; /* Offset 0x0F0C */ 112 uint32_t Buf_Offset_0x0f10; /* Offset 0x0F10 */ 113 uint32_t VSI1_CTL; /* Offset 0x0F14 */ 114 uint32_t VSI1_BS; /* Offset 0x0F18 */ 115 uint32_t VSI1_BD; /* Offset 0x0F1C */ 116 uint32_t VSI1_TO; /* Offset 0x0F20 */ 117 uint32_t Buf_Offset_0x0F24; /* Offset 0x0F24 */ 118 uint32_t VSI2_CTL; /* Offset 0x0F28 */ 119 uint32_t VSI2_BS; /* Offset 0x0F2C */ 120 uint32_t VSI2_BD; /* Offset 0x0F30 */ 121 uint32_t VSI2_TO; /* Offset 0x0F34 */ 122 uint32_t Buf_Offset_0x0F38; /* Offset 0x0F38 */ 123 uint32_t VSI3_CTL; /* Offset 0x0F3C */ 124 uint32_t VSI3_BS; /* Offset 0x0F40 */ 125 uint32_t VSI3_BD; /* Offset 0x0F44 */ 126 uint32_t VSI3_TO; /* Offset 0x0F48 */ 127 uint32_t Buf_Offset_0x0F4C[ 0x9 ]; /* Offset 0x0F4C */ 128 uint32_t VRAI_CTL; /* Offset 0x0F70 */ 129 uint32_t VRAI_BS; /* Offset 0x0F74 */ 130 uint32_t Buf_Offset_0x0F78[ 0x2 ]; /* Offset 0x0F78 */ 131 uint32_t VCSR_CTL; /* Offset 0x0F80 */ 132 uint32_t VCSR_TO; /* Offset 0x0F84 */ 133 uint32_t V_AMERR; /* Offset 0x0F88 */ 134 uint32_t VAERR; /* Offset 0x0F8C */ 135 uint32_t Buf_Offset_0x0F90[ 0x19 ]; /* Offset 0x0F90 */ 136 uint32_t VCSR_CLR; /* Offset 0x0FF4 */ 137 uint32_t VCSR_SET; /* Offset 0x0FF8 */ 138 uint32_t VCSR_BS; /* Offset 0x0FFC */ 139 139 } Universe_Memory; 140 140 … … 145 145 */ 146 146 void PCI_bus_write( 147 volatile rtems_unsigned32* _addr, /* IN */148 rtems_unsigned32_data /* IN */147 volatile uint32_t * _addr, /* IN */ 148 uint32_t _data /* IN */ 149 149 ) 150 150 { … … 152 152 } 153 153 154 rtems_unsigned32PCI_bus_read(155 volatile rtems_unsigned32* _addr /* IN */154 uint32_t PCI_bus_read( 155 volatile uint32_t * _addr /* IN */ 156 156 ) 157 157 { 158 rtems_unsigned32data;158 uint32_t data; 159 159 160 160 inport_32(_addr, data); … … 178 178 void InitializeUniverse() 179 179 { 180 rtems_unsigned32pci_id;181 rtems_unsigned32universe_temp_value;180 uint32_t pci_id; 181 uint32_t universe_temp_value; 182 182 183 183 /* … … 310 310 */ 311 311 void set_vme_base_address ( 312 rtems_unsigned32base_address312 uint32_t base_address 313 313 ) 314 314 { 315 volatile rtems_unsigned32temp;315 volatile uint32_t temp; 316 316 317 317 /* … … 342 342 * Gets the VME base address 343 343 */ 344 rtems_unsigned32get_vme_base_address ()344 uint32_t get_vme_base_address () 345 345 { 346 volatile rtems_unsigned32temp;346 volatile uint32_t temp; 347 347 348 348 temp = PCI_bus_read( &UNIVERSE->VSI0_BS ); … … 351 351 } 352 352 353 rtems_unsigned32get_vme_slave_size()353 uint32_t get_vme_slave_size() 354 354 { 355 volatile rtems_unsigned32temp;355 volatile uint32_t temp; 356 356 temp = PCI_bus_read( &UNIVERSE->VSI0_BD); 357 357 temp &= 0xFFFFF000; … … 364 364 * Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF) 365 365 */ 366 void set_vme_slave_size ( rtems_unsigned32size)366 void set_vme_slave_size (uint32_t size) 367 367 { 368 volatile rtems_unsigned32temp;368 volatile uint32_t temp; 369 369 370 370 if (size<0) … … 392 392 * pointer to VME D16 space 393 393 */ 394 rtems_unsigned16get_vme(395 rtems_unsigned16*vme_ptr394 uint16_t get_vme( 395 uint16_t *vme_ptr 396 396 ) 397 397 { 398 rtems_unsigned16result;399 400 if (vme_ptr > ( rtems_unsigned16*)0x3EFFFFFF)398 uint16_t result; 399 400 if (vme_ptr > (uint16_t*)0x3EFFFFFF) 401 401 { 402 402 /* … … 406 406 PCI_bus_write( &UNIVERSE->LSI0_TO, 0x3EFFF000 ); 407 407 408 result = (*( rtems_unsigned16*)(409 (( rtems_unsigned32)vme_ptr - 0x3EFFF000)+408 result = (*(uint16_t*)( 409 ((uint32_t)vme_ptr - 0x3EFFF000)+ 410 410 PPCN_60X_PCI_MEM_BASE) ); 411 411 } 412 412 else 413 result = (*( rtems_unsigned16*)414 (( rtems_unsigned32)vme_ptr+PPCN_60X_PCI_MEM_BASE));413 result = (*(uint16_t*) 414 ((uint32_t)vme_ptr+PPCN_60X_PCI_MEM_BASE)); 415 415 416 416 return result; … … 422 422 */ 423 423 void put_vme( 424 rtems_unsigned16*vme_ptr,425 rtems_unsigned16value424 uint16_t *vme_ptr, 425 uint16_t value 426 426 ) 427 427 { 428 428 429 if (vme_ptr > ( rtems_unsigned16*)0x3EFFFFFF) {429 if (vme_ptr > (uint16_t*)0x3EFFFFFF) { 430 430 /* 431 431 * LSI0_TO register to 0x3EFFF000 if it had not been updated already … … 434 434 PCI_bus_write( &UNIVERSE->LSI0_TO, 0x3EFFF000 ); 435 435 436 *( rtems_unsigned16 *) (((rtems_unsigned32)vme_ptr - 0x3EFFF000) +436 *(uint16_t*) (((uint32_t)vme_ptr - 0x3EFFF000) + 437 437 PPCN_60X_PCI_MEM_BASE) = value; 438 438 } 439 439 else 440 *( rtems_unsigned16 *)((rtems_unsigned32)vme_ptr +440 *(uint16_t*)((uint32_t)vme_ptr + 441 441 PPCN_60X_PCI_MEM_BASE) = value; 442 442 }
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