Changeset ba938b8 in rtems for c/src/lib/libbsp/arm/lpc24xx/ssp


Ignore:
Timestamp:
Sep 18, 2009, 8:05:40 AM (11 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, 5, master
Children:
091705c
Parents:
f90c5fb
Message:

Changes throughout.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/lpc24xx/ssp/ssp.c

    rf90c5fb rba938b8  
    22 * @file
    33 *
    4  * @ingroup lpc24xx
     4 * @ingroup lpc24xx_libi2c
    55 *
    66 * @brief LibI2C bus driver for the Synchronous Serial Port (SSP).
     
    7575static uint32_t lpc24xx_ssp_trash = 0;
    7676
    77 static inline bool lpc24xx_ssp_is_busy( const lpc24xx_ssp_bus_entry *bus)
     77static inline bool lpc24xx_ssp_is_busy(const lpc24xx_ssp_bus_entry *bus)
    7878{
    7979  return lpc24xx_ssp_dma_data.bus == bus
     
    8181}
    8282
    83 static void lpc24xx_ssp_handler( rtems_vector_number vector, void *arg)
     83static void lpc24xx_ssp_handler(rtems_vector_number vector, void *arg)
    8484{
    8585  lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) arg;
     
    8888  uint32_t icr = 0;
    8989
    90   if (IS_FLAG_SET( mis, SSP_MIS_RORRIS)) {
     90  if (IS_FLAG_SET(mis, SSP_MIS_RORRIS)) {
    9191    /* TODO */
    92     printk( "%s: Receiver overrun!\n", __func__);
     92    printk("%s: Receiver overrun!\n", __func__);
    9393    icr |= SSP_ICR_RORRIS;
    9494  }
     
    9797}
    9898
    99 static void lpc24xx_ssp_dma_handler( rtems_vector_number vector, void *arg)
     99static void lpc24xx_ssp_dma_handler(rtems_vector_number vector, void *arg)
    100100{
    101101  lpc24xx_ssp_dma_entry *e = (lpc24xx_ssp_dma_entry *) arg;
     
    106106
    107107  /* Return if we are not in a transfer status */
    108   if (IS_FLAG_CLEARED( status, LPC24XX_SSP_DMA_TRANSFER_FLAG)) {
     108  if (IS_FLAG_CLEARED(status, LPC24XX_SSP_DMA_TRANSFER_FLAG)) {
    109109    return;
    110110  }
     
    122122    switch (status) {
    123123      case LPC24XX_SSP_DMA_WAIT:
    124         if (ARE_FLAGS_SET( tc, GPDMA_STATUS_CH_0 | GPDMA_STATUS_CH_1)) {
     124        if (ARE_FLAGS_SET(tc, GPDMA_STATUS_CH_0 | GPDMA_STATUS_CH_1)) {
    125125          status = LPC24XX_SSP_DMA_DONE;
    126         } else if (IS_FLAG_SET( tc, GPDMA_STATUS_CH_0)) {
     126        } else if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_0)) {
    127127          status = LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_1;
    128         } else if (IS_FLAG_SET( tc, GPDMA_STATUS_CH_1)) {
     128        } else if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_1)) {
    129129          status = LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_0;
    130130        }
    131131        break;
    132132      case LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_0:
    133         if (IS_FLAG_SET( tc, GPDMA_STATUS_CH_1)) {
     133        if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_1)) {
    134134          status = LPC24XX_SSP_DMA_ERROR;
    135         } else if (IS_FLAG_SET( tc, GPDMA_STATUS_CH_0)) {
     135        } else if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_0)) {
    136136          status = LPC24XX_SSP_DMA_DONE;
    137137        }
    138138        break;
    139139      case LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_1:
    140         if (IS_FLAG_SET( tc, GPDMA_STATUS_CH_0)) {
     140        if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_0)) {
    141141          status = LPC24XX_SSP_DMA_ERROR;
    142         } else if (IS_FLAG_SET( tc, GPDMA_STATUS_CH_1)) {
     142        } else if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_1)) {
    143143          status = LPC24XX_SSP_DMA_DONE;
    144144        }
     
    154154  /* Error cleanup */
    155155  if (status == LPC24XX_SSP_DMA_ERROR) {
    156     lpc24xx_dma_channel_disable( 0, true);
    157     lpc24xx_dma_channel_disable( 1, true);
     156    lpc24xx_dma_channel_disable(0, true);
     157    lpc24xx_dma_channel_disable(1, true);
    158158    status = LPC24XX_SSP_DMA_DONE;
    159159    rv = -RTEMS_IO_ERROR;
     
    164164    status = LPC24XX_SSP_DMA_AVAILABLE;
    165165    if (e->done != NULL) {
    166       e->done( rv, e->n, e->arg);
     166      e->done(rv, e->n, e->arg);
    167167      e->done = NULL;
    168168    }
     
    173173}
    174174
    175 static rtems_status_code lpc24xx_ssp_init( rtems_libi2c_bus_t *bus)
     175static rtems_status_code lpc24xx_ssp_init(rtems_libi2c_bus_t *bus)
    176176{
    177177  rtems_status_code sc = RTEMS_SUCCESSFUL;
     
    188188
    189189    /* Test and set DMA support status */
    190     rtems_interrupt_disable( level);
     190    rtems_interrupt_disable(level);
    191191    status = lpc24xx_ssp_dma_data.status;
    192192    if (status == LPC24XX_SSP_DMA_NOT_INITIALIZED) {
    193193      lpc24xx_ssp_dma_data.status = LPC24XX_SSP_DMA_INITIALIZATION;
    194194    }
    195     rtems_interrupt_enable( level);
     195    rtems_interrupt_enable(level);
    196196
    197197    if (status == LPC24XX_SSP_DMA_NOT_INITIALIZED) {
     
    204204        &lpc24xx_ssp_dma_data
    205205      );
    206       RTEMS_CHECK_SC( sc, "Install DMA interrupt handler");
     206      RTEMS_CHECK_SC(sc, "install DMA interrupt handler");
    207207
    208208      /* Set DMA support status */
     
    217217  switch ((uintptr_t) regs) {
    218218    case SSP0_BASE_ADDR:
    219       rtems_interrupt_disable( level);
    220       PCLKSEL1 = SET_PCLKSEL1_PCLK_SSP0( PCLKSEL1, 1);
    221       rtems_interrupt_enable( level);
     219      rtems_interrupt_disable(level);
     220      PCLKSEL1 = SET_PCLKSEL1_PCLK_SSP0(PCLKSEL1, 1);
     221      rtems_interrupt_enable(level);
    222222
    223223      vector = LPC24XX_IRQ_SPI_SSP_0;
    224224      break;
    225225    case SSP1_BASE_ADDR:
    226       rtems_interrupt_disable( level);
    227       PCLKSEL0 = SET_PCLKSEL0_PCLK_SSP1( PCLKSEL0, 1);
    228       rtems_interrupt_enable( level);
     226      rtems_interrupt_disable(level);
     227      PCLKSEL0 = SET_PCLKSEL0_PCLK_SSP1(PCLKSEL0, 1);
     228      rtems_interrupt_enable(level);
    229229
    230230      vector = LPC24XX_IRQ_SSP_1;
     
    235235
    236236  /* Set serial clock rate to save value */
    237   regs->cr0 = SET_SSP_CR0_SCR( 0, 255);
     237  regs->cr0 = SET_SSP_CR0_SCR(0, 255);
    238238
    239239  /* Set clock prescaler */
     
    259259    e
    260260  );
    261   RTEMS_CHECK_SC( sc, "Install interrupt handler");
     261  RTEMS_CHECK_SC(sc, "install interrupt handler");
    262262
    263263  /* Enable receiver overrun interrupts */
     
    267267}
    268268
    269 static rtems_status_code lpc24xx_ssp_send_start( rtems_libi2c_bus_t *bus)
     269static rtems_status_code lpc24xx_ssp_send_start(rtems_libi2c_bus_t *bus)
    270270{
    271271  return RTEMS_SUCCESSFUL;
    272272}
    273273
    274 static rtems_status_code lpc24xx_ssp_send_stop( rtems_libi2c_bus_t *bus)
     274static rtems_status_code lpc24xx_ssp_send_stop(rtems_libi2c_bus_t *bus)
    275275{
    276276  lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) bus;
     
    279279  if (lpc24xx_ssp_dma_data.bus == e) {
    280280    if (lpc24xx_ssp_dma_data.status == LPC24XX_SSP_DMA_AVAILABLE) {
    281       lpc24xx_dma_channel_release( 0);
    282       lpc24xx_dma_channel_release( 1);
     281      lpc24xx_dma_channel_release(0);
     282      lpc24xx_dma_channel_release(1);
    283283      lpc24xx_ssp_dma_data.bus = NULL;
    284284    } else {
     
    298298  lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) bus;
    299299
    300   if (lpc24xx_ssp_is_busy( e)) {
     300  if (lpc24xx_ssp_is_busy(e)) {
    301301    return RTEMS_RESOURCE_IN_USE;
    302302  }
     
    316316  unsigned scr = (clk + br - 1) / br;
    317317
    318   if (lpc24xx_ssp_is_busy( e)) {
     318  if (lpc24xx_ssp_is_busy(e)) {
    319319    return -RTEMS_RESOURCE_IN_USE;
    320320  }
     
    364364  e->idle_char = mode->idle_char;
    365365
    366   while (IS_FLAG_CLEARED( regs->sr, SSP_SR_TFE)) {
     366  while (IS_FLAG_CLEARED(regs->sr, SSP_SR_TFE)) {
    367367    /* Wait */
    368368  }
    369369
    370   regs->cr0 = SET_SSP_CR0_DSS( 0, 0x7)
    371     | SET_SSP_CR0_SCR( 0, scr)
     370  regs->cr0 = SET_SSP_CR0_DSS(0, 0x7)
     371    | SET_SSP_CR0_SCR(0, scr)
    372372    | (mode->clock_inv ? SSP_CR0_CPOL : 0)
    373373    | (mode->clock_phs ? SSP_CR0_CPHA : 0);
     
    394394  unsigned char idle_char = (unsigned char) e->idle_char;
    395395
    396   if (lpc24xx_ssp_is_busy( e)) {
     396  if (lpc24xx_ssp_is_busy(e)) {
    397397    return -RTEMS_RESOURCE_IN_USE;
    398398  }
     
    427427
    428428    /* Write */
    429     if (IS_FLAG_SET( sr, SSP_SR_TNF) && m < LPC24XX_SSP_FIFO_SIZE) {
     429    if (IS_FLAG_SET(sr, SSP_SR_TNF) && m < LPC24XX_SSP_FIFO_SIZE) {
    430430      regs->dr = *out;
    431431      ++w;
     
    434434
    435435    /* Read */
    436     if (IS_FLAG_SET( sr, SSP_SR_RNE)) {
     436    if (IS_FLAG_SET(sr, SSP_SR_RNE)) {
    437437      *in = (unsigned char) regs->dr;
    438438      ++r;
     
    449449    do {
    450450      sr = regs->sr;
    451     } while (IS_FLAG_CLEARED( sr, SSP_SR_RNE));
     451    } while (IS_FLAG_CLEARED(sr, SSP_SR_RNE));
    452452
    453453    /* Read */
     
    473473  lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) bus;
    474474  volatile lpc24xx_ssp *ssp = e->regs;
    475   volatile lpc24xx_dma_channel *receive_channel = GPDMA_CH_BASE_ADDR( 0);
    476   volatile lpc24xx_dma_channel *transmit_channel = GPDMA_CH_BASE_ADDR( 1);
     475  volatile lpc24xx_dma_channel *receive_channel = GPDMA_CH_BASE_ADDR(0);
     476  volatile lpc24xx_dma_channel *transmit_channel = GPDMA_CH_BASE_ADDR(1);
    477477  uint32_t di = GPDMA_CH_CTRL_DI;
    478478  uint32_t si = GPDMA_CH_CTRL_SI;
     
    484484  /* Try to reserve DMA support for this bus */
    485485  if (lpc24xx_ssp_dma_data.bus == NULL) {
    486     rtems_interrupt_disable( level);
     486    rtems_interrupt_disable(level);
    487487    if (lpc24xx_ssp_dma_data.bus == NULL) {
    488488      lpc24xx_ssp_dma_data.bus = e;
    489489    }
    490     rtems_interrupt_enable( level);
     490    rtems_interrupt_enable(level);
    491491
    492492    /* Try to obtain DMA channels */
    493493    if (lpc24xx_ssp_dma_data.bus == e) {
    494       bool channel_0 = lpc24xx_dma_channel_obtain( 0);
    495       bool channel_1 = lpc24xx_dma_channel_obtain( 1);
    496 
    497       if (!channel_0 && channel_1) {
    498         lpc24xx_dma_channel_release( 1);
    499         lpc24xx_ssp_dma_data.bus = NULL;
    500       } else if (channel_0 && !channel_1) {
    501         lpc24xx_dma_channel_release( 0);
    502         lpc24xx_ssp_dma_data.bus = NULL;
    503       } else if (!channel_0 || !channel_1) {
     494      rtems_status_code cs0 = lpc24xx_dma_channel_obtain(0);
     495      rtems_status_code cs1 = lpc24xx_dma_channel_obtain(1);
     496
     497      if (cs0 != RTEMS_SUCCESSFUL || cs1 != RTEMS_SUCCESSFUL) {
     498        if (cs0 == RTEMS_SUCCESSFUL) {
     499          lpc24xx_dma_channel_release(0);
     500        }
     501        if (cs1 == RTEMS_SUCCESSFUL) {
     502          lpc24xx_dma_channel_release(1);
     503        }
    504504        lpc24xx_ssp_dma_data.bus = NULL;
    505505      }
     
    524524  /* Receive */
    525525  if (in != NULL) {
    526     receive_channel->dest = (uint32_t) in;
     526    receive_channel->desc.dest = (uint32_t) in;
    527527  } else {
    528     receive_channel->dest = (uint32_t) &lpc24xx_ssp_trash;
     528    receive_channel->desc.dest = (uint32_t) &lpc24xx_ssp_trash;
    529529    di = 0;
    530530  }
    531   receive_channel->src = (uint32_t) &ssp->dr;
    532   receive_channel->lli = 0;
    533   receive_channel->ctrl = SET_GPDMA_CH_CTRL_TSZ( 0, n)
    534     | SET_GPDMA_CH_CTRL_SBSZ( 0, GPDMA_CH_CTRL_BSZ_4)
    535     | SET_GPDMA_CH_CTRL_DBSZ( 0, GPDMA_CH_CTRL_BSZ_4)
    536     | SET_GPDMA_CH_CTRL_SW( 0, GPDMA_CH_CTRL_W_8)
    537     | SET_GPDMA_CH_CTRL_DW( 0, GPDMA_CH_CTRL_W_8)
     531  receive_channel->desc.src = (uint32_t) &ssp->dr;
     532  receive_channel->desc.lli = 0;
     533  receive_channel->desc.ctrl = SET_GPDMA_CH_CTRL_TSZ(0, n)
     534    | SET_GPDMA_CH_CTRL_SBSZ(0, GPDMA_CH_CTRL_BSZ_4)
     535    | SET_GPDMA_CH_CTRL_DBSZ(0, GPDMA_CH_CTRL_BSZ_4)
     536    | SET_GPDMA_CH_CTRL_SW(0, GPDMA_CH_CTRL_W_8)
     537    | SET_GPDMA_CH_CTRL_DW(0, GPDMA_CH_CTRL_W_8)
    538538    | GPDMA_CH_CTRL_ITC
    539539    | di;
    540   receive_channel->cfg = SET_GPDMA_CH_CFG_SRCPER( 0, GPDMA_CH_CFG_PER_SSP1_RX)
    541     | SET_GPDMA_CH_CFG_FLOW( 0, GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA)
     540  receive_channel->cfg = SET_GPDMA_CH_CFG_SRCPER(0, GPDMA_CH_CFG_PER_SSP1_RX)
     541    | SET_GPDMA_CH_CFG_FLOW(0, GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA)
    542542    | GPDMA_CH_CFG_IE
    543543    | GPDMA_CH_CFG_ITC
     
    546546  /* Transmit */
    547547  if (out != NULL) {
    548     transmit_channel->src = (uint32_t) out;
     548    transmit_channel->desc.src = (uint32_t) out;
    549549  } else {
    550     transmit_channel->src = (uint32_t) &e->idle_char;
     550    transmit_channel->desc.src = (uint32_t) &e->idle_char;
    551551    si = 0;
    552552  }
    553   transmit_channel->dest = (uint32_t) &ssp->dr;
    554   transmit_channel->lli = 0;
    555   transmit_channel->ctrl = SET_GPDMA_CH_CTRL_TSZ( 0, n)
    556     | SET_GPDMA_CH_CTRL_SBSZ( 0, GPDMA_CH_CTRL_BSZ_4)
    557     | SET_GPDMA_CH_CTRL_DBSZ( 0, GPDMA_CH_CTRL_BSZ_4)
    558     | SET_GPDMA_CH_CTRL_SW( 0, GPDMA_CH_CTRL_W_8)
    559     | SET_GPDMA_CH_CTRL_DW( 0, GPDMA_CH_CTRL_W_8)
     553  transmit_channel->desc.dest = (uint32_t) &ssp->dr;
     554  transmit_channel->desc.lli = 0;
     555  transmit_channel->desc.ctrl = SET_GPDMA_CH_CTRL_TSZ(0, n)
     556    | SET_GPDMA_CH_CTRL_SBSZ(0, GPDMA_CH_CTRL_BSZ_4)
     557    | SET_GPDMA_CH_CTRL_DBSZ(0, GPDMA_CH_CTRL_BSZ_4)
     558    | SET_GPDMA_CH_CTRL_SW(0, GPDMA_CH_CTRL_W_8)
     559    | SET_GPDMA_CH_CTRL_DW(0, GPDMA_CH_CTRL_W_8)
    560560    | GPDMA_CH_CTRL_ITC
    561561    | si;
    562   transmit_channel->cfg = SET_GPDMA_CH_CFG_DESTPER( 0, GPDMA_CH_CFG_PER_SSP1_TX)
    563     | SET_GPDMA_CH_CFG_FLOW( 0, GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA)
     562  transmit_channel->cfg = SET_GPDMA_CH_CFG_DESTPER(0, GPDMA_CH_CFG_PER_SSP1_TX)
     563    | SET_GPDMA_CH_CFG_FLOW(0, GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA)
    564564    | GPDMA_CH_CFG_IE
    565565    | GPDMA_CH_CFG_ITC
     
    569569}
    570570
    571 static int lpc24xx_ssp_read( rtems_libi2c_bus_t *bus, unsigned char *in, int n)
    572 {
    573   return lpc24xx_ssp_read_write( bus, in, NULL, n);
     571static int lpc24xx_ssp_read(rtems_libi2c_bus_t *bus, unsigned char *in, int n)
     572{
     573  return lpc24xx_ssp_read_write(bus, in, NULL, n);
    574574}
    575575
     
    580580)
    581581{
    582   return lpc24xx_ssp_read_write( bus, NULL, out, n);
    583 }
    584 
    585 static int lpc24xx_ssp_ioctl( rtems_libi2c_bus_t *bus, int cmd, void *arg)
     582  return lpc24xx_ssp_read_write(bus, NULL, out, n);
     583}
     584
     585static int lpc24xx_ssp_ioctl(rtems_libi2c_bus_t *bus, int cmd, void *arg)
    586586{
    587587  int rv = -1;
     
    593593  switch (cmd) {
    594594    case RTEMS_LIBI2C_IOCTL_READ_WRITE:
    595       rv = lpc24xx_ssp_read_write( bus, rw->rd_buf, rw->wr_buf, rw->byte_cnt);
     595      rv = lpc24xx_ssp_read_write(bus, rw->rd_buf, rw->wr_buf, rw->byte_cnt);
    596596      break;
    597597    case RTEMS_LIBI2C_IOCTL_READ_WRITE_ASYNC:
     
    606606      break;
    607607    case RTEMS_LIBI2C_IOCTL_SET_TFRMODE:
    608       rv = lpc24xx_ssp_set_transfer_mode( bus, tm);
     608      rv = lpc24xx_ssp_set_transfer_mode(bus, tm);
    609609      break;
    610610    default:
     
    631631    .bus = {
    632632      .ops = &lpc24xx_ssp_ops,
    633       .size = sizeof( lpc24xx_ssp_bus_entry)
     633      .size = sizeof(lpc24xx_ssp_bus_entry)
    634634    },
    635635    .regs = (volatile lpc24xx_ssp *) SSP0_BASE_ADDR,
     
    640640    .bus = {
    641641      .ops = &lpc24xx_ssp_ops,
    642       .size = sizeof( lpc24xx_ssp_bus_entry)
     642      .size = sizeof(lpc24xx_ssp_bus_entry)
    643643    },
    644644    .regs = (volatile lpc24xx_ssp *) SSP1_BASE_ADDR,
Note: See TracChangeset for help on using the changeset viewer.