Changeset ba938b8 in rtems


Ignore:
Timestamp:
Sep 18, 2009, 8:05:40 AM (10 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, master
Children:
091705c
Parents:
f90c5fb
Message:

Changes throughout.

Location:
c/src/lib/libbsp/arm/lpc24xx
Files:
19 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/lpc24xx/ChangeLog

    rf90c5fb rba938b8  
     12009-09-17      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * startup/bspstarthooks.c, misc/dma-copy.c, misc/timer.c: New files.
     4        * Makefile.am, configure.ac, i2c/i2c.c, include/bsp.h, include/dma.h,
     5        include/i2c.h, include/io.h, include/irq.h, include/lpc24xx.h,
     6        include/ssp.h, include/system-clocks.h, irq/irq.c, misc/bspidle.c,
     7        misc/dma.c, misc/io.c, misc/system-clocks.c, network/network.c,
     8        ssp/ssp.c, startup/bspstart.c: Changes throughout.
     9
    1102009-09-15      Ralf Corsépius <ralf.corsepius@rtems.org>
    211
  • c/src/lib/libbsp/arm/lpc24xx/Makefile.am

    rf90c5fb rba938b8  
    9191        ../../shared/src/irq-info.c \
    9292        ../../shared/src/irq-shell.c \
     93        ../../shared/src/irq-server.c \
    9394        irq/irq.c
    9495
     
    104105libbsp_a_SOURCES += ../../shared/tod.c \
    105106        rtc/rtc-config.c
    106 # Timer
    107 libbsp_a_SOURCES += ../../shared/timerstub.c
    108107
    109108# Misc
    110109libbsp_a_SOURCES += misc/system-clocks.c \
    111110        misc/dma.c \
     111        misc/dma-copy.c \
    112112        misc/bspidle.c \
    113         misc/io.c
     113        misc/io.c \
     114        misc/timer.c
    114115
    115116# SSP
     
    118119# I2C
    119120libbsp_a_SOURCES += i2c/i2c.c
     121
     122# Start hooks (FIXME: This is brittle.)
     123libbsp_a_SOURCES += startup/bspstarthooks.c
     124bspstarthooks.o: startup/bspstarthooks.c
     125        $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS:-mthumb=) \
     126        -MT bspstarthooks.o -MD -MP -MF $(DEPDIR)/bspstarthooks.Tpo -c -o bspstarthooks.o \
     127        `test -f 'startup/bspstarthooks.c' || echo '$(srcdir)/'`startup/bspstarthooks.c
    120128
    121129###############################################################################
  • c/src/lib/libbsp/arm/lpc24xx/i2c/i2c.c

    rf90c5fb rba938b8  
    22 * @file
    33 *
    4  * @ingroup lpc24xx
     4 * @ingroup lpc24xx_libi2c
    55 *
    6  * LibI2C bus driver for the I2C modules.
     6 * @brief LibI2C bus driver for the I2C modules.
    77 */
    88
  • c/src/lib/libbsp/arm/lpc24xx/include/bsp.h

    rf90c5fb rba938b8  
    44 * @ingroup lpc24xx
    55 *
    6  * @brief Global BSP variables and functions.
     6 * @brief Global BSP definitions.
    77 */
    88
     
    3636#ifndef ASM
    3737
    38 /* Network driver configuration */
    39 
    4038struct rtems_bsdnet_ifconfig;
    4139
     40/**
     41 * @defgroup lpc24xx LPC24XX Support
     42 *
     43 * @ingroup bsp_kit
     44 *
     45 * @brief LPC24XX support package.
     46 *
     47 * @{
     48 */
     49
     50/**
     51 * @brief Network driver attach and detach function.
     52 */
    4253int lpc24xx_eth_attach_detach(
    4354  struct rtems_bsdnet_ifconfig *config,
     
    4556);
    4657
     58/**
     59 * @brief Standard network driver attach and detach function.
     60 */
    4761#define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc24xx_eth_attach_detach
    4862
     63/**
     64 * @brief Standard network driver name.
     65 */
    4966#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
    5067
    51 /*
    52  *  BSP specific idle thread
     68/**
     69 * @brief Optimized idle task.
     70 *
     71 * This idle task sets the power mode to idle.  This causes the processor clock
     72 * to be stopped, while on-chip peripherals remain active.  Any enabled
     73 * interrupt from a peripheral or an external interrupt source will cause the
     74 * processor to resume execution.
     75 *
     76 * To enable the idle task use the following in the system configuration:
     77 *
     78 * @code
     79 * #include <bsp.h>
     80 *
     81 * #define CONFIGURE_INIT
     82 *
     83 * #define CONFIGURE_IDLE_TASK_BODY lpc24xx_idle
     84 *
     85 * #include <confdefs.h>
     86 * @endcode
    5387 */
    54 void *bsp_idle_thread( uint32_t ignored);
     88void *lpc24xx_idle(uintptr_t ignored);
    5589
    56 #define BSP_IDLE_TASK_BODY bsp_idle_thread
     90/** @} */
    5791
    5892#endif /* ASM */
  • c/src/lib/libbsp/arm/lpc24xx/include/dma.h

    rf90c5fb rba938b8  
    22 * @file
    33 *
    4  * @ingroup lpc24xx
     4 * @ingroup lpc24xx_dma
    55 *
    6  * @brief DMA support.
     6 * @brief Direct memory access (DMA) support.
    77 */
    88
     
    1313 * D-82178 Puchheim
    1414 * Germany
    15  * rtems@embedded-brains.de
     15 * <rtems@embedded-brains.de>
    1616 *
    17  * The license and distribution terms for this file may be found in the file
    18  * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
     17 * The license and distribution terms for this file may be
     18 * found in the file LICENSE in this distribution or at
     19 * http://www.rtems.com/license/LICENSE.
    1920 */
    2021
     
    2829#endif /* __cplusplus */
    2930
     31/**
     32 * @defgroup lpc24xx_dma DMA Support
     33 *
     34 * @ingroup lpc24xx
     35 *
     36 * @brief Direct memory access (DMA) support.
     37 *
     38 * @{
     39 */
     40
     41/**
     42 * @brief Initializes the general purpose DMA.
     43 */
    3044void lpc24xx_dma_initialize(void);
    3145
     46/**
     47 * @brief Tries to obtain the DMA channel @a channel.
     48 *
     49 * @retval RTEMS_SUCCESSFUL Successful operation.
     50 * @retval RTEMS_INVALID_ID Invalid channel number.
     51 * @retval RTEMS_RESOURCE_IN_USE Channel already occupied.
     52 */
    3253rtems_status_code lpc24xx_dma_channel_obtain(unsigned channel);
    3354
     55/**
     56 * @brief Releases the DMA channel @a channel.
     57 *
     58 * You must have obtained this channel with lpc24xx_dma_channel_obtain()
     59 * previously.
     60 *
     61 * If the channel number @a channel is out of range nothing will happen.
     62 */
    3463void lpc24xx_dma_channel_release(unsigned channel);
    3564
     65/**
     66 * @brief Disables the DMA channel @a channel.
     67 *
     68 * If @a force is @c false the channel will be halted and disabled when the
     69 * channel is inactive otherwise it will be disabled immediately.
     70 *
     71 * If the channel number @a channel is out of range nothing will happen.
     72 */
    3673void lpc24xx_dma_channel_disable(unsigned channel, bool force);
     74
     75rtems_status_code lpc24xx_dma_copy_initialize(void);
     76
     77rtems_status_code lpc24xx_dma_copy_release(void);
     78
     79rtems_status_code lpc24xx_dma_copy(
     80  unsigned channel,
     81  void *dest,
     82  const void *src,
     83  size_t n,
     84  size_t width
     85);
     86
     87rtems_status_code lpc24xx_dma_copy_wait(unsigned channel);
     88
     89/** @} */
    3790
    3891#ifdef __cplusplus
  • c/src/lib/libbsp/arm/lpc24xx/include/i2c.h

    rf90c5fb rba938b8  
    22 * @file
    33 *
    4  * @ingroup lpc24xx
     4 * @ingroup lpc24xx_libi2c
    55 *
    6  * LibI2C bus driver for the I2C modules.
     6 * @brief LibI2C bus driver for the I2C modules.
    77 */
    88
     
    2929#endif /* __cplusplus */
    3030
     31/**
     32 * @defgroup lpc24xx_libi2c LPC24XX Bus Drivers
     33 *
     34 * @ingroup libi2c
     35 *
     36 * @brief LibI2C bus drivers for LPC24XX.
     37 *
     38 * @{
     39 */
     40
    3141extern rtems_libi2c_bus_t * const lpc24xx_i2c_0;
    3242
     
    3545extern rtems_libi2c_bus_t * const lpc24xx_i2c_2;
    3646
     47/** @} */
     48
    3749#ifdef __cplusplus
    3850}
  • c/src/lib/libbsp/arm/lpc24xx/include/io.h

    rf90c5fb rba938b8  
    22 * @file
    33 *
    4  * @ingroup lpc24xx
     4 * @ingroup lpc24xx_io
    55 *
    6  * Input and output module.
     6 * @brief Input and output module.
    77 */
    88
     
    3030extern "C" {
    3131#endif /* __cplusplus */
     32
     33/**
     34 * @defgroup lpc24xx_io IO Support and Configuration
     35 *
     36 * @ingroup lpc24xx
     37 *
     38 * @brief Input and output module.
     39 *
     40 * @{
     41 */
    3242
    3343#define LPC24XX_IO_PORT_COUNT 5U
     
    6575  LPC24XX_MODULE_USB,
    6676  LPC24XX_MODULE_WDT,
    67   LPC24XX_MODULE_NUMBER
     77  LPC24XX_MODULE_COUNT
    6878} lpc24xx_module;
    6979
     
    160170}
    161171
     172/** @} */
     173
    162174#ifdef __cplusplus
    163175}
  • c/src/lib/libbsp/arm/lpc24xx/include/irq.h

    rf90c5fb rba938b8  
    6767#define LPC24XX_IRQ_I2S 31
    6868
    69 #define LPC24XX_IRQ_PRIORITY_VALUE_MIN 0
    70 #define LPC24XX_IRQ_PRIORITY_VALUE_MAX 15
     69#define LPC24XX_IRQ_PRIORITY_VALUE_MIN 0U
     70#define LPC24XX_IRQ_PRIORITY_VALUE_MAX 15U
    7171
    7272/**
  • c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h

    rf90c5fb rba938b8  
    22 * @file
    33 *
    4  * @ingroup lpc24xx
     4 * @ingroup lpc24xx_regs
    55 *
    66 * @brief Register definitions.
     
    2525
    2626#include <bsp/utility.h>
     27
     28/**
     29 * @defgroup lpc24xx_regs Register Definitions
     30 *
     31 * @ingroup lpc24xx
     32 *
     33 * @brief Register definitions.
     34 *
     35 * @{
     36 */
    2737
    2838/* Vectored Interrupt Controller (VIC) */
     
    459469
    460470/* static RAM access registers */
     471#define EMC_STA_BASE_0    ((uint32_t *) (EMC_BASE_ADDR + 0x200))
    461472#define EMC_STA_CFG0      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x200))
    462473#define EMC_STA_WAITWEN0  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x204))
     
    467478#define EMC_STA_WAITTURN0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x218))
    468479
     480#define EMC_STA_BASE_1    ((uint32_t *) (EMC_BASE_ADDR + 0x220))
    469481#define EMC_STA_CFG1      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x220))
    470482#define EMC_STA_WAITWEN1  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x224))
     
    475487#define EMC_STA_WAITTURN1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x238))
    476488
     489#define EMC_STA_BASE_2    ((uint32_t *) (EMC_BASE_ADDR + 0x240))
    477490#define EMC_STA_CFG2      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x240))
    478491#define EMC_STA_WAITWEN2  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x244))
     
    483496#define EMC_STA_WAITTURN2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x258))
    484497
     498#define EMC_STA_BASE_3    ((uint32_t *) (EMC_BASE_ADDR + 0x260))
    485499#define EMC_STA_CFG3      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x260))
    486500#define EMC_STA_WAITWEN3  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x264))
     
    16471661  uint32_t lli;
    16481662  uint32_t ctrl;
     1663} lpc24xx_dma_descriptor;
     1664
     1665typedef struct {
     1666  lpc24xx_dma_descriptor desc;
    16491667  uint32_t cfg;
    16501668} lpc24xx_dma_channel;
     
    20872105
    20882106#define EMC_DYN_CTRL_CMD_NOP 0x00000180U
     2107
     2108typedef struct {
     2109  uint32_t cfg;
     2110  uint32_t waitwen;
     2111  uint32_t waitoen;
     2112  uint32_t waitrd;
     2113  uint32_t waitpage;
     2114  uint32_t waitwr;
     2115  uint32_t waitrun;
     2116} lpc24xx_emc_static;
    20892117
    20902118/* I2C */
     
    21212149} lpc24xx_fio;
    21222150
    2123 static volatile uint32_t * const LPC24XX_PINSEL = &PINSEL0;
    2124 
    2125 static volatile uint32_t * const LPC24XX_PINMODE = &PINMODE0;
    2126 
    2127 static volatile lpc24xx_fio * const LPC24XX_FIO = (volatile lpc24xx_fio *) FIO_BASE_ADDR;
     2151#define LPC24XX_PINSEL ((volatile uint32_t *) &PINSEL0)
     2152
     2153#define LPC24XX_PINMODE ((volatile uint32_t *) &PINMODE0)
     2154
     2155#define LPC24XX_FIO ((volatile lpc24xx_fio *) FIO_BASE_ADDR)
     2156
     2157/** @} */
    21282158
    21292159#endif /* LIBBSP_ARM_LPC24XX_LPC24XX_H */
  • c/src/lib/libbsp/arm/lpc24xx/include/ssp.h

    rf90c5fb rba938b8  
    22 * @file
    33 *
    4  * @ingroup lpc24xx
     4 * @ingroup lpc24xx_libi2c
    55 *
    66 * @brief LibI2C bus driver for the Synchronous Serial Port (SSP).
     
    2828#endif /* __cplusplus */
    2929
     30/**
     31 * @ingroup lpc24xx_libi2c
     32 *
     33 * @{
     34 */
     35
    3036extern rtems_libi2c_bus_t * const lpc24xx_ssp_0;
    3137
    3238extern rtems_libi2c_bus_t * const lpc24xx_ssp_1;
     39
     40/** @} */
    3341
    3442#ifdef __cplusplus
  • c/src/lib/libbsp/arm/lpc24xx/include/system-clocks.h

    rf90c5fb rba938b8  
    22 * @file
    33 *
    4  * @ingroup lpc24xx
     4 * @ingroup lpc24xx_clocks
    55 *
    66 * @brief System clocks.
     
    88
    99/*
    10  * Copyright (c) 2008
    11  * Embedded Brains GmbH
     10 * Copyright (c) 2008, 2009
     11 * embedded brains GmbH
    1212 * Obere Lagerstr. 30
    1313 * D-82178 Puchheim
    1414 * Germany
    15  * rtems@embedded-brains.de
     15 * <rtems@embedded-brains.de>
    1616 *
    17  * The license and distribution terms for this file may be found in the file
    18  * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
     17 * The license and distribution terms for this file may be
     18 * found in the file LICENSE in this distribution or at
     19 * http://www.rtems.com/license/LICENSE.
    1920 */
    2021
     
    2223#define LIBBSP_ARM_LPC24XX_SYSTEM_CLOCKS_H
    2324
     25#include <bsp/lpc24xx.h>
     26
    2427#ifdef __cplusplus
    2528extern "C" {
    2629#endif /* __cplusplus */
    2730
    28 void lpc24xx_micro_seconds_delay( unsigned us);
     31/**
     32 * @defgroup lpc24xx_clock System Clocks
     33 *
     34 * @ingroup lpc24xx
     35 *
     36 * @brief System clocks.
     37 *
     38 * @{
     39 */
    2940
    30 unsigned lpc24xx_pllclk( void);
     41/**
     42 * @brief Initializes the standard timer.
     43 *
     44 * This function uses Timer 1.
     45 */
     46void lpc24xx_timer_initialize(void);
    3147
    32 unsigned lpc24xx_cclk( void);
     48/**
     49 * @brief Returns current standard timer value in CPU clocks.
     50 *
     51 * This function uses Timer 1.
     52 */
     53static inline unsigned lpc24xx_timer(void)
     54{
     55  return T1TC;
     56}
    3357
    34 void lpc24xx_set_pll( unsigned clksrc, unsigned nsel, unsigned msel, unsigned cclksel);
     58/**
     59 * @brief Delay for @a us micro seconds.
     60 *
     61 * This function uses the standard timer and assumes that the CPU frequency is
     62 * in whole MHz numbers.  The delay value @a us will be converted to CPU ticks
     63 * and there is no protection against integer overflows.
     64 *
     65 * This function uses Timer 1.
     66 */
     67void lpc24xx_micro_seconds_delay(unsigned us);
     68
     69/**
     70 * @brief Returns the PLL output clock frequency in [Hz].
     71 *
     72 * Returns zero in case of an unexpected PLL input frequency.
     73 */
     74unsigned lpc24xx_pllclk(void);
     75
     76/**
     77 * @brief Returns the CPU clock frequency in [Hz].
     78 *
     79 * Returns zero in case of an unexpected PLL input frequency.
     80 */
     81unsigned lpc24xx_cclk(void);
     82
     83/** @} */
    3584
    3685#ifdef __cplusplus
  • c/src/lib/libbsp/arm/lpc24xx/irq/irq.c

    rf90c5fb rba938b8  
    4545    return VICVectPriorityBase [vector];
    4646  } else {
    47     return LPC24XX_IRQ_PRIORITY_VALUE_MIN - 1;
     47    return LPC24XX_IRQ_PRIORITY_VALUE_MIN - 1U;
    4848  }
    4949}
  • c/src/lib/libbsp/arm/lpc24xx/misc/bspidle.c

    rf90c5fb rba938b8  
    2525#include <bsp/lpc24xx.h>
    2626
    27 void *bsp_idle_thread(uint32_t ignored)
     27void *bsp_idle_thread(uintptr_t ignored)
    2828{
    2929  while (true) {
  • c/src/lib/libbsp/arm/lpc24xx/misc/dma.c

    rf90c5fb rba938b8  
    22 * @file
    33 *
    4  * @ingroup lpc24xx
     4 * @ingroup lpc24xx_dma
    55 *
    6  * @brief DMA support.
     6 * @brief Direct memory access (DMA) support.
    77 */
    88
     
    1313 * D-82178 Puchheim
    1414 * Germany
    15  * rtems@embedded-brains.de
     15 * <rtems@embedded-brains.de>
    1616 *
    17  * The license and distribution terms for this file may be found in the file
    18  * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
     17 * The license and distribution terms for this file may be
     18 * found in the file LICENSE in this distribution or at
     19 * http://www.rtems.com/license/LICENSE.
    1920 */
    2021
     
    3031static bool lpc24xx_dma_channel_occupation [GPDMA_CH_NUMBER];
    3132
    32 /**
    33  * @brief Initializes the general purpose DMA.
    34  */
    3533void lpc24xx_dma_initialize(void)
    3634{
     
    5856}
    5957
    60 /**
    61  * @brief Tries to obtain the channel @a channel.
    62  *
    63  * @retval RTEMS_SUCCESSFUL Successful operation.
    64  * @retval RTEMS_INVALID_ID Invalid channel number.
    65  * @retval RTEMS_RESOURCE_IN_USE Channel already occupied.
    66  */
    6758rtems_status_code lpc24xx_dma_channel_obtain(unsigned channel)
    6859{
     
    8273}
    8374
    84 /**
    85  * @brief Releases the channel @a channel.
    86  *
    87  * You must have obtained this channel with lpc24xx_dma_channel_obtain()
    88  * previously.
    89  *
    90  * If the channel number @a channel is out of range nothing will happen.
    91  */
    9275void lpc24xx_dma_channel_release(unsigned channel)
    9376{
     
    9780}
    9881
    99 /**
    100  * @brief Disables the channel @a channel.
    101  *
    102  * If @a force is false the channel will be halted and disabled when the
    103  * channel is inactive.
    104  *
    105  * If the channel number @a channel is out of range the behaviour is undefined.
    106  */
    10782void lpc24xx_dma_channel_disable(unsigned channel, bool force)
    10883{
    109   volatile lpc24xx_dma_channel *ch = GPDMA_CH_BASE_ADDR(channel);
    110   uint32_t cfg = ch->cfg;
    111 
    112   if (!force) {
    113     /* Halt */
    114     ch->cfg = SET_FLAG(cfg, GPDMA_CH_CFG_HALT);
    115 
    116     /* Wait for inactive */
    117     do {
    118       cfg = ch->cfg;
    119     } while (IS_FLAG_SET(cfg, GPDMA_CH_CFG_ACTIVE));
     84  if (channel < GPDMA_CH_NUMBER) {
     85    volatile lpc24xx_dma_channel *ch = GPDMA_CH_BASE_ADDR(channel);
     86    uint32_t cfg = ch->cfg;
     87 
     88    if (!force) {
     89      /* Halt */
     90      ch->cfg = SET_FLAG(cfg, GPDMA_CH_CFG_HALT);
     91 
     92      /* Wait for inactive */
     93      do {
     94        cfg = ch->cfg;
     95      } while (IS_FLAG_SET(cfg, GPDMA_CH_CFG_ACTIVE));
     96    }
     97 
     98    /* Disable */
     99    ch->cfg = CLEAR_FLAG(cfg, GPDMA_CH_CFG_EN);
    120100  }
    121 
    122   /* Disable */
    123   ch->cfg = CLEAR_FLAG(cfg, GPDMA_CH_CFG_EN);
    124101}
  • c/src/lib/libbsp/arm/lpc24xx/misc/io.c

    rf90c5fb rba938b8  
    22 * @file
    33 *
    4  * @ingroup lpc24xx
     4 * @ingroup lpc24xx_io
    55 *
    6  * Input and output module.
     6 * @brief Input and output module.
    77 */
    88
     
    2121
    2222#include <bsp/io.h>
    23 
    24 #define LPC24XX_IO_SELECT( index) (index >> 4U)
    25 
    26 #define LPC24XX_IO_SELECT_SHIFT( index) ((index & 0xfU) << 1U)
     23#include <bsp/system-clocks.h>
     24
     25#define LPC24XX_IO_SELECT(pin) (pin >> 4U)
     26
     27#define LPC24XX_IO_SELECT_SHIFT(pin) ((pin & 0xfU) << 1U)
    2728
    2829#define LPC24XX_IO_SELECT_MASK 0x3U
     
    3637#define LPC24XX_IO_ALTERNATE_2 0x3U
    3738
    38 #define LPC24XX_IO_HEADER_FLAG 0x80U
    39 
    40 #define LPC24XX_IO_ENTRY( b, e, f) \
    41   { .function = f, .begin = b, .end = e }
    42 
    43 #define LPC24XX_IO_HEADER( module, index, config) \
    44   { .function = config | LPC24XX_IO_HEADER_FLAG, .begin = module, .end = index }
    45 
    46 typedef struct  __attribute__ ((__packed__)) {
    47   unsigned char function;
    48   unsigned char begin;
    49   unsigned char end;
     39#define LPC24XX_IO_ENTRY(mod, idx, cfg, begin_port, begin_index, last_port, last_index, function) \
     40  { \
     41    .module = mod, \
     42    .index = idx, \
     43    .config = cfg, \
     44    .pin_begin = LPC24XX_IO_INDEX_BY_PORT(begin_port, begin_index), \
     45    .pin_last = LPC24XX_IO_INDEX_BY_PORT(last_port, last_index), \
     46    .pin_function = function \
     47  }
     48
     49typedef struct {
     50  unsigned module : 5;
     51  unsigned index : 4;
     52  unsigned config : 4;
     53  unsigned pin_begin : 8;
     54  unsigned pin_last : 8;
     55  unsigned pin_function : 3;
    5056} lpc24xx_io_entry;
    5157
    52 typedef void (*lpc24xx_io_iterate_routine)( unsigned /* index */, unsigned /* function */);
     58typedef void (*lpc24xx_io_iterate_routine)(unsigned /* pin */, unsigned /* function */);
    5359
    5460static const lpc24xx_io_entry lpc24xx_io_config_table [] = {
    55   /* EMC */
    56   LPC24XX_IO_HEADER( LPC24XX_MODULE_EMC, 0, 0),
    57   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 2, 16), LPC24XX_IO_INDEX_BY_PORT( 2, 22), LPC24XX_IO_ALTERNATE_0),
    58   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 2, 24), LPC24XX_IO_INDEX_BY_PORT( 2, 26), LPC24XX_IO_ALTERNATE_0),
    59   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 2, 26), LPC24XX_IO_INDEX_BY_PORT( 2, 30), LPC24XX_IO_ALTERNATE_0),
    60   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 3, 0), LPC24XX_IO_INDEX_BY_PORT( 3, 16), LPC24XX_IO_ALTERNATE_0),
    61   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 4, 0), LPC24XX_IO_INDEX_BY_PORT( 4, 28), LPC24XX_IO_ALTERNATE_0),
    62   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 4, 30), LPC24XX_IO_INDEX_BY_PORT( 5, 0), LPC24XX_IO_ALTERNATE_0),
    63 
    6461  /* UART */
    65   LPC24XX_IO_HEADER( LPC24XX_MODULE_UART, 0, 0),
    66   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 0, 2), LPC24XX_IO_INDEX_BY_PORT( 0, 4), LPC24XX_IO_ALTERNATE_0),
    67   LPC24XX_IO_HEADER( LPC24XX_MODULE_UART, 1, 0),
    68   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 0, 15), LPC24XX_IO_INDEX_BY_PORT( 0, 17), LPC24XX_IO_ALTERNATE_1),
    69   LPC24XX_IO_HEADER( LPC24XX_MODULE_UART, 1, 1),
    70   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 2, 0), LPC24XX_IO_INDEX_BY_PORT( 2, 2), LPC24XX_IO_ALTERNATE_2),
    71   LPC24XX_IO_HEADER( LPC24XX_MODULE_UART, 1, 2),
    72   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 3, 16), LPC24XX_IO_INDEX_BY_PORT( 3, 18), LPC24XX_IO_ALTERNATE_1),
    73   LPC24XX_IO_HEADER( LPC24XX_MODULE_UART, 2, 0),
    74   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 0, 10), LPC24XX_IO_INDEX_BY_PORT( 0, 12), LPC24XX_IO_ALTERNATE_1),
    75   LPC24XX_IO_HEADER( LPC24XX_MODULE_UART, 2, 1),
    76   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 2, 8), LPC24XX_IO_INDEX_BY_PORT( 2, 10), LPC24XX_IO_ALTERNATE_1),
    77   LPC24XX_IO_HEADER( LPC24XX_MODULE_UART, 2, 2),
    78   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 4, 22), LPC24XX_IO_INDEX_BY_PORT( 4, 24), LPC24XX_IO_ALTERNATE_1),
    79   LPC24XX_IO_HEADER( LPC24XX_MODULE_UART, 3, 0),
    80   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 0, 0), LPC24XX_IO_INDEX_BY_PORT( 0, 2), LPC24XX_IO_ALTERNATE_2),
    81   LPC24XX_IO_HEADER( LPC24XX_MODULE_UART, 3, 1),
    82   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 0, 25), LPC24XX_IO_INDEX_BY_PORT( 0, 27), LPC24XX_IO_ALTERNATE_2),
    83   LPC24XX_IO_HEADER( LPC24XX_MODULE_UART, 3, 2),
    84   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 4, 28), LPC24XX_IO_INDEX_BY_PORT( 4, 30), LPC24XX_IO_ALTERNATE_2),
     62  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 0, 0, 0, 2, 0, 3, LPC24XX_IO_ALTERNATE_0),
     63  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 1, 0, 0, 15, 0, 16, LPC24XX_IO_ALTERNATE_1),
     64  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 1, 1, 2, 0, 2, 1, LPC24XX_IO_ALTERNATE_2),
     65  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 1, 2, 3, 16, 3, 17, LPC24XX_IO_ALTERNATE_1),
     66  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 2, 0, 0, 10, 0, 11, LPC24XX_IO_ALTERNATE_1),
     67  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 2, 1, 2, 8, 2, 9, LPC24XX_IO_ALTERNATE_1),
     68  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 2, 2, 4, 22, 4, 23, LPC24XX_IO_ALTERNATE_1),
     69  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 3, 0, 0, 0, 0, 1, LPC24XX_IO_ALTERNATE_2),
     70  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 3, 1, 0, 25, 0, 26, LPC24XX_IO_ALTERNATE_2),
     71  LPC24XX_IO_ENTRY(LPC24XX_MODULE_UART, 3, 2, 4, 28, 4, 29, LPC24XX_IO_ALTERNATE_2),
    8572
    8673  /* Ethernet */
    87   LPC24XX_IO_HEADER( LPC24XX_MODULE_ETHERNET, 0, 0),
    88   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 1, 0), LPC24XX_IO_INDEX_BY_PORT( 1, 18), LPC24XX_IO_ALTERNATE_0),
    89   LPC24XX_IO_HEADER( LPC24XX_MODULE_ETHERNET, 0, 1),
    90   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 1, 0), LPC24XX_IO_INDEX_BY_PORT( 1, 2), LPC24XX_IO_ALTERNATE_0),
    91   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 1, 4), LPC24XX_IO_INDEX_BY_PORT( 1, 5), LPC24XX_IO_ALTERNATE_0),
    92   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 1, 8), LPC24XX_IO_INDEX_BY_PORT( 1, 11), LPC24XX_IO_ALTERNATE_0),
    93   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 1, 14), LPC24XX_IO_INDEX_BY_PORT( 1, 18), LPC24XX_IO_ALTERNATE_0),
     74  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 0, 0, 1, 0, 1, 17, LPC24XX_IO_ALTERNATE_0),
     75  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 0, 1, 1, 0, 1, 1, LPC24XX_IO_ALTERNATE_0),
     76  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 0, 1, 1, 4, 1, 4, LPC24XX_IO_ALTERNATE_0),
     77  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 0, 1, 1, 8, 1, 10, LPC24XX_IO_ALTERNATE_0),
     78  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ETHERNET, 0, 1, 1, 14, 1, 17, LPC24XX_IO_ALTERNATE_0),
    9479
    9580  /* ADC */
    96   LPC24XX_IO_HEADER( LPC24XX_MODULE_ADC, 0, 0),
    97   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 0, 12), LPC24XX_IO_INDEX_BY_PORT( 0, 14), LPC24XX_IO_ALTERNATE_2),
     81  LPC24XX_IO_ENTRY(LPC24XX_MODULE_ADC, 0, 0, 0, 12, 0, 13, LPC24XX_IO_ALTERNATE_2),
    9882
    9983  /* I2C */
    100   LPC24XX_IO_HEADER( LPC24XX_MODULE_I2C, 0, 0),
    101   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 0, 27), LPC24XX_IO_INDEX_BY_PORT( 0, 29), LPC24XX_IO_ALTERNATE_0),
    102   LPC24XX_IO_HEADER( LPC24XX_MODULE_I2C, 1, 0),
    103   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 0, 0), LPC24XX_IO_INDEX_BY_PORT( 0, 2), LPC24XX_IO_ALTERNATE_2),
    104   LPC24XX_IO_HEADER( LPC24XX_MODULE_I2C, 1, 1),
    105   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 0, 19), LPC24XX_IO_INDEX_BY_PORT( 0, 21), LPC24XX_IO_ALTERNATE_2),
    106   LPC24XX_IO_HEADER( LPC24XX_MODULE_I2C, 1, 2),
    107   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 2, 14), LPC24XX_IO_INDEX_BY_PORT( 2, 16), LPC24XX_IO_ALTERNATE_2),
    108   LPC24XX_IO_HEADER( LPC24XX_MODULE_I2C, 2, 0),
    109   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 0, 10), LPC24XX_IO_INDEX_BY_PORT( 0, 12), LPC24XX_IO_ALTERNATE_1),
    110   LPC24XX_IO_HEADER( LPC24XX_MODULE_I2C, 2, 1),
    111   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 2, 30), LPC24XX_IO_INDEX_BY_PORT( 3, 0), LPC24XX_IO_ALTERNATE_2),
    112   LPC24XX_IO_HEADER( LPC24XX_MODULE_I2C, 2, 2),
    113   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 4, 20), LPC24XX_IO_INDEX_BY_PORT( 4, 22), LPC24XX_IO_ALTERNATE_1),
     84  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 0, 0, 0, 27, 0, 28, LPC24XX_IO_ALTERNATE_0),
     85  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 1, 0, 0, 0, 0, 1, LPC24XX_IO_ALTERNATE_2),
     86  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 1, 1, 0, 19, 0, 20, LPC24XX_IO_ALTERNATE_2),
     87  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 1, 2, 2, 14, 2, 15, LPC24XX_IO_ALTERNATE_2),
     88  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 2, 0, 0, 10, 0, 11, LPC24XX_IO_ALTERNATE_1),
     89  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 2, 1, 2, 30, 2, 31, LPC24XX_IO_ALTERNATE_2),
     90  LPC24XX_IO_ENTRY(LPC24XX_MODULE_I2C, 2, 2, 4, 20, 4, 21, LPC24XX_IO_ALTERNATE_1),
     91
     92  /* SSP */
     93  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 0, 0, 0, 15, 0, 18, LPC24XX_IO_ALTERNATE_1),
     94  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 0, 1, 1, 20, 0, 21, LPC24XX_IO_ALTERNATE_2),
     95  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 0, 1, 1, 23, 0, 24, LPC24XX_IO_ALTERNATE_2),
     96  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 0, 2, 2, 22, 2, 23, LPC24XX_IO_ALTERNATE_2),
     97  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 0, 2, 2, 26, 2, 27, LPC24XX_IO_ALTERNATE_2),
     98  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 1, 0, 0, 6, 0, 9, LPC24XX_IO_ALTERNATE_1),
     99  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 1, 1, 0, 12, 0, 13, LPC24XX_IO_ALTERNATE_1),
     100  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 1, 1, 0, 14, 0, 14, LPC24XX_IO_ALTERNATE_2),
     101  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 1, 1, 1, 31, 1, 31, LPC24XX_IO_ALTERNATE_1),
     102  LPC24XX_IO_ENTRY(LPC24XX_MODULE_SSP, 1, 2, 4, 20, 4, 23, LPC24XX_IO_ALTERNATE_2),
    114103
    115104  /* USB */
    116   LPC24XX_IO_HEADER( LPC24XX_MODULE_USB, 0, 0),
    117   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 0, 29), LPC24XX_IO_INDEX_BY_PORT( 0, 31), LPC24XX_IO_ALTERNATE_0),
    118   LPC24XX_IO_ENTRY( LPC24XX_IO_INDEX_BY_PORT( 1, 19), LPC24XX_IO_INDEX_BY_PORT( 1, 20), LPC24XX_IO_ALTERNATE_1),
     105  LPC24XX_IO_ENTRY(LPC24XX_MODULE_USB, 0, 0, 0, 29, 0, 30, LPC24XX_IO_ALTERNATE_0),
     106  LPC24XX_IO_ENTRY(LPC24XX_MODULE_USB, 0, 0, 1, 19, 1, 19, LPC24XX_IO_ALTERNATE_1),
     107
     108  /* Terminate */
     109  LPC24XX_IO_ENTRY(LPC24XX_MODULE_COUNT, 0, 0, 0, 0, 0, 0, 0),
    119110};
    120111
    121 static size_t lpc24xx_io_get_entry_index( lpc24xx_module module, unsigned index, unsigned config)
    122 {
    123   size_t i = 0;
    124 
    125   config |= LPC24XX_IO_HEADER_FLAG;
    126 
    127   for (i = 0; i < sizeof( lpc24xx_io_config_table); ++i) {
    128     const lpc24xx_io_entry *e = lpc24xx_io_config_table + i;
    129 
    130     if (e->function == config && e->begin == module && e->end == index) {
    131       return i + 1;
     112static rtems_status_code lpc24xx_io_iterate(
     113  lpc24xx_module module,
     114  unsigned index,
     115  unsigned config,
     116  lpc24xx_io_iterate_routine routine
     117)
     118{
     119  rtems_status_code sc = RTEMS_INVALID_ID;
     120  const lpc24xx_io_entry *e = &lpc24xx_io_config_table [0];
     121
     122  while (e->module != LPC24XX_MODULE_COUNT) {
     123    if (e->module == module && e->index == index && e->config == config) {
     124      unsigned pin = e->pin_begin;
     125      unsigned last = e->pin_last;
     126      unsigned function = e->pin_function;
     127
     128      while (pin <= last) {
     129        (*routine)(pin, function);
     130
     131        ++pin;
     132      }
     133
     134      sc = RTEMS_SUCCESSFUL;
    132135    }
    133   }
    134 
    135   return (size_t) -1;
    136 }
    137 
    138 static void lpc24xx_io_do_config( unsigned index, unsigned function)
     136    ++e;
     137  }
     138
     139  return sc;
     140}
     141
     142static void lpc24xx_io_do_config(unsigned pin, unsigned function)
    139143{
    140144  rtems_interrupt_level level;
    141   unsigned select = LPC24XX_IO_SELECT( index);
    142   unsigned shift = LPC24XX_IO_SELECT_SHIFT( index);
    143 
    144   rtems_interrupt_disable( level);
     145  unsigned select = LPC24XX_IO_SELECT(pin);
     146  unsigned shift = LPC24XX_IO_SELECT_SHIFT(pin);
     147
     148  rtems_interrupt_disable(level);
    145149
    146150  LPC24XX_PINSEL [select] =
     
    148152      | ((function & LPC24XX_IO_SELECT_MASK) << shift);
    149153
    150   rtems_interrupt_flash( level);
     154  rtems_interrupt_flash(level);
    151155
    152156  LPC24XX_PINMODE [select] &= ~(LPC24XX_IO_SELECT_MASK << shift);
    153157
    154   rtems_interrupt_enable( level);
    155 }
    156 
    157 static void lpc24xx_io_do_release( unsigned index, unsigned function)
     158  rtems_interrupt_enable(level);
     159}
     160
     161static void lpc24xx_io_do_release(unsigned pin, unsigned function)
    158162{
    159163  rtems_interrupt_level level;
    160   unsigned select = LPC24XX_IO_SELECT( index);
    161   unsigned shift = LPC24XX_IO_SELECT_SHIFT( index);
    162 
    163   rtems_interrupt_disable( level);
     164  unsigned select = LPC24XX_IO_SELECT(pin);
     165  unsigned shift = LPC24XX_IO_SELECT_SHIFT(pin);
     166
     167  rtems_interrupt_disable(level);
    164168  LPC24XX_PINSEL [select] =
    165169    (LPC24XX_PINSEL [select] & ~(LPC24XX_IO_SELECT_MASK << shift));
    166   rtems_interrupt_enable( level);
    167 }
    168 
    169 static rtems_status_code lpc24xx_io_iterate(
    170   lpc24xx_module module,
    171   unsigned index,
    172   unsigned config,
    173   lpc24xx_io_iterate_routine routine
    174 )
    175 {
    176   size_t i = lpc24xx_io_get_entry_index( module, index, config);
    177 
    178   if (i != (size_t) -1) {
    179     const lpc24xx_io_entry * const table_end = lpc24xx_io_config_table
    180       + sizeof( lpc24xx_io_config_table) / sizeof( lpc24xx_io_config_table [0]);
    181     const lpc24xx_io_entry *e = lpc24xx_io_config_table + i;
    182 
    183     while (e != table_end && (e->function & LPC24XX_IO_HEADER_FLAG) == 0) {
    184       unsigned j = e->begin;
    185       unsigned end = e->end;
    186       unsigned function = e->function;
    187 
    188       while (j < end) {
    189         routine( j, function);
    190 
    191         ++j;
    192       }
    193 
    194       ++e;
    195     }
    196   } else {
    197     return RTEMS_INVALID_ID;
    198   }
    199 
    200   return RTEMS_SUCCESSFUL;
     170  rtems_interrupt_enable(level);
    201171}
    202172
     
    207177)
    208178{
    209   return lpc24xx_io_iterate( module, index, config, lpc24xx_io_do_config);
     179  return lpc24xx_io_iterate(module, index, config, lpc24xx_io_do_config);
    210180}
    211181
     
    216186)
    217187{
    218   return lpc24xx_io_iterate( module, index, config, lpc24xx_io_do_release);
     188  return lpc24xx_io_iterate(module, index, config, lpc24xx_io_do_release);
    219189}
    220190
    221191rtems_status_code lpc24xx_gpio_config(
    222   unsigned index,
     192  unsigned pin,
    223193  lpc24xx_gpio_settings settings
    224194)
    225195{
    226   if (index <= LPC24XX_IO_INDEX_MAX) {
     196  if (pin <= LPC24XX_IO_INDEX_MAX) {
    227197    rtems_interrupt_level level;
    228     unsigned port = LPC24XX_IO_PORT( index);
    229     unsigned bit = LPC24XX_IO_PORT_BIT( index);
    230     unsigned select = LPC24XX_IO_SELECT( index);
    231     unsigned shift = LPC24XX_IO_SELECT_SHIFT( index);
     198    unsigned port = LPC24XX_IO_PORT(pin);
     199    unsigned bit = LPC24XX_IO_PORT_BIT(pin);
     200    unsigned select = LPC24XX_IO_SELECT(pin);
     201    unsigned shift = LPC24XX_IO_SELECT_SHIFT(pin);
    232202    unsigned resistor = settings & LPC24XX_GPIO_RESISTOR_MASK;
    233203    unsigned output = (settings & LPC24XX_GPIO_OUTPUT) != 0 ? 1U : 0U;
     
    249219    }
    250220
    251     rtems_interrupt_disable( level);
     221    rtems_interrupt_disable(level);
    252222
    253223    /* Resistor */
     
    256226        | ((resistor & LPC24XX_IO_SELECT_MASK) << shift);
    257227
    258     rtems_interrupt_flash( level);
     228    rtems_interrupt_flash(level);
    259229
    260230    /* Input or output */
     
    262232      (LPC24XX_FIO [port].dir & ~(1U << bit)) | (output << bit);
    263233
    264     rtems_interrupt_enable( level);
     234    rtems_interrupt_enable(level);
    265235  } else {
    266236    return RTEMS_INVALID_ID;
     
    446416    rtems_interrupt_level level;
    447417
    448     rtems_interrupt_disable( level);
     418    rtems_interrupt_disable(level);
    449419    PCONP |= 1U << power_bit;
    450     rtems_interrupt_enable( level);
     420    rtems_interrupt_enable(level);
    451421
    452422    if (module != LPC24XX_MODULE_USB) {
    453       rtems_interrupt_disable( level);
     423      rtems_interrupt_disable(level);
    454424      if (clock_shift < 32U) {
    455425        PCLKSEL0 = (PCLKSEL0 & ~(LPC24XX_MODULE_CLOCK_MASK << clock_shift))
     
    460430            | (clock << clock_shift);
    461431      }
    462       rtems_interrupt_enable( level);
     432      rtems_interrupt_enable(level);
    463433    } else {
    464434      unsigned pllclk = lpc24xx_pllclk();
     
    474444    rtems_interrupt_level level;
    475445
    476     rtems_interrupt_disable( level);
     446    rtems_interrupt_disable(level);
    477447    PCONP &= ~(1U << power_bit);
    478     rtems_interrupt_enable( level);
     448    rtems_interrupt_enable(level);
    479449  }
    480450
     
    488458)
    489459{
    490   return lpc24xx_module_do_enable( module, index, clock, true);
     460  return lpc24xx_module_do_enable(module, index, clock, true);
    491461}
    492462
     
    496466)
    497467{
    498   return lpc24xx_module_do_enable( module, index, 0U, false);
    499 }
     468  return lpc24xx_module_do_enable(module, index, 0U, false);
     469}
  • c/src/lib/libbsp/arm/lpc24xx/misc/system-clocks.c

    rf90c5fb rba938b8  
    22 * @file
    33 *
    4  * @ingroup lpc24xx
     4 * @ingroup lpc24xx_clocks
    55 *
    66 * @brief System clocks.
     
    3737#endif
    3838
    39 /**
    40  * @brief Delay for @a us micro seconds.
    41  *
    42  * @note Uses Timer 1.
    43  */
    44 void lpc24xx_micro_seconds_delay( unsigned us)
     39void lpc24xx_timer_initialize(void)
    4540{
    46   /* Stop and reset timer */
    47   T1TCR = 0x02;
     41  /* Reset timer */
     42  T1TCR = TCR_RST;
     43
     44  /* Set timer mode */
     45  T1CTCR = 0;
    4846
    4947  /* Set prescaler to zero */
    50   T1PR = 0x00;
    51  
    52   /* Set match value */
    53   T1MR0 = (uint32_t) ((uint64_t) 4000000 * (uint64_t) us / (uint64_t) lpc24xx_cclk()) + 1;
     48  T1PR = 0;
    5449
    5550  /* Reset all interrupt flags */
    5651  T1IR = 0xff;
    5752
    58   /* Stop timer on match */
    59   T1MCR = 0x04;
     53  /* Do not stop on a match */
     54  T1MCR = 0;
     55
     56  /* No captures */
     57  T1CCR = 0;
    6058
    6159  /* Start timer */
    62   T1TCR = 0x01;
    63  
    64   /* Wait until delay time has elapsed */
    65   while ((T1TCR & 0x01) != 0) {
    66     /* Wait */
    67   }
     60  T1TCR = TCR_EN;
    6861}
    6962
    70 /**
    71  * @brief Returns the PLL output clock frequency in [Hz].
    72  *
    73  * Returns zero in case of an unexpected PLL input frequency.
    74  */
    75 unsigned lpc24xx_pllclk( void)
     63void lpc24xx_micro_seconds_delay(unsigned us)
    7664{
    77   unsigned clksrc = GET_CLKSRCSEL_CLKSRC( CLKSRCSEL);
     65  unsigned start = lpc24xx_timer();
     66  unsigned end = start + us * (lpc24xx_cclk() / 1000000);
     67  unsigned now = 0;
     68
     69  do {
     70    now = lpc24xx_timer();
     71  } while (now < end);
     72}
     73
     74unsigned lpc24xx_pllclk(void)
     75{
     76  unsigned clksrc = GET_CLKSRCSEL_CLKSRC(CLKSRCSEL);
    7877  unsigned pllinclk = 0;
    7978  unsigned pllclk = 0;
     
    9594
    9695  /* Get PLL output frequency */
    97   if (IS_FLAG_SET( PLLSTAT, PLLSTAT_PLLC)) {
     96  if (IS_FLAG_SET(PLLSTAT, PLLSTAT_PLLC)) {
    9897    uint32_t pllcfg = PLLCFG;
    99     unsigned n = GET_PLLCFG_NSEL( pllcfg) + 1;
    100     unsigned m = GET_PLLCFG_MSEL( pllcfg) + 1;
     98    unsigned n = GET_PLLCFG_NSEL(pllcfg) + 1;
     99    unsigned m = GET_PLLCFG_MSEL(pllcfg) + 1;
    101100
    102101    pllclk = (pllinclk / n) * 2 * m;
     
    108107}
    109108
    110 /**
    111  * @brief Returns the CPU clock frequency in [Hz].
    112  *
    113  * Returns zero in case of an unexpected PLL input frequency.
    114  */
    115 unsigned lpc24xx_cclk( void)
     109unsigned lpc24xx_cclk(void)
    116110{
    117111  /* Get PLL output frequency */
     
    119113
    120114  /* Get CPU frequency */
    121   unsigned cclk = pllclk / (GET_CCLKCFG_CCLKSEL( CCLKCFG) + 1);
     115  unsigned cclk = pllclk / (GET_CCLKCFG_CCLKSEL(CCLKCFG) + 1);
    122116
    123117  return cclk;
    124118}
    125 
    126 static void lpc24xx_pll_config( uint32_t val)
    127 {
    128   PLLCON = val;
    129   PLLFEED = 0xaa;
    130   PLLFEED = 0x55;
    131 }
    132 
    133 /**
    134  * @brief Sets the Phase Locked Loop (PLL).
    135  *
    136  * @param clksrc Selects the clock source for the PLL.
    137  *
    138  * @param nsel Selects PLL pre-divider value (sometimes named psel).
    139  *
    140  * @param msel Selects PLL multiplier value.
    141  *
    142  * @param cclksel Selects the divide value for creating the CPU clock (CCLK)
    143  * from the PLL output.
    144  *
    145  * @note All parameter values are the actual register field values.
    146  */
    147 void lpc24xx_set_pll( unsigned clksrc, unsigned nsel, unsigned msel, unsigned cclksel)
    148 {
    149   bool pll_enabled = IS_FLAG_SET( PLLSTAT, PLLSTAT_PLLE);
    150 
    151   /* Disconnect PLL if necessary */
    152   if (IS_FLAG_SET( PLLSTAT, PLLSTAT_PLLC)) {
    153     if (pll_enabled) {
    154       lpc24xx_pll_config( PLLCON_PLLE);
    155     } else {
    156       lpc24xx_pll_config( 0);
    157     }
    158   }
    159 
    160   /* Set CPU clock divider to a reasonable save value */
    161   CCLKCFG = 0;
    162 
    163   /* Disable PLL if necessary */
    164   if (pll_enabled) {
    165     lpc24xx_pll_config( 0);
    166   }
    167 
    168   /* Select clock source */
    169   CLKSRCSEL = SET_CLKSRCSEL_CLKSRC( 0, clksrc);
    170 
    171   /* Set PLL Configuration Register */
    172   PLLCFG = SET_PLLCFG_NSEL( 0, nsel) | SET_PLLCFG_MSEL( 0, msel);
    173 
    174   /* Enable PLL */
    175   lpc24xx_pll_config( PLLCON_PLLE);
    176 
    177   /* Wait for lock */
    178   while (IS_FLAG_CLEARED( PLLSTAT, PLLSTAT_PLOCK)) {
    179     /* Wait */
    180   }
    181 
    182   /* Set CPU clock divider and ensure that we have an odd value */
    183   CCLKCFG = SET_CCLKCFG_CCLKSEL( 0, cclksel | 1);
    184 
    185   /* Connect PLL */
    186   lpc24xx_pll_config( PLLCON_PLLE | PLLCON_PLLC);
    187 }
  • c/src/lib/libbsp/arm/lpc24xx/network/network.c

    rf90c5fb rba938b8  
    171171
    172172#ifdef DEBUG
    173   #define LPC24XX_ETH_PRINTF( ...) printf( __VA_ARGS__)
    174   #define LPC24XX_ETH_PRINTK( ...) printk( __VA_ARGS__)
     173  #define LPC24XX_ETH_PRINTF(...) printf(__VA_ARGS__)
     174  #define LPC24XX_ETH_PRINTK(...) printk(__VA_ARGS__)
    175175#else
    176   #define LPC24XX_ETH_PRINTF( ...)
    177   #define LPC24XX_ETH_PRINTK( ...)
     176  #define LPC24XX_ETH_PRINTF(...)
     177  #define LPC24XX_ETH_PRINTK(...)
    178178#endif
    179179
     
    232232}
    233233
    234 static void lpc24xx_eth_reset_filter( void)
     234static void lpc24xx_eth_reset_filter(void)
    235235{
    236236  MAC_RXFILTERCTRL = 0;
     
    240240}
    241241
    242 static void lpc24xx_eth_enable_promiscous_mode( bool enable)
     242static void lpc24xx_eth_enable_promiscous_mode(bool enable)
    243243{
    244244  if (enable) {
     
    268268
    269269  /* Check receive interrupts */
    270   if (IS_FLAG_SET( is, ETH_INT_RX_OVERRUN)) {
     270  if (IS_FLAG_SET(is, ETH_INT_RX_OVERRUN)) {
    271271    re = LPC24XX_ETH_EVENT_INITIALIZE;
    272272    ++e->receive_fatal_errors;
    273   } else if (IS_ANY_FLAG_SET( is, LPC24XX_ETH_INTERRUPT_RECEIVE)) {
     273  } else if (IS_ANY_FLAG_SET(is, LPC24XX_ETH_INTERRUPT_RECEIVE)) {
    274274    re = LPC24XX_ETH_EVENT_INTERRUPT;
    275     ie = SET_FLAGS( ie, LPC24XX_ETH_INTERRUPT_RECEIVE);
     275    ie = SET_FLAGS(ie, LPC24XX_ETH_INTERRUPT_RECEIVE);
    276276  }
    277277
     
    279279  if (re != 0) {
    280280    ++e->receive_interrupts;
    281     (void) rtems_event_send( e->receive_task, re);
     281    (void) rtems_event_send(e->receive_task, re);
    282282  }
    283283
    284284  /* Check transmit interrupts */
    285   if (IS_FLAG_SET( is, ETH_INT_TX_UNDERRUN)) {
     285  if (IS_FLAG_SET(is, ETH_INT_TX_UNDERRUN)) {
    286286    te = LPC24XX_ETH_EVENT_INITIALIZE;
    287287    ++e->transmit_fatal_errors;
    288   } else if (IS_ANY_FLAG_SET( is, LPC24XX_ETH_INTERRUPT_TRANSMIT)) {
     288  } else if (IS_ANY_FLAG_SET(is, LPC24XX_ETH_INTERRUPT_TRANSMIT)) {
    289289    te = LPC24XX_ETH_EVENT_INTERRUPT;
    290     ie = SET_FLAGS( ie, LPC24XX_ETH_INTERRUPT_TRANSMIT);
     290    ie = SET_FLAGS(ie, LPC24XX_ETH_INTERRUPT_TRANSMIT);
    291291  }
    292292
     
    294294  if (te != 0) {
    295295    ++e->transmit_interrupts;
    296     (void) rtems_event_send( e->transmit_task, te);
    297   }
    298 
    299   LPC24XX_ETH_PRINTK( "interrupt: rx = 0x%08x, tx = 0x%08x\n", re, te);
     296    (void) rtems_event_send(e->transmit_task, te);
     297  }
     298
     299  LPC24XX_ETH_PRINTK("interrupt: rx = 0x%08x, tx = 0x%08x\n", re, te);
    300300
    301301  /* Update interrupt mask */
    302   MAC_INTENABLE = CLEAR_FLAGS( im, ie);
     302  MAC_INTENABLE = CLEAR_FLAGS(im, ie);
    303303
    304304  /* Clear interrupts */
     
    306306}
    307307
    308 static void lpc24xx_eth_enable_receive_interrupts( void)
     308static void lpc24xx_eth_enable_receive_interrupts(void)
    309309{
    310310  rtems_interrupt_level level;
    311311
    312   rtems_interrupt_disable( level);
    313   MAC_INTENABLE = SET_FLAGS( MAC_INTENABLE, LPC24XX_ETH_INTERRUPT_RECEIVE);
    314   rtems_interrupt_enable( level);
    315 }
    316 
    317 static void lpc24xx_eth_disable_receive_interrupts( void)
     312  rtems_interrupt_disable(level);
     313  MAC_INTENABLE = SET_FLAGS(MAC_INTENABLE, LPC24XX_ETH_INTERRUPT_RECEIVE);
     314  rtems_interrupt_enable(level);
     315}
     316
     317static void lpc24xx_eth_disable_receive_interrupts(void)
    318318{
    319319  rtems_interrupt_level level;
    320320
    321   rtems_interrupt_disable( level);
    322   MAC_INTENABLE = CLEAR_FLAGS( MAC_INTENABLE, LPC24XX_ETH_INTERRUPT_RECEIVE);
    323   rtems_interrupt_enable( level);
    324 }
    325 
    326 static void lpc24xx_eth_enable_transmit_interrupts( void)
     321  rtems_interrupt_disable(level);
     322  MAC_INTENABLE = CLEAR_FLAGS(MAC_INTENABLE, LPC24XX_ETH_INTERRUPT_RECEIVE);
     323  rtems_interrupt_enable(level);
     324}
     325
     326static void lpc24xx_eth_enable_transmit_interrupts(void)
    327327{
    328328  rtems_interrupt_level level;
    329329
    330   rtems_interrupt_disable( level);
    331   MAC_INTENABLE = SET_FLAGS( MAC_INTENABLE, LPC24XX_ETH_INTERRUPT_TRANSMIT);
    332   rtems_interrupt_enable( level);
    333 }
    334 
    335 static void lpc24xx_eth_disable_transmit_interrupts( void)
     330  rtems_interrupt_disable(level);
     331  MAC_INTENABLE = SET_FLAGS(MAC_INTENABLE, LPC24XX_ETH_INTERRUPT_TRANSMIT);
     332  rtems_interrupt_enable(level);
     333}
     334
     335static void lpc24xx_eth_disable_transmit_interrupts(void)
    336336{
    337337  rtems_interrupt_level level;
    338338
    339   rtems_interrupt_disable( level);
    340   MAC_INTENABLE = CLEAR_FLAGS( MAC_INTENABLE, LPC24XX_ETH_INTERRUPT_TRANSMIT);
    341   rtems_interrupt_enable( level);
    342 }
    343 
    344 static struct mbuf *lpc24xx_eth_new_mbuf( struct ifnet *ifp, bool wait)
     339  rtems_interrupt_disable(level);
     340  MAC_INTENABLE = CLEAR_FLAGS(MAC_INTENABLE, LPC24XX_ETH_INTERRUPT_TRANSMIT);
     341  rtems_interrupt_enable(level);
     342}
     343
     344static struct mbuf *lpc24xx_eth_new_mbuf(struct ifnet *ifp, bool wait)
    345345{
    346346  struct mbuf *m = NULL;
    347347  int mw = wait ? M_WAIT : M_DONTWAIT;
    348348
    349   MGETHDR( m, mw, MT_DATA);
     349  MGETHDR(m, mw, MT_DATA);
    350350  if (m != NULL) {
    351     MCLGET( m, mw);
    352     if (IS_FLAG_SET( m->m_flags, M_EXT)) {
     351    MCLGET(m, mw);
     352    if (IS_FLAG_SET(m->m_flags, M_EXT)) {
    353353      /* Set receive interface */
    354354      m->m_pkthdr.rcvif = ifp;
    355355
    356356      /* Adjust by two bytes for proper IP header alignment */
    357       m->m_data = mtod( m, char *) + 2;
     357      m->m_data = mtod(m, char *) + 2;
    358358
    359359      return m;
    360360    } else {
    361       m_free( m);
     361      m_free(m);
    362362    }
    363363  }
     
    375375{
    376376  /* New mbuf */
    377   struct mbuf *m = lpc24xx_eth_new_mbuf( ifp, wait);
     377  struct mbuf *m = lpc24xx_eth_new_mbuf(ifp, wait);
    378378
    379379  /* Check mbuf */
    380380  if (m != NULL) {
    381381    /* Add mbuf to queue */
    382     desc [i].start = mtod( m, uint32_t);
    383     desc [i].control = SET_ETH_RX_CTRL_SIZE( 0, MCLBYTES - 1)
     382    desc [i].start = mtod(m, uint32_t);
     383    desc [i].control = SET_ETH_RX_CTRL_SIZE(0, MCLBYTES - 1)
    384384      | ETH_RX_CTRL_INTERRUPT;
    385385
     
    393393}
    394394
    395 static void lpc24xx_eth_receive_task( void *arg)
     395static void lpc24xx_eth_receive_task(void *arg)
    396396{
    397397  rtems_status_code sc = RTEMS_SUCCESSFUL;
     
    412412  uint32_t receive_index = 0;
    413413
    414   LPC24XX_ETH_PRINTF( "%s\n", __func__);
     414  LPC24XX_ETH_PRINTF("%s\n", __func__);
    415415
    416416  /* Main event loop */
     
    425425      &events
    426426    );
    427     RTEMS_CLEANUP_SC( sc, cleanup, "wait for events");
    428 
    429     LPC24XX_ETH_PRINTF( "rx: wake up: 0x%08" PRIx32 "\n", events);
     427    RTEMS_CLEANUP_SC(sc, cleanup, "wait for events");
     428
     429    LPC24XX_ETH_PRINTF("rx: wake up: 0x%08" PRIx32 "\n", events);
    430430
    431431    /* Initialize receiver? */
    432     if (IS_FLAG_SET( events, LPC24XX_ETH_EVENT_INITIALIZE)) {
     432    if (IS_FLAG_SET(events, LPC24XX_ETH_EVENT_INITIALIZE)) {
    433433      /* Disable receive interrupts */
    434434      lpc24xx_eth_disable_receive_interrupts();
    435435
    436436      /* Disable receiver */
    437       MAC_COMMAND = CLEAR_FLAG( MAC_COMMAND, ETH_CMD_RX_ENABLE);
     437      MAC_COMMAND = CLEAR_FLAG(MAC_COMMAND, ETH_CMD_RX_ENABLE);
    438438
    439439      /* Wait for inactive status */
    440       while (IS_FLAG_SET( MAC_STATUS, ETH_STAT_RX_ACTIVE)) {
     440      while (IS_FLAG_SET(MAC_STATUS, ETH_STAT_RX_ACTIVE)) {
    441441        /* Wait */
    442442      }
    443443
    444444      /* Reset */
    445       MAC_COMMAND = SET_FLAG( MAC_COMMAND, ETH_CMD_RX_RESET);
     445      MAC_COMMAND = SET_FLAG(MAC_COMMAND, ETH_CMD_RX_RESET);
    446446
    447447      /* Clear receive interrupts */
     
    463463      for (produce_index = consume_index; produce_index <= index_max; ++produce_index) {
    464464        if (
    465           !lpc24xx_eth_add_new_mbuf( ifp, desc, mbuf_table, produce_index, false)
     465          !lpc24xx_eth_add_new_mbuf(ifp, desc, mbuf_table, produce_index, false)
    466466        ) {
    467467          break;
     
    479479        index_max = produce_index - 1;
    480480
    481         RTEMS_SYSLOG_ERROR( "not enough mbufs to fill receive queue");
     481        RTEMS_SYSLOG_ERROR("not enough mbufs to fill receive queue");
    482482      }
    483483
     
    493493
    494494      /* Enable receiver */
    495       MAC_COMMAND = SET_FLAG( MAC_COMMAND, ETH_CMD_RX_ENABLE);
     495      MAC_COMMAND = SET_FLAG(MAC_COMMAND, ETH_CMD_RX_ENABLE);
    496496
    497497      /* Enable receive interrupts */
     
    518518
    519519        if (
    520           IS_FLAG_SET( stat, ETH_RX_STAT_LAST_FLAG)
    521             && ARE_FLAGS_CLEARED( stat, LPC24XX_ETH_RX_STAT_ERRORS)
     520          IS_FLAG_SET(stat, ETH_RX_STAT_LAST_FLAG)
     521            && ARE_FLAGS_CLEARED(stat, LPC24XX_ETH_RX_STAT_ERRORS)
    522522        ) {
    523523          /* Ethernet header */
    524           struct ether_header *eh = mtod( m, struct ether_header *);
     524          struct ether_header *eh = mtod(m, struct ether_header *);
    525525
    526526          /* Discard Ethernet header and CRC */
    527           int sz = (int) GET_ETH_RX_STAT_RXSIZE( stat) + 1
     527          int sz = (int) GET_ETH_RX_STAT_RXSIZE(stat) + 1
    528528            - ETHER_HDR_LEN - ETHER_CRC_LEN;
    529529
     
    531531          m->m_len = sz;
    532532          m->m_pkthdr.len = sz;
    533           m->m_data = mtod( m, char *) + ETHER_HDR_LEN;
    534 
    535           LPC24XX_ETH_PRINTF( "rx: %02" PRIu32 ": %u\n", receive_index, sz);
     533          m->m_data = mtod(m, char *) + ETHER_HDR_LEN;
     534
     535          LPC24XX_ETH_PRINTF("rx: %02" PRIu32 ": %u\n", receive_index, sz);
    536536
    537537          /* Hand over */
    538           ether_input( ifp, eh, m);
     538          ether_input(ifp, eh, m);
    539539
    540540          /* Increment received frames counter */
     
    542542        } else {
    543543          /* Release mbuf */
    544           m_free( m);
     544          m_free(m);
    545545
    546546          /* Update error counters */
    547           if (IS_FLAG_SET( stat, ETH_RX_STAT_OVERRUN)) {
     547          if (IS_FLAG_SET(stat, ETH_RX_STAT_OVERRUN)) {
    548548            ++e->receive_overrun_errors;
    549549          }
    550           if (IS_FLAG_CLEARED( stat, ETH_RX_STAT_LAST_FLAG)) {
     550          if (IS_FLAG_CLEARED(stat, ETH_RX_STAT_LAST_FLAG)) {
    551551            ++e->receive_fragment_errors;
    552552          }
    553           if (IS_FLAG_SET( stat, ETH_RX_STAT_CRC_ERROR)) {
     553          if (IS_FLAG_SET(stat, ETH_RX_STAT_CRC_ERROR)) {
    554554            ++e->receive_crc_errors;
    555555          }
    556           if (IS_FLAG_SET( stat, ETH_RX_STAT_SYMBOL_ERROR)) {
     556          if (IS_FLAG_SET(stat, ETH_RX_STAT_SYMBOL_ERROR)) {
    557557            ++e->receive_symbol_errors;
    558558          }
    559           if (IS_FLAG_SET( stat, ETH_RX_STAT_LENGTH_ERROR)) {
     559          if (IS_FLAG_SET(stat, ETH_RX_STAT_LENGTH_ERROR)) {
    560560            ++e->receive_length_errors;
    561561          }
    562           if (IS_FLAG_SET( stat, ETH_RX_STAT_ALIGNMENT_ERROR)) {
     562          if (IS_FLAG_SET(stat, ETH_RX_STAT_ALIGNMENT_ERROR)) {
    563563            ++e->receive_alignment_errors;
    564564          }
    565           if (IS_FLAG_SET( stat, ETH_RX_STAT_NO_DESCRIPTOR)) {
     565          if (IS_FLAG_SET(stat, ETH_RX_STAT_NO_DESCRIPTOR)) {
    566566            ++e->receive_no_descriptor_errors;
    567567          }
     
    569569
    570570        /* Increment receive index */
    571         receive_index = lpc24xx_eth_increment( receive_index, index_max);
     571        receive_index = lpc24xx_eth_increment(receive_index, index_max);
    572572      } else {
    573573        /* Nothing to do, enable receive interrupts */
     
    579579    /* Wait for mbuf? */
    580580    wait_for_mbuf =
    581       lpc24xx_eth_increment( produce_index, index_max) == consume_index;
     581      lpc24xx_eth_increment(produce_index, index_max) == consume_index;
    582582
    583583    /* Fill queue with new mbufs */
     
    596596
    597597      /* Increment consume index */
    598       consume_index = lpc24xx_eth_increment( consume_index, index_max);
     598      consume_index = lpc24xx_eth_increment(consume_index, index_max);
    599599
    600600      /* Update consume indices */
     
    612612
    613613  /* Terminate self */
    614   (void) rtems_task_delete( RTEMS_SELF);
     614  (void) rtems_task_delete(RTEMS_SELF);
    615615}
    616616
     
    627627    if (m == NULL) {
    628628      /* Dequeue first fragment of the next frame */
    629       IF_DEQUEUE( &ifp->if_snd, m);
     629      IF_DEQUEUE(&ifp->if_snd, m);
    630630
    631631      /* Empty queue? */
     
    643643    } else {
    644644      /* Discard empty fragments */
    645       m = m_free( m);
     645      m = m_free(m);
    646646    }
    647647  }
    648648
    649649  /* Set fragment size */
    650   *ctrl = SET_ETH_TX_CTRL_SIZE( 0, size - 1);
     650  *ctrl = SET_ETH_TX_CTRL_SIZE(0, size - 1);
    651651
    652652  /* Discard empty successive fragments */
    653653  n = m->m_next;
    654654  while (n != NULL && n->m_len <= 0) {
    655     n = m_free( n);
     655    n = m_free(n);
    656656  }
    657657  m->m_next = n;
     
    659659  /* Is our fragment the last in the frame? */
    660660  if (n == NULL) {
    661     *ctrl = SET_FLAGS( *ctrl, LPC24XX_ETH_LAST_FRAGMENT_FLAGS);
     661    *ctrl = SET_FLAGS(*ctrl, LPC24XX_ETH_LAST_FRAGMENT_FLAGS);
    662662  }
    663663
     
    665665}
    666666
    667 static void lpc24xx_eth_transmit_task( void *arg)
     667static void lpc24xx_eth_transmit_task(void *arg)
    668668{
    669669  rtems_status_code sc = RTEMS_SUCCESSFUL;
     
    686686  char *frame_buffer = NULL;
    687687
    688   LPC24XX_ETH_PRINTF( "%s\n", __func__);
     688  LPC24XX_ETH_PRINTF("%s\n", __func__);
    689689
    690690  /* Initialize descriptor table */
     
    705705      &events
    706706    );
    707     RTEMS_CLEANUP_SC( sc, cleanup, "wait for events");
    708 
    709     LPC24XX_ETH_PRINTF( "tx: wake up: 0x%08" PRIx32 "\n", events);
     707    RTEMS_CLEANUP_SC(sc, cleanup, "wait for events");
     708
     709    LPC24XX_ETH_PRINTF("tx: wake up: 0x%08" PRIx32 "\n", events);
    710710
    711711    /* Initialize transmitter? */
    712     if (IS_FLAG_SET( events, LPC24XX_ETH_EVENT_INITIALIZE)) {
     712    if (IS_FLAG_SET(events, LPC24XX_ETH_EVENT_INITIALIZE)) {
    713713      /* Disable transmit interrupts */
    714714      lpc24xx_eth_disable_transmit_interrupts();
    715715
    716716      /* Disable transmitter */
    717       MAC_COMMAND = CLEAR_FLAG( MAC_COMMAND, ETH_CMD_TX_ENABLE);
     717      MAC_COMMAND = CLEAR_FLAG(MAC_COMMAND, ETH_CMD_TX_ENABLE);
    718718
    719719      /* Wait for inactive status */
    720       while (IS_FLAG_SET( MAC_STATUS, ETH_STAT_TX_ACTIVE)) {
     720      while (IS_FLAG_SET(MAC_STATUS, ETH_STAT_TX_ACTIVE)) {
    721721        /* Wait */
    722722      }
    723723
    724724      /* Reset */
    725       MAC_COMMAND = SET_FLAG( MAC_COMMAND, ETH_CMD_TX_RESET);
     725      MAC_COMMAND = SET_FLAG(MAC_COMMAND, ETH_CMD_TX_RESET);
    726726
    727727      /* Clear transmit interrupts */
     
    741741
    742742      /* Enable transmitter */
    743       MAC_COMMAND = SET_FLAG( MAC_COMMAND, ETH_CMD_TX_ENABLE);
     743      MAC_COMMAND = SET_FLAG(MAC_COMMAND, ETH_CMD_TX_ENABLE);
    744744    }
    745745
     
    765765        /* Update error counters */
    766766        if (
    767           IS_ANY_FLAG_SET( s, ETH_TX_STAT_ERROR | ETH_TX_STAT_NO_DESCRIPTOR)
     767          IS_ANY_FLAG_SET(s, ETH_TX_STAT_ERROR | ETH_TX_STAT_NO_DESCRIPTOR)
    768768        ) {
    769           if (IS_FLAG_SET( s, ETH_TX_STAT_UNDERRUN)) {
     769          if (IS_FLAG_SET(s, ETH_TX_STAT_UNDERRUN)) {
    770770            ++e->transmit_underrun_errors;
    771771          }
    772           if (IS_FLAG_SET( s, ETH_TX_STAT_LATE_COLLISION)) {
     772          if (IS_FLAG_SET(s, ETH_TX_STAT_LATE_COLLISION)) {
    773773            ++e->transmit_late_collision_errors;
    774774          }
    775           if (IS_FLAG_SET( s, ETH_TX_STAT_EXCESSIVE_COLLISION)) {
     775          if (IS_FLAG_SET(s, ETH_TX_STAT_EXCESSIVE_COLLISION)) {
    776776            ++e->transmit_excessive_collision_errors;
    777777          }
    778           if (IS_FLAG_SET( s, ETH_TX_STAT_EXCESSIVE_DEFER)) {
     778          if (IS_FLAG_SET(s, ETH_TX_STAT_EXCESSIVE_DEFER)) {
    779779            ++e->transmit_excessive_defer_errors;
    780780          }
    781           if (IS_FLAG_SET( s, ETH_TX_STAT_NO_DESCRIPTOR)) {
     781          if (IS_FLAG_SET(s, ETH_TX_STAT_NO_DESCRIPTOR)) {
    782782            ++e->transmit_no_descriptor_errors;
    783783          }
     
    785785
    786786        /* Next consume index */
    787         c = lpc24xx_eth_increment( c, index_max);
     787        c = lpc24xx_eth_increment(c, index_max);
    788788      }
    789789    }
     
    792792    while (true) {
    793793      /* Compute next produce index */
    794       uint32_t p = lpc24xx_eth_increment( produce_index, index_max);
     794      uint32_t p = lpc24xx_eth_increment(produce_index, index_max);
    795795
    796796      /* Queue full? */
     
    801801
    802802      /* Get next fragment and control value */
    803       m = lpc24xx_eth_next_fragment( ifp, m, &ctrl);
     803      m = lpc24xx_eth_next_fragment(ifp, m, &ctrl);
    804804
    805805      /* New fragment? */
    806806      if (m != NULL) {
    807807        size_t fragment_length = (size_t) m->m_len;
    808         void *fragment_start = mtod( m, void *);
     808        void *fragment_start = mtod(m, void *);
    809809        uint32_t new_frame_length = frame_length + fragment_length;
    810810
    811811        /* Check buffer size */
    812812        if (new_frame_length > LPC24XX_ETH_TRANSMIT_BUFFER_SIZE) {
    813           LPC24XX_ETH_PRINTF( "tx: overflow\n");
     813          LPC24XX_ETH_PRINTF("tx: overflow\n");
    814814
    815815          /* Discard overflow data */
     
    818818
    819819          /* Finalize frame */
    820           ctrl = SET_FLAGS( ctrl, LPC24XX_ETH_LAST_FRAGMENT_FLAGS);
     820          ctrl = SET_FLAGS(ctrl, LPC24XX_ETH_LAST_FRAGMENT_FLAGS);
    821821
    822822          /* Update error counter */
     
    827827          "tx: copy: %" PRIu32 "%s%s\n",
    828828          fragment_length,
    829           IS_FLAG_SET( m->m_flags, M_EXT) ? ", E" : "",
    830           IS_FLAG_SET( m->m_flags, M_PKTHDR) ? ", H" : ""
     829          IS_FLAG_SET(m->m_flags, M_EXT) ? ", E" : "",
     830          IS_FLAG_SET(m->m_flags, M_PKTHDR) ? ", H" : ""
    831831        );
    832832
    833833        /* Copy fragment to buffer in Ethernet RAM */
    834         memcpy( frame_buffer, fragment_start, fragment_length);
    835 
    836         if (IS_FLAG_SET( ctrl, ETH_TX_CTRL_LAST)) {
     834        memcpy(frame_buffer, fragment_start, fragment_length);
     835
     836        if (IS_FLAG_SET(ctrl, ETH_TX_CTRL_LAST)) {
    837837          /* Finalize descriptor */
    838838          desc [produce_index].control =
    839             SET_ETH_TX_CTRL_SIZE( ctrl, new_frame_length - 1);
    840 
    841           LPC24XX_ETH_PRINTF( "tx: %02" PRIu32 ": %" PRIu32 "\n", produce_index, new_frame_length);
     839            SET_ETH_TX_CTRL_SIZE(ctrl, new_frame_length - 1);
     840
     841          LPC24XX_ETH_PRINTF("tx: %02" PRIu32 ": %" PRIu32 "\n", produce_index, new_frame_length);
    842842
    843843          /* Next produce index */
     
    862862
    863863        /* Free mbuf and get next */
    864         m = m_free( m);
     864        m = m_free(m);
    865865      } else {
    866866        /* Nothing to transmit */
     
    872872    if (m == NULL) {
    873873      /* Interface is now inactive */
    874       ifp->if_flags = CLEAR_FLAG( ifp->if_flags, IFF_OACTIVE);
     874      ifp->if_flags = CLEAR_FLAG(ifp->if_flags, IFF_OACTIVE);
    875875    } else {
    876876      /* Enable transmit interrupts */
     
    888888
    889889  /* Terminate self */
    890   (void) rtems_task_delete( RTEMS_SELF);
    891 }
    892 
    893 static void lpc24xx_eth_interface_init( void *arg)
     890  (void) rtems_task_delete(RTEMS_SELF);
     891}
     892
     893static void lpc24xx_eth_interface_init(void *arg)
    894894{
    895895  rtems_status_code sc = RTEMS_SUCCESSFUL;
     
    897897  struct ifnet *ifp = &e->arpcom.ac_if;
    898898
    899   LPC24XX_ETH_PRINTF( "%s\n", __func__);
     899  LPC24XX_ETH_PRINTF("%s\n", __func__);
    900900
    901901  if (e->state == LPC24XX_ETH_INITIALIZED) {
    902     #ifndef LPC24XX_HAS_UBOOT
    903       /* Enable module power */
    904       lpc24xx_module_enable(
    905         LPC24XX_MODULE_ETHERNET,
    906         0,
    907         LPC24XX_MODULE_PCLK_DEFAULT
    908       );
    909 
    910       /* Module IO configuration */
    911       #ifdef LPC24XX_ETHERNET_RMII
    912         lpc24xx_io_config( LPC24XX_MODULE_ETHERNET, 0, 0);
    913       #else
    914         lpc24xx_io_config( LPC24XX_MODULE_ETHERNET, 0, 1);
    915       #endif
    916 
    917       /* Soft reset */
    918 
    919       /* Do soft reset */
    920       MAC_COMMAND = 0x38;
    921       MAC_MAC1 = 0xcf00;
    922 
    923       /* Initialize PHY */
    924       /* TODO */
    925 
    926       /* Reinitialize registers */
    927       MAC_MAC2 = 0x31;
    928       MAC_IPGT = 0x15;
    929       MAC_IPGR = 0x12;
    930       MAC_CLRT = 0x370f;
    931       MAC_MAXF = 0x0600;
    932       MAC_SUPP = 0x0100;
    933       MAC_TEST = 0;
    934       #ifdef LPC24XX_ETHERNET_RMII
    935         MAC_COMMAND = 0x0400;
    936       #else
    937         MAC_COMMAND = 0x0600;
    938       #endif
    939       MAC_INTENABLE = 0;
    940       MAC_INTCLEAR = 0x30ff;
    941       MAC_POWERDOWN = 0;
    942 
    943       /* MAC address */
    944       MAC_SA0 = ((uint32_t) e->arpcom.ac_enaddr [5] << 8)
    945         | (uint32_t) e->arpcom.ac_enaddr [4];
    946       MAC_SA1 = ((uint32_t) e->arpcom.ac_enaddr [3] << 8)
    947         | (uint32_t) e->arpcom.ac_enaddr [2];
    948       MAC_SA2 = ((uint32_t) e->arpcom.ac_enaddr [1] << 8)
    949         | (uint32_t) e->arpcom.ac_enaddr [0];
    950 
    951       /* Enable receiver */
    952       MAC_MAC1 = 0x03;
    953     #else /* LPC24XX_HAS_UBOOT */
    954       /* Reset receiver and transmitter */
    955       MAC_COMMAND = SET_FLAGS(
    956         MAC_COMMAND,
    957         ETH_CMD_RX_RESET | ETH_CMD_TX_RESET | ETH_CMD_REG_RESET
    958       );
    959 
    960       /* MAC configuration */
    961       MAC_MAC1 = 0x3;
    962     #endif /* LPC24XX_HAS_UBOOT */
     902    /* Enable module power */
     903    lpc24xx_module_enable(
     904      LPC24XX_MODULE_ETHERNET,
     905      0,
     906      LPC24XX_MODULE_PCLK_DEFAULT
     907    );
     908
     909    /* Module IO configuration */
     910    #ifdef LPC24XX_ETHERNET_RMII
     911        lpc24xx_io_config(LPC24XX_MODULE_ETHERNET, 0, 0);
     912    #else
     913        lpc24xx_io_config(LPC24XX_MODULE_ETHERNET, 0, 1);
     914    #endif
     915
     916    /* Soft reset */
     917
     918    /* Do soft reset */
     919    MAC_COMMAND = 0x38;
     920    MAC_MAC1 = 0xcf00;
     921
     922    /* Initialize PHY */
     923    /* TODO */
     924
     925    /* Reinitialize registers */
     926    MAC_MAC2 = 0x31;
     927    MAC_IPGT = 0x15;
     928    MAC_IPGR = 0x12;
     929    MAC_CLRT = 0x370f;
     930    MAC_MAXF = 0x0600;
     931    MAC_SUPP = 0x0100;
     932    MAC_TEST = 0;
     933    #ifdef LPC24XX_ETHERNET_RMII
     934      MAC_COMMAND = 0x0400;
     935    #else
     936      MAC_COMMAND = 0x0600;
     937    #endif
     938    MAC_INTENABLE = 0;
     939    MAC_INTCLEAR = 0x30ff;
     940    MAC_POWERDOWN = 0;
     941
     942    /* MAC address */
     943    MAC_SA0 = ((uint32_t) e->arpcom.ac_enaddr [5] << 8)
     944      | (uint32_t) e->arpcom.ac_enaddr [4];
     945    MAC_SA1 = ((uint32_t) e->arpcom.ac_enaddr [3] << 8)
     946      | (uint32_t) e->arpcom.ac_enaddr [2];
     947    MAC_SA2 = ((uint32_t) e->arpcom.ac_enaddr [1] << 8)
     948      | (uint32_t) e->arpcom.ac_enaddr [0];
     949
     950    /* Enable receiver */
     951    MAC_MAC1 = 0x03;
    963952
    964953    /* Start receive task */
     
    970959        e
    971960      );
    972       sc = rtems_event_send( e->receive_task, LPC24XX_ETH_EVENT_INITIALIZE);
    973       RTEMS_SYSLOG_ERROR_SC( sc, "send receive initialize event");
     961      sc = rtems_event_send(e->receive_task, LPC24XX_ETH_EVENT_INITIALIZE);
     962      RTEMS_SYSLOG_ERROR_SC(sc, "send receive initialize event");
    974963    }
    975964
     
    982971        e
    983972      );
    984       sc = rtems_event_send( e->transmit_task, LPC24XX_ETH_EVENT_INITIALIZE);
    985       RTEMS_SYSLOG_ERROR_SC( sc, "send transmit initialize event");
     973      sc = rtems_event_send(e->transmit_task, LPC24XX_ETH_EVENT_INITIALIZE);
     974      RTEMS_SYSLOG_ERROR_SC(sc, "send transmit initialize event");
    986975    }
    987976
     
    1000989    /* Enable promiscous mode */
    1001990    lpc24xx_eth_enable_promiscous_mode(
    1002       IS_FLAG_SET( ifp->if_flags, IFF_PROMISC)
     991      IS_FLAG_SET(ifp->if_flags, IFF_PROMISC)
    1003992    );
    1004993
     
    1007996
    1008997    /* Set interface to running state */
    1009     ifp->if_flags = SET_FLAG( ifp->if_flags, IFF_RUNNING);
     998    ifp->if_flags = SET_FLAG(ifp->if_flags, IFF_RUNNING);
    1010999
    10111000    /* Change state */
     
    10141003}
    10151004
    1016 static void lpc24xx_eth_interface_stats( const lpc24xx_eth_driver_entry *e)
     1005static void lpc24xx_eth_interface_stats(const lpc24xx_eth_driver_entry *e)
    10171006{
    10181007  rtems_bsdnet_semaphore_release();
    10191008
    1020   printf( "received frames:                     %u\n", e->received_frames);
    1021   printf( "receive interrupts:                  %u\n", e->receive_interrupts);
    1022   printf( "transmitted frames:                  %u\n", e->transmitted_frames);
    1023   printf( "transmit interrupts:                 %u\n", e->transmit_interrupts);
    1024   printf( "receive overrun errors:              %u\n", e->receive_overrun_errors);
    1025   printf( "receive fragment errors:             %u\n", e->receive_fragment_errors);
    1026   printf( "receive CRC errors:                  %u\n", e->receive_crc_errors);
    1027   printf( "receive symbol errors:               %u\n", e->receive_symbol_errors);
    1028   printf( "receive length errors:               %u\n", e->receive_length_errors);
    1029   printf( "receive alignment errors:            %u\n", e->receive_alignment_errors);
    1030   printf( "receive no descriptor errors:        %u\n", e->receive_no_descriptor_errors);
    1031   printf( "receive fatal errors:                %u\n", e->receive_fatal_errors);
    1032   printf( "transmit underrun errors:            %u\n", e->transmit_underrun_errors);
    1033   printf( "transmit late collision errors:      %u\n", e->transmit_late_collision_errors);
    1034   printf( "transmit excessive collision errors: %u\n", e->transmit_excessive_collision_errors);
    1035   printf( "transmit excessive defer errors:     %u\n", e->transmit_excessive_defer_errors);
    1036   printf( "transmit no descriptor errors:       %u\n", e->transmit_no_descriptor_errors);
    1037   printf( "transmit overflow errors:            %u\n", e->transmit_overflow_errors);
    1038   printf( "transmit fatal errors:               %u\n", e->transmit_fatal_errors);
     1009  printf("received frames:                     %u\n", e->received_frames);
     1010  printf("receive interrupts:                  %u\n", e->receive_interrupts);
     1011  printf("transmitted frames:                  %u\n", e->transmitted_frames);
     1012  printf("transmit interrupts:                 %u\n", e->transmit_interrupts);
     1013  printf("receive overrun errors:              %u\n", e->receive_overrun_errors);
     1014  printf("receive fragment errors:             %u\n", e->receive_fragment_errors);
     1015  printf("receive CRC errors:                  %u\n", e->receive_crc_errors);
     1016  printf("receive symbol errors:               %u\n", e->receive_symbol_errors);
     1017  printf("receive length errors:               %u\n", e->receive_length_errors);
     1018  printf("receive alignment errors:            %u\n", e->receive_alignment_errors);
     1019  printf("receive no descriptor errors:        %u\n", e->receive_no_descriptor_errors);
     1020  printf("receive fatal errors:                %u\n", e->receive_fatal_errors);
     1021  printf("transmit underrun errors:            %u\n", e->transmit_underrun_errors);
     1022  printf("transmit late collision errors:      %u\n", e->transmit_late_collision_errors);
     1023  printf("transmit excessive collision errors: %u\n", e->transmit_excessive_collision_errors);
     1024  printf("transmit excessive defer errors:     %u\n", e->transmit_excessive_defer_errors);
     1025  printf("transmit no descriptor errors:       %u\n", e->transmit_no_descriptor_errors);
     1026  printf("transmit overflow errors:            %u\n", e->transmit_overflow_errors);
     1027  printf("transmit fatal errors:               %u\n", e->transmit_fatal_errors);
    10391028
    10401029  rtems_bsdnet_semaphore_obtain();
     
    10501039  int rv = 0;
    10511040
    1052   LPC24XX_ETH_PRINTF( "%s\n", __func__);
     1041  LPC24XX_ETH_PRINTF("%s\n", __func__);
    10531042
    10541043  switch (command)  {
    10551044    case SIOCGIFMEDIA:
    10561045    case SIOCSIFMEDIA:
    1057       rtems_mii_ioctl( &e->mdio_info, e, (int) command, (int *) data);
     1046      rtems_mii_ioctl(&e->mdio_info, e, (int) command, (int *) data);
    10581047      break;
    10591048    case SIOCGIFADDR:
    10601049    case SIOCSIFADDR:
    1061       ether_ioctl( ifp, command, data);
     1050      ether_ioctl(ifp, command, data);
    10621051      break;
    10631052    case SIOCSIFFLAGS:
     
    10661055      }
    10671056      if (ifp->if_flags & IFF_UP) {
    1068         ifp->if_flags = SET_FLAG( ifp->if_flags, IFF_RUNNING);
     1057        ifp->if_flags = SET_FLAG(ifp->if_flags, IFF_RUNNING);
    10691058        /* TODO: init */
    10701059      }
    10711060      break;
    10721061    case SIO_RTEMS_SHOW_STATS:
    1073       lpc24xx_eth_interface_stats( e);
     1062      lpc24xx_eth_interface_stats(e);
    10741063      break;
    10751064    default:
     
    10811070}
    10821071
    1083 static void lpc24xx_eth_interface_start( struct ifnet *ifp)
     1072static void lpc24xx_eth_interface_start(struct ifnet *ifp)
    10841073{
    10851074  rtems_status_code sc = RTEMS_SUCCESSFUL;
    10861075  lpc24xx_eth_driver_entry *e = (lpc24xx_eth_driver_entry *) ifp->if_softc;
    10871076
    1088   ifp->if_flags = SET_FLAG( ifp->if_flags, IFF_OACTIVE);
    1089 
    1090   sc = rtems_event_send( e->transmit_task, LPC24XX_ETH_EVENT_START);
    1091   RTEMS_SYSLOG_ERROR_SC( sc, "send transmit start event");
    1092 }
    1093 
    1094 static void lpc24xx_eth_interface_watchdog( struct ifnet *ifp)
     1077  ifp->if_flags = SET_FLAG(ifp->if_flags, IFF_OACTIVE);
     1078
     1079  sc = rtems_event_send(e->transmit_task, LPC24XX_ETH_EVENT_START);
     1080  RTEMS_SYSLOG_ERROR_SC(sc, "send transmit start event");
     1081}
     1082
     1083static void lpc24xx_eth_interface_watchdog(struct ifnet *ifp)
    10951084{
    10961085  lpc24xx_eth_driver_entry *e = (lpc24xx_eth_driver_entry *) ifp->if_softc;
    10971086
    1098   LPC24XX_ETH_PRINTF( "%s\n", __func__);
    1099 }
    1100 
    1101 static int lpc24xx_eth_attach( struct rtems_bsdnet_ifconfig *config)
     1087  LPC24XX_ETH_PRINTF("%s\n", __func__);
     1088}
     1089
     1090static int lpc24xx_eth_attach(struct rtems_bsdnet_ifconfig *config)
    11021091{
    11031092  rtems_status_code sc = RTEMS_SUCCESSFUL;
     
    11051094  struct ifnet *ifp = &e->arpcom.ac_if;
    11061095  char *unit_name = NULL;
    1107   int unit_number = rtems_bsdnet_parse_driver_name( config, &unit_name);
     1096  int unit_number = rtems_bsdnet_parse_driver_name(config, &unit_name);
    11081097  uint32_t reg = 0;
    11091098
    11101099  /* Check parameter */
    11111100  if (unit_number < 0) {
    1112     RTEMS_SYSLOG_ERROR( "parse error for interface name\n");
     1101    RTEMS_SYSLOG_ERROR("parse error for interface name\n");
    11131102    return 0;
    11141103  }
    11151104  if (unit_number != 0) {
    1116     RTEMS_DO_CLEANUP( cleanup, "unexpected unit number");
     1105    RTEMS_DO_CLEANUP(cleanup, "unexpected unit number");
    11171106  }
    11181107  if (config->hardware_address == NULL) {
    1119     RTEMS_DO_CLEANUP( cleanup, "MAC address missing");
     1108    RTEMS_DO_CLEANUP(cleanup, "MAC address missing");
    11201109  }
    11211110  if (e->state != LPC24XX_ETH_NOT_INITIALIZED) {
    1122     RTEMS_DO_CLEANUP( cleanup, "already attached");
     1111    RTEMS_DO_CLEANUP(cleanup, "already attached");
    11231112  }
    11241113
     
    11581147    e
    11591148  );
    1160   RTEMS_CLEANUP_SC( sc, cleanup, "install interrupt handler");
     1149  RTEMS_CLEANUP_SC(sc, cleanup, "install interrupt handler");
    11611150
    11621151  /* Copy MAC address */
    1163   memcpy( e->arpcom.ac_enaddr, config->hardware_address, ETHER_ADDR_LEN);
     1152  memcpy(e->arpcom.ac_enaddr, config->hardware_address, ETHER_ADDR_LEN);
    11641153
    11651154  /* Clear Ethernet RAM */
    1166   memset( (void *) LPC24XX_ETH_RAM_START, 0, (size_t) LPC24XX_ETH_RAM_SIZE);
     1155  memset((void *) LPC24XX_ETH_RAM_START, 0, (size_t) LPC24XX_ETH_RAM_SIZE);
    11671156
    11681157  /* Set interface data */
     
    11841173
    11851174  /* Attach the interface */
    1186   if_attach( ifp);
    1187   ether_ifattach( ifp);
     1175  if_attach(ifp);
     1176  ether_ifattach(ifp);
    11881177
    11891178  return 1;
     
    11921181
    11931182  /* FIXME: Type */
    1194   free( unit_name, (int) 0xdeadbeef);
     1183  free(unit_name, (int) 0xdeadbeef);
     1184
     1185  return 0;
     1186}
     1187
     1188static int lpc24xx_eth_detach(struct rtems_bsdnet_ifconfig *config)
     1189{
     1190  /* FIXME: Detach the interface from the upper layers? */
     1191
     1192  /* Module soft reset */
     1193  MAC_COMMAND = 0x38;
     1194  MAC_MAC1 = 0xcf00;
     1195
     1196  /* FIXME: More cleanup */
    11951197
    11961198  return 0;
     
    12051207
    12061208  if (attaching) {
    1207     return lpc24xx_eth_attach( config);
     1209    return lpc24xx_eth_attach(config);
    12081210  } else {
    1209     /* TODO */
    1210     return 0;
    1211   }
    1212 }
     1211    return lpc24xx_eth_detach(config);
     1212  }
     1213}
  • c/src/lib/libbsp/arm/lpc24xx/ssp/ssp.c

    rf90c5fb rba938b8  
    22 * @file
    33 *
    4  * @ingroup lpc24xx
     4 * @ingroup lpc24xx_libi2c
    55 *
    66 * @brief LibI2C bus driver for the Synchronous Serial Port (SSP).
     
    7575static uint32_t lpc24xx_ssp_trash = 0;
    7676
    77 static inline bool lpc24xx_ssp_is_busy( const lpc24xx_ssp_bus_entry *bus)
     77static inline bool lpc24xx_ssp_is_busy(const lpc24xx_ssp_bus_entry *bus)
    7878{
    7979  return lpc24xx_ssp_dma_data.bus == bus
     
    8181}
    8282
    83 static void lpc24xx_ssp_handler( rtems_vector_number vector, void *arg)
     83static void lpc24xx_ssp_handler(rtems_vector_number vector, void *arg)
    8484{
    8585  lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) arg;
     
    8888  uint32_t icr = 0;
    8989
    90   if (IS_FLAG_SET( mis, SSP_MIS_RORRIS)) {
     90  if (IS_FLAG_SET(mis, SSP_MIS_RORRIS)) {
    9191    /* TODO */
    92     printk( "%s: Receiver overrun!\n", __func__);
     92    printk("%s: Receiver overrun!\n", __func__);
    9393    icr |= SSP_ICR_RORRIS;
    9494  }
     
    9797}
    9898
    99 static void lpc24xx_ssp_dma_handler( rtems_vector_number vector, void *arg)
     99static void lpc24xx_ssp_dma_handler(rtems_vector_number vector, void *arg)
    100100{
    101101  lpc24xx_ssp_dma_entry *e = (lpc24xx_ssp_dma_entry *) arg;
     
    106106
    107107  /* Return if we are not in a transfer status */
    108   if (IS_FLAG_CLEARED( status, LPC24XX_SSP_DMA_TRANSFER_FLAG)) {
     108  if (IS_FLAG_CLEARED(status, LPC24XX_SSP_DMA_TRANSFER_FLAG)) {
    109109    return;
    110110  }
     
    122122    switch (status) {
    123123      case LPC24XX_SSP_DMA_WAIT:
    124         if (ARE_FLAGS_SET( tc, GPDMA_STATUS_CH_0 | GPDMA_STATUS_CH_1)) {
     124        if (ARE_FLAGS_SET(tc, GPDMA_STATUS_CH_0 | GPDMA_STATUS_CH_1)) {
    125125          status = LPC24XX_SSP_DMA_DONE;
    126         } else if (IS_FLAG_SET( tc, GPDMA_STATUS_CH_0)) {
     126        } else if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_0)) {
    127127          status = LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_1;
    128         } else if (IS_FLAG_SET( tc, GPDMA_STATUS_CH_1)) {
     128        } else if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_1)) {
    129129          status = LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_0;
    130130        }
    131131        break;
    132132      case LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_0:
    133         if (IS_FLAG_SET( tc, GPDMA_STATUS_CH_1)) {
     133        if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_1)) {
    134134          status = LPC24XX_SSP_DMA_ERROR;
    135         } else if (IS_FLAG_SET( tc, GPDMA_STATUS_CH_0)) {
     135        } else if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_0)) {
    136136          status = LPC24XX_SSP_DMA_DONE;
    137137        }
    138138        break;
    139139      case LPC24XX_SSP_DMA_WAIT_FOR_CHANNEL_1:
    140         if (IS_FLAG_SET( tc, GPDMA_STATUS_CH_0)) {
     140        if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_0)) {
    141141          status = LPC24XX_SSP_DMA_ERROR;
    142         } else if (IS_FLAG_SET( tc, GPDMA_STATUS_CH_1)) {
     142        } else if (IS_FLAG_SET(tc, GPDMA_STATUS_CH_1)) {
    143143          status = LPC24XX_SSP_DMA_DONE;
    144144        }
     
    154154  /* Error cleanup */
    155155  if (status == LPC24XX_SSP_DMA_ERROR) {
    156     lpc24xx_dma_channel_disable( 0, true);
    157     lpc24xx_dma_channel_disable( 1, true);
     156    lpc24xx_dma_channel_disable(0, true);
     157    lpc24xx_dma_channel_disable(1, true);
    158158    status = LPC24XX_SSP_DMA_DONE;
    159159    rv = -RTEMS_IO_ERROR;
     
    164164    status = LPC24XX_SSP_DMA_AVAILABLE;
    165165    if (e->done != NULL) {
    166       e->done( rv, e->n, e->arg);
     166      e->done(rv, e->n, e->arg);
    167167      e->done = NULL;
    168168    }
     
    173173}
    174174
    175 static rtems_status_code lpc24xx_ssp_init( rtems_libi2c_bus_t *bus)
     175static rtems_status_code lpc24xx_ssp_init(rtems_libi2c_bus_t *bus)
    176176{
    177177  rtems_status_code sc = RTEMS_SUCCESSFUL;
     
    188188
    189189    /* Test and set DMA support status */
    190     rtems_interrupt_disable( level);
     190    rtems_interrupt_disable(level);
    191191    status = lpc24xx_ssp_dma_data.status;
    192192    if (status == LPC24XX_SSP_DMA_NOT_INITIALIZED) {
    193193      lpc24xx_ssp_dma_data.status = LPC24XX_SSP_DMA_INITIALIZATION;
    194194    }
    195     rtems_interrupt_enable( level);
     195    rtems_interrupt_enable(level);
    196196
    197197    if (status == LPC24XX_SSP_DMA_NOT_INITIALIZED) {
     
    204204        &lpc24xx_ssp_dma_data
    205205      );
    206       RTEMS_CHECK_SC( sc, "Install DMA interrupt handler");
     206      RTEMS_CHECK_SC(sc, "install DMA interrupt handler");
    207207
    208208      /* Set DMA support status */
     
    217217  switch ((uintptr_t) regs) {
    218218    case SSP0_BASE_ADDR:
    219       rtems_interrupt_disable( level);
    220       PCLKSEL1 = SET_PCLKSEL1_PCLK_SSP0( PCLKSEL1, 1);
    221       rtems_interrupt_enable( level);
     219      rtems_interrupt_disable(level);
     220      PCLKSEL1 = SET_PCLKSEL1_PCLK_SSP0(PCLKSEL1, 1);
     221      rtems_interrupt_enable(level);
    222222
    223223      vector = LPC24XX_IRQ_SPI_SSP_0;
    224224      break;
    225225    case SSP1_BASE_ADDR:
    226       rtems_interrupt_disable( level);
    227       PCLKSEL0 = SET_PCLKSEL0_PCLK_SSP1( PCLKSEL0, 1);
    228       rtems_interrupt_enable( level);
     226      rtems_interrupt_disable(level);
     227      PCLKSEL0 = SET_PCLKSEL0_PCLK_SSP1(PCLKSEL0, 1);
     228      rtems_interrupt_enable(level);
    229229
    230230      vector = LPC24XX_IRQ_SSP_1;
     
    235235
    236236  /* Set serial clock rate to save value */
    237   regs->cr0 = SET_SSP_CR0_SCR( 0, 255);
     237  regs->cr0 = SET_SSP_CR0_SCR(0, 255);
    238238
    239239  /* Set clock prescaler */
     
    259259    e
    260260  );
    261   RTEMS_CHECK_SC( sc, "Install interrupt handler");
     261  RTEMS_CHECK_SC(sc, "install interrupt handler");
    262262
    263263  /* Enable receiver overrun interrupts */
     
    267267}
    268268
    269 static rtems_status_code lpc24xx_ssp_send_start( rtems_libi2c_bus_t *bus)
     269static rtems_status_code lpc24xx_ssp_send_start(rtems_libi2c_bus_t *bus)
    270270{
    271271  return RTEMS_SUCCESSFUL;
    272272}
    273273
    274 static rtems_status_code lpc24xx_ssp_send_stop( rtems_libi2c_bus_t *bus)
     274static rtems_status_code lpc24xx_ssp_send_stop(rtems_libi2c_bus_t *bus)
    275275{
    276276  lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) bus;
     
    279279  if (lpc24xx_ssp_dma_data.bus == e) {
    280280    if (lpc24xx_ssp_dma_data.status == LPC24XX_SSP_DMA_AVAILABLE) {
    281       lpc24xx_dma_channel_release( 0);
    282       lpc24xx_dma_channel_release( 1);
     281      lpc24xx_dma_channel_release(0);
     282      lpc24xx_dma_channel_release(1);
    283283      lpc24xx_ssp_dma_data.bus = NULL;
    284284    } else {
     
    298298  lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) bus;
    299299
    300   if (lpc24xx_ssp_is_busy( e)) {
     300  if (lpc24xx_ssp_is_busy(e)) {
    301301    return RTEMS_RESOURCE_IN_USE;
    302302  }
     
    316316  unsigned scr = (clk + br - 1) / br;
    317317
    318   if (lpc24xx_ssp_is_busy( e)) {
     318  if (lpc24xx_ssp_is_busy(e)) {
    319319    return -RTEMS_RESOURCE_IN_USE;
    320320  }
     
    364364  e->idle_char = mode->idle_char;
    365365
    366   while (IS_FLAG_CLEARED( regs->sr, SSP_SR_TFE)) {
     366  while (IS_FLAG_CLEARED(regs->sr, SSP_SR_TFE)) {
    367367    /* Wait */
    368368  }
    369369
    370   regs->cr0 = SET_SSP_CR0_DSS( 0, 0x7)
    371     | SET_SSP_CR0_SCR( 0, scr)
     370  regs->cr0 = SET_SSP_CR0_DSS(0, 0x7)
     371    | SET_SSP_CR0_SCR(0, scr)
    372372    | (mode->clock_inv ? SSP_CR0_CPOL : 0)
    373373    | (mode->clock_phs ? SSP_CR0_CPHA : 0);
     
    394394  unsigned char idle_char = (unsigned char) e->idle_char;
    395395
    396   if (lpc24xx_ssp_is_busy( e)) {
     396  if (lpc24xx_ssp_is_busy(e)) {
    397397    return -RTEMS_RESOURCE_IN_USE;
    398398  }
     
    427427
    428428    /* Write */
    429     if (IS_FLAG_SET( sr, SSP_SR_TNF) && m < LPC24XX_SSP_FIFO_SIZE) {
     429    if (IS_FLAG_SET(sr, SSP_SR_TNF) && m < LPC24XX_SSP_FIFO_SIZE) {
    430430      regs->dr = *out;
    431431      ++w;
     
    434434
    435435    /* Read */
    436     if (IS_FLAG_SET( sr, SSP_SR_RNE)) {
     436    if (IS_FLAG_SET(sr, SSP_SR_RNE)) {
    437437      *in = (unsigned char) regs->dr;
    438438      ++r;
     
    449449    do {
    450450      sr = regs->sr;
    451     } while (IS_FLAG_CLEARED( sr, SSP_SR_RNE));
     451    } while (IS_FLAG_CLEARED(sr, SSP_SR_RNE));
    452452
    453453    /* Read */
     
    473473  lpc24xx_ssp_bus_entry *e = (lpc24xx_ssp_bus_entry *) bus;
    474474  volatile lpc24xx_ssp *ssp = e->regs;
    475   volatile lpc24xx_dma_channel *receive_channel = GPDMA_CH_BASE_ADDR( 0);
    476   volatile lpc24xx_dma_channel *transmit_channel = GPDMA_CH_BASE_ADDR( 1);
     475  volatile lpc24xx_dma_channel *receive_channel = GPDMA_CH_BASE_ADDR(0);
     476  volatile lpc24xx_dma_channel *transmit_channel = GPDMA_CH_BASE_ADDR(1);
    477477  uint32_t di = GPDMA_CH_CTRL_DI;
    478478  uint32_t si = GPDMA_CH_CTRL_SI;
     
    484484  /* Try to reserve DMA support for this bus */
    485485  if (lpc24xx_ssp_dma_data.bus == NULL) {
    486     rtems_interrupt_disable( level);
     486    rtems_interrupt_disable(level);
    487487    if (lpc24xx_ssp_dma_data.bus == NULL) {
    488488      lpc24xx_ssp_dma_data.bus = e;
    489489    }
    490     rtems_interrupt_enable( level);
     490    rtems_interrupt_enable(level);
    491491
    492492    /* Try to obtain DMA channels */
    493493    if (lpc24xx_ssp_dma_data.bus == e) {
    494       bool channel_0 = lpc24xx_dma_channel_obtain( 0);
    495       bool channel_1 = lpc24xx_dma_channel_obtain( 1);
    496 
    497       if (!channel_0 && channel_1) {
    498         lpc24xx_dma_channel_release( 1);
    499         lpc24xx_ssp_dma_data.bus = NULL;
    500       } else if (channel_0 && !channel_1) {
    501         lpc24xx_dma_channel_release( 0);
    502         lpc24xx_ssp_dma_data.bus = NULL;
    503       } else if (!channel_0 || !channel_1) {
     494      rtems_status_code cs0 = lpc24xx_dma_channel_obtain(0);
     495      rtems_status_code cs1 = lpc24xx_dma_channel_obtain(1);
     496
     497      if (cs0 != RTEMS_SUCCESSFUL || cs1 != RTEMS_SUCCESSFUL) {
     498        if (cs0 == RTEMS_SUCCESSFUL) {
     499          lpc24xx_dma_channel_release(0);
     500        }
     501        if (cs1 == RTEMS_SUCCESSFUL) {
     502          lpc24xx_dma_channel_release(1);
     503        }
    504504        lpc24xx_ssp_dma_data.bus = NULL;
    505505      }
     
    524524  /* Receive */
    525525  if (in != NULL) {
    526     receive_channel->dest = (uint32_t) in;
     526    receive_channel->desc.dest = (uint32_t) in;
    527527  } else {
    528     receive_channel->dest = (uint32_t) &lpc24xx_ssp_trash;
     528    receive_channel->desc.dest = (uint32_t) &lpc24xx_ssp_trash;
    529529    di = 0;
    530530  }
    531   receive_channel->src = (uint32_t) &ssp->dr;
    532   receive_channel->lli = 0;
    533   receive_channel->ctrl = SET_GPDMA_CH_CTRL_TSZ( 0, n)
    534     | SET_GPDMA_CH_CTRL_SBSZ( 0, GPDMA_CH_CTRL_BSZ_4)
    535     | SET_GPDMA_CH_CTRL_DBSZ( 0, GPDMA_CH_CTRL_BSZ_4)
    536     | SET_GPDMA_CH_CTRL_SW( 0, GPDMA_CH_CTRL_W_8)
    537     | SET_GPDMA_CH_CTRL_DW( 0, GPDMA_CH_CTRL_W_8)
     531  receive_channel->desc.src = (uint32_t) &ssp->dr;
     532  receive_channel->desc.lli = 0;
     533  receive_channel->desc.ctrl = SET_GPDMA_CH_CTRL_TSZ(0, n)
     534    | SET_GPDMA_CH_CTRL_SBSZ(0, GPDMA_CH_CTRL_BSZ_4)
     535    | SET_GPDMA_CH_CTRL_DBSZ(0, GPDMA_CH_CTRL_BSZ_4)
     536    | SET_GPDMA_CH_CTRL_SW(0, GPDMA_CH_CTRL_W_8)
     537    | SET_GPDMA_CH_CTRL_DW(0, GPDMA_CH_CTRL_W_8)
    538538    | GPDMA_CH_CTRL_ITC
    539539    | di;
    540   receive_channel->cfg = SET_GPDMA_CH_CFG_SRCPER( 0, GPDMA_CH_CFG_PER_SSP1_RX)
    541     | SET_GPDMA_CH_CFG_FLOW( 0, GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA)
     540  receive_channel->cfg = SET_GPDMA_CH_CFG_SRCPER(0, GPDMA_CH_CFG_PER_SSP1_RX)
     541    | SET_GPDMA_CH_CFG_FLOW(0, GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA)
    542542    | GPDMA_CH_CFG_IE
    543543    | GPDMA_CH_CFG_ITC
     
    546546  /* Transmit */
    547547  if (out != NULL) {
    548     transmit_channel->src = (uint32_t) out;
     548    transmit_channel->desc.src = (uint32_t) out;
    549549  } else {
    550     transmit_channel->src = (uint32_t) &e->idle_char;
     550    transmit_channel->desc.src = (uint32_t) &e->idle_char;
    551551    si = 0;
    552552  }
    553   transmit_channel->dest = (uint32_t) &ssp->dr;
    554   transmit_channel->lli = 0;
    555   transmit_channel->ctrl = SET_GPDMA_CH_CTRL_TSZ( 0, n)
    556     | SET_GPDMA_CH_CTRL_SBSZ( 0, GPDMA_CH_CTRL_BSZ_4)
    557     | SET_GPDMA_CH_CTRL_DBSZ( 0, GPDMA_CH_CTRL_BSZ_4)
    558     | SET_GPDMA_CH_CTRL_SW( 0, GPDMA_CH_CTRL_W_8)
    559     | SET_GPDMA_CH_CTRL_DW( 0, GPDMA_CH_CTRL_W_8)
     553  transmit_channel->desc.dest = (uint32_t) &ssp->dr;
     554  transmit_channel->desc.lli = 0;
     555  transmit_channel->desc.ctrl = SET_GPDMA_CH_CTRL_TSZ(0, n)
     556    | SET_GPDMA_CH_CTRL_SBSZ(0, GPDMA_CH_CTRL_BSZ_4)
     557    | SET_GPDMA_CH_CTRL_DBSZ(0, GPDMA_CH_CTRL_BSZ_4)
     558    | SET_GPDMA_CH_CTRL_SW(0, GPDMA_CH_CTRL_W_8)
     559    | SET_GPDMA_CH_CTRL_DW(0, GPDMA_CH_CTRL_W_8)
    560560    | GPDMA_CH_CTRL_ITC
    561561    | si;
    562   transmit_channel->cfg = SET_GPDMA_CH_CFG_DESTPER( 0, GPDMA_CH_CFG_PER_SSP1_TX)
    563     | SET_GPDMA_CH_CFG_FLOW( 0, GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA)
     562  transmit_channel->cfg = SET_GPDMA_CH_CFG_DESTPER(0, GPDMA_CH_CFG_PER_SSP1_TX)
     563    | SET_GPDMA_CH_CFG_FLOW(0, GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA)
    564564    | GPDMA_CH_CFG_IE
    565565    | GPDMA_CH_CFG_ITC
     
    569569}
    570570
    571 static int lpc24xx_ssp_read( rtems_libi2c_bus_t *bus, unsigned char *in, int n)
    572 {
    573   return lpc24xx_ssp_read_write( bus, in, NULL, n);
     571static int lpc24xx_ssp_read(rtems_libi2c_bus_t *bus, unsigned char *in, int n)
     572{
     573  return lpc24xx_ssp_read_write(bus, in, NULL, n);
    574574}
    575575
     
    580580)
    581581{
    582   return lpc24xx_ssp_read_write( bus, NULL, out, n);
    583 }
    584 
    585 static int lpc24xx_ssp_ioctl( rtems_libi2c_bus_t *bus, int cmd, void *arg)
     582  return lpc24xx_ssp_read_write(bus, NULL, out, n);
     583}
     584
     585static int lpc24xx_ssp_ioctl(rtems_libi2c_bus_t *bus, int cmd, void *arg)
    586586{
    587587  int rv = -1;
     
    593593  switch (cmd) {
    594594    case RTEMS_LIBI2C_IOCTL_READ_WRITE:
    595       rv = lpc24xx_ssp_read_write( bus, rw->rd_buf, rw->wr_buf, rw->byte_cnt);
     595      rv = lpc24xx_ssp_read_write(bus, rw->rd_buf, rw->wr_buf, rw->byte_cnt);
    596596      break;
    597597    case RTEMS_LIBI2C_IOCTL_READ_WRITE_ASYNC:
     
    606606      break;
    607607    case RTEMS_LIBI2C_IOCTL_SET_TFRMODE:
    608       rv = lpc24xx_ssp_set_transfer_mode( bus, tm);
     608      rv = lpc24xx_ssp_set_transfer_mode(bus, tm);
    609609      break;
    610610    default:
     
    631631    .bus = {
    632632      .ops = &lpc24xx_ssp_ops,
    633       .size = sizeof( lpc24xx_ssp_bus_entry)
     633      .size = sizeof(lpc24xx_ssp_bus_entry)
    634634    },
    635635    .regs = (volatile lpc24xx_ssp *) SSP0_BASE_ADDR,
     
    640640    .bus = {
    641641      .ops = &lpc24xx_ssp_ops,
    642       .size = sizeof( lpc24xx_ssp_bus_entry)
     642      .size = sizeof(lpc24xx_ssp_bus_entry)
    643643    },
    644644    .regs = (volatile lpc24xx_ssp *) SSP1_BASE_ADDR,
  • c/src/lib/libbsp/arm/lpc24xx/startup/bspstart.c

    rf90c5fb rba938b8  
    88
    99/*
    10  * Copyright (c) 2008
    11  * Embedded Brains GmbH
     10 * Copyright (c) 2008, 2009
     11 * embedded brains GmbH
    1212 * Obere Lagerstr. 30
    1313 * D-82178 Puchheim
    1414 * Germany
    15  * rtems@embedded-brains.de
     15 * <rtems@embedded-brains.de>
    1616 *
    17  * The license and distribution terms for this file may be found in the file
    18  * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
     17 * The license and distribution terms for this file may be
     18 * found in the file LICENSE in this distribution or at
     19 * http://www.rtems.com/license/LICENSE.
    1920 */
    20 
    21 #include <string.h>
    2221
    2322#include <bsp.h>
     
    3029#include <bsp/lpc24xx.h>
    3130#include <bsp/stackalloc.h>
    32 #include <bsp/start.h>
    3331#include <bsp/system-clocks.h>
    3432
    35 static void lpc24xx_fatal_error( void)
     33void bsp_start(void)
    3634{
    37   while (true) {
    38     /* Spin forever */
    39   }
    40 }
     35  /* Initialize Timer 1 */
     36  lpc24xx_module_enable(LPC24XX_MODULE_TIMER, 1, LPC24XX_MODULE_CCLK);
    4137
    42 static void lpc24xx_ram_test_32( void)
    43 {
    44   const unsigned *end = (const unsigned *) bsp_region_data_end;
    45   unsigned *begin = (unsigned *) bsp_region_data_begin;
    46   unsigned *out = begin;
     38  /* Initialize standard timer */
     39  lpc24xx_timer_initialize();
    4740
    48   while (out != end) {
    49     *out = (unsigned) out;
    50     ++out;
    51   }
    52 
    53   out = begin;
    54   while (out != end) {
    55     if (*out != (unsigned) out) {
    56       lpc24xx_fatal_error();
    57     }
    58     ++out;
    59   }
    60 }
    61 
    62 /**
    63  * @brief EMC initialization.
    64  *
    65  * Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT
    66  */
    67 static void lpc24xx_init_emc( void)
    68 {
    69   #ifdef LPC24XX_EMC_MICRON
    70     int i = 0;
    71     uint32_t mode = 0;
    72 
    73     /* Enable module power */
    74     lpc24xx_module_enable( LPC24XX_MODULE_EMC, 0, LPC24XX_MODULE_PCLK_DEFAULT);
    75 
    76     /* IO configuration */
    77     lpc24xx_io_config( LPC24XX_MODULE_EMC, 0, 0);
    78 
    79     /* Enable module, normal memory map and normal power mode */
    80     EMC_CTRL = 1;
    81 
    82     /* Use little-endian mode and 1:1 clock ratio */
    83     EMC_CONFIG = 0;
    84 
    85     /* Global dynamic settings */
    86 
    87     /* FIXME */
    88     EMC_DYN_APR = 2;
    89 
    90     /* Data-in to active command period tWR + tRP */
    91     EMC_DYN_DAL = 4;
    92 
    93     /* Load mode register to active or refresh command period 2 tCK */
    94     EMC_DYN_MRD = 1;
    95 
    96     /* Active to precharge command period 44 ns */
    97     EMC_DYN_RAS = 3;
    98 
    99     /* Active to active command period 66 ns */
    100     EMC_DYN_RC = 4;
    101 
    102     /* Use command delayed strategy */
    103     EMC_DYN_RD_CFG = 1;
    104 
    105     /* Auto refresh period 66 ns */
    106     EMC_DYN_RFC = 4;
    107 
    108     /* Precharge command period 20 ns */
    109     EMC_DYN_RP = 1;
    110 
    111     /* Active bank a to active bank b command period 15 ns */
    112     EMC_DYN_RRD = 1;
    113 
    114     /* FIXME */
    115     EMC_DYN_SREX = 5;
    116 
    117     /* Write recovery time 15 ns */
    118     EMC_DYN_WR = 1;
    119 
    120     /* Exit self refresh to active command period 75 ns */
    121     EMC_DYN_XSR = 5;
    122 
    123     /* Dynamic Memory 0 settings */
    124 
    125     /*
    126      * Use SDRAM, 0 0 001 01 address mapping, disabled buffer, unprotected writes
    127      */
    128     EMC_DYN_CFG0 = 0x0280;
    129 
    130     /* CAS and RAS latency */
    131     EMC_DYN_RASCAS0 = 0x0202;
    132 
    133     /* Wait 50 micro seconds */
    134     lpc24xx_micro_seconds_delay( 50);
    135 
    136     /* Send command: NOP */
    137     EMC_DYN_CTRL = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS | EMC_DYN_CTRL_CMD_NOP;
    138 
    139     /* Wait 50 micro seconds */
    140     lpc24xx_micro_seconds_delay( 50);
    141 
    142     /* Send command: PRECHARGE ALL */
    143     EMC_DYN_CTRL = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS | EMC_DYN_CTRL_CMD_PALL;
    144 
    145     /* Shortest possible refresh period */
    146     EMC_DYN_RFSH = 0x01;
    147 
    148     /* Wait at least 128 ABH clock cycles */
    149     for (i = 0; i < 128; ++i) {
    150       asm volatile (" nop");
    151     }
    152 
    153     /* Wait 1 micro second */
    154     lpc24xx_micro_seconds_delay( 1);
    155 
    156     /* Set refresh period */
    157     EMC_DYN_RFSH = 0x46;
    158 
    159     /* Send command: MODE */
    160     EMC_DYN_CTRL = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS | EMC_DYN_CTRL_CMD_MODE;
    161 
    162     /* Set mode registerin SDRAM */
    163     mode = *((volatile uint32_t *) (0xa0000000 | (0x23 << (1 + 2 + 8))));
    164 
    165     /* Send command: NORMAL */
    166     EMC_DYN_CTRL = 0;
    167 
    168     /* Enable buffer */
    169     EMC_DYN_CFG0 |= 0x00080000;
    170 
    171     /* Extended wait register */
    172     EMC_STA_EXT_WAIT = 0;
    173 
    174     /* Static Memory 1 settings */
    175     EMC_STA_WAITWEN1 = 0x02;
    176     EMC_STA_WAITOEN1 = 0x02;
    177     EMC_STA_WAITRD1 = 0x08;
    178     EMC_STA_WAITPAGE1 = 0x1f;
    179     EMC_STA_WAITWR1 = 0x08;
    180     EMC_STA_WAITTURN1 = 0x0f;
    181     EMC_STA_CFG1 = 0x81;
    182 
    183     /* RAM test */
    184     lpc24xx_ram_test_32();
     41  /* Initialize console */
     42  #ifdef LPC24XX_CONFIG_CONSOLE
     43    lpc24xx_module_enable(LPC24XX_MODULE_UART, 0, LPC24XX_MODULE_CCLK);
     44    lpc24xx_io_config(LPC24XX_MODULE_UART, 0, LPC24XX_CONFIG_CONSOLE);
     45    U0LCR = 0;
     46    U0IER = 0;
     47    U0LCR = 0x80;
     48    U0DLL = lpc24xx_cclk() / 16 / LPC24XX_UART_BAUD;
     49    U0DLM = 0;
     50    U0LCR = 0x03;
     51    U0FCR = 0x07;
    18552  #endif
    186 }
    187 
    188 static void lpc24xx_init_pll( void)
    189 {
    190   #ifndef LPC24XX_HAS_UBOOT
    191     /* Enable main oscillator */
    192     SCS = SET_FLAG( SCS, 0x20);
    193     while (IS_FLAG_CLEARED( SCS, 0x40)) {
    194       /* Wait */
    195     }
    196 
    197     /* Set PLL */
    198     lpc24xx_set_pll( 1, 0, 11, 3);
    199   #endif
    200 }
    201 
    202 void /* __attribute__ ((section (".entry"))) */ bsp_start_hook_0( void)
    203 {
    204   /* Initialize PLL */
    205   lpc24xx_init_pll();
    206 
    207   #ifndef LPC24XX_HAS_UBOOT
    208     /* Set pin functions  */
    209     PINSEL0 = 0;
    210     PINSEL1 = 0;
    211     PINSEL2 = 0;
    212     PINSEL3 = 0;
    213     PINSEL4 = 0;
    214     PINSEL5 = 0;
    215     PINSEL6 = 0;
    216     PINSEL7 = 0;
    217     PINSEL8 = 0;
    218     PINSEL9 = 0;
    219     PINSEL10 = 0;
    220     PINSEL11 = 0;
    221 
    222     /* Set pin modes  */
    223     PINMODE0 = 0;
    224     PINMODE1 = 0;
    225     PINMODE2 = 0;
    226     PINMODE3 = 0;
    227     PINMODE4 = 0;
    228     PINMODE5 = 0;
    229     PINMODE6 = 0;
    230     PINMODE7 = 0;
    231     PINMODE8 = 0;
    232     PINMODE9 = 0;
    233 
    234     /* Set periperal clocks */
    235     PCLKSEL0 = 0;
    236     PCLKSEL1 = 0;
    237 
    238     /* Disable power for all modules */
    239     PCONP = 0;
    240 
    241     /* Set memory accelerator module (MAM) */
    242     MAMCR = 0;
    243     MAMTIM = 4;
    244 
    245     /* Enable fast IO for ports 0 and 1 */
    246     SCS = SET_FLAG( SCS, 0x1);
    247 
    248     /* Set fast IO */
    249     FIO0DIR = 0;
    250     FIO1DIR = 0;
    251     FIO2DIR = 0;
    252     FIO3DIR = 0;
    253     FIO4DIR = 0;
    254     FIO0CLR = 0xffffffff;
    255     FIO1CLR = 0xffffffff;
    256     FIO2CLR = 0xffffffff;
    257     FIO3CLR = 0xffffffff;
    258     FIO4CLR = 0xffffffff;
    259 
    260     /* Initialize console */
    261     #ifdef LPC24XX_CONFIG_CONSOLE
    262       lpc24xx_module_enable( LPC24XX_MODULE_UART, 0, LPC24XX_MODULE_CCLK);
    263       lpc24xx_io_config( LPC24XX_MODULE_UART, 0, LPC24XX_CONFIG_CONSOLE);
    264       U0LCR = 0;
    265       U0IER = 0;
    266       U0LCR = 0x80;
    267       U0DLL = lpc24xx_cclk() / 16 / LPC24XX_UART_BAUD;
    268       U0DLM = 0;
    269       U0LCR = 0x03;
    270       U0FCR = 0x07;
    271     #endif
    272 
    273     /* Initialize Timer 1 */
    274     lpc24xx_module_enable( LPC24XX_MODULE_TIMER, 1, LPC24XX_MODULE_CCLK);
    275   #endif
    276 }
    277 
    278 static void lpc24xx_copy_data( void)
    279 {
    280   #ifndef LPC24XX_HAS_UBOOT
    281     const unsigned *end = (const unsigned *) bsp_section_data_end;
    282     unsigned *in = (unsigned *) bsp_section_data_load_begin;
    283     unsigned *out = (unsigned *) bsp_section_data_begin;
    284 
    285     /* Copy data */
    286     while (out != end) {
    287       *out = *in;
    288       ++out;
    289       ++in;
    290     }
    291   #endif
    292 }
    293 
    294 static void lpc24xx_clear_bss( void)
    295 {
    296   const unsigned *end = (const unsigned *) bsp_section_bss_end;
    297   unsigned *out = (unsigned *) bsp_section_bss_begin;
    298 
    299   /* Clear BSS */
    300   while (out != end) {
    301     *out = 0;
    302     ++out;
    303   }
    304 }
    305 
    306 void /* __attribute__ ((section (".entry"))) */ bsp_start_hook_1( void)
    307 {
    308   /* Re-map interrupt vectors to internal RAM */
    309   MEMMAP = SET_MEMMAP_MAP( MEMMAP, 2);
    310 
    311   /* Initialize External Memory Controller (EMC) */
    312   lpc24xx_init_emc();
    313 
    314   /* Copy data */
    315   lpc24xx_copy_data();
    316 
    317   /* Clear BSS */
    318   lpc24xx_clear_bss();
    319 }
    320 
    321 void bsp_start( void)
    322 {
    323   printk( "CPU clock (CCLK): %u\n", lpc24xx_cclk());
    324 
    325   /* Exceptions */
    326   /* FIXME
    327   rtems_exception_init_mngt();
    328   */
    32953
    33054  /* Interrupts */
    33155  if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
    332     /* FIXME */
    333     printk( "cannot intitialize interrupt support\n");
    334     lpc24xx_fatal_error();
     56    _CPU_Fatal_halt(0xe);
    33557  }
    33658
     
    34163  bsp_stack_initialize(
    34264    bsp_section_stack_begin,
    343     (intptr_t) bsp_section_stack_size
     65    (uintptr_t) bsp_section_stack_size
    34466  );
    34567
    34668  /* UART configurations */
    34769  #ifdef LPC24XX_CONFIG_UART_1
    348     lpc24xx_module_enable( LPC24XX_MODULE_UART, 1, LPC24XX_MODULE_CCLK);
    349     lpc24xx_io_config( LPC24XX_MODULE_UART, 1, LPC24XX_CONFIG_UART_1);
     70    lpc24xx_module_enable(LPC24XX_MODULE_UART, 1, LPC24XX_MODULE_CCLK);
     71    lpc24xx_io_config(LPC24XX_MODULE_UART, 1, LPC24XX_CONFIG_UART_1);
    35072  #endif
    35173  #ifdef LPC24XX_CONFIG_UART_2
    352     lpc24xx_module_enable( LPC24XX_MODULE_UART, 2, LPC24XX_MODULE_CCLK);
    353     lpc24xx_io_config( LPC24XX_MODULE_UART, 2, LPC24XX_CONFIG_UART_2);
     74    lpc24xx_module_enable(LPC24XX_MODULE_UART, 2, LPC24XX_MODULE_CCLK);
     75    lpc24xx_io_config(LPC24XX_MODULE_UART, 2, LPC24XX_CONFIG_UART_2);
    35476  #endif
    35577  #ifdef LPC24XX_CONFIG_UART_3
    356     lpc24xx_module_enable( LPC24XX_MODULE_UART, 3, LPC24XX_MODULE_CCLK);
    357     lpc24xx_io_config( LPC24XX_MODULE_UART, 3, LPC24XX_CONFIG_UART_3);
     78    lpc24xx_module_enable(LPC24XX_MODULE_UART, 3, LPC24XX_MODULE_CCLK);
     79    lpc24xx_io_config(LPC24XX_MODULE_UART, 3, LPC24XX_CONFIG_UART_3);
    35880  #endif
    35981}
     
    36183#define ULSR_THRE 0x00000020U
    36284
    363 static void lpc24xx_BSP_output_char( char c)
     85static void lpc24xx_BSP_output_char(char c)
    36486{
    365   while (IS_FLAG_CLEARED( U0LSR, ULSR_THRE)) {
     87  while (IS_FLAG_CLEARED(U0LSR, ULSR_THRE)) {
    36688    /* Wait */
    36789  }
     
    36991
    37092  if (c == '\n') {
    371     while (IS_FLAG_CLEARED( U0LSR, ULSR_THRE)) {
     93    while (IS_FLAG_CLEARED(U0LSR, ULSR_THRE)) {
    37294      /* Wait */
    37395    }
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