Changeset ba46ffa6 in rtems


Ignore:
Timestamp:
06/14/99 16:51:13 (24 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
a4f6b02
Parents:
255b293
Message:

This is a large patch from Eric Valette <valette@…> that was
described in the message following this paragraph. This patch also includes
a mcp750 BSP.

From valette@… Mon Jun 14 10:03:08 1999
Date: Tue, 18 May 1999 01:30:14 +0200 (CEST)
From: VALETTE Eric <valette@…>
To: joel@…
Cc: raguet@…, rtems-snapshots@…, valette@…
Subject: Questions/Suggestion? regarding RTEMS PowerPC code (long)

Dear knowledgeable RTEMS powerpc users,

As some of you may know, I'm currently finalizing a port
of RTEMS on a MCP750 Motorola board. I have done most
of it but have some questions to ask before submitting
the port.

In order to understand some of the changes I have made
or would like to make, maybe it is worth describing the
MCP750 Motorola board.

the MCP750 is a COMPACT PCI powerpc board with :

1) a MPC750 233 MHz processor,
2) a raven bus bridge/PCI controller that
implement an OPENPIC compliant interrupt controller,
3) a VIA 82C586 PCI/ISA bridge that offers a PC
compliant IO for keyboard, serial line, IDE, and
the well known PC 8259 cascaded PIC interrupt
architecture model,
4) a DEC 21140 Ethernet controller,
5) the PPCBUG Motorola firmware in flash,
6) A DEC PCI bridge,

This architecture is common to most Motorola 60x/7xx
board except that :

1) on VME board, the DEC PCI bridge is replaced by
a VME chipset,
2) the VIA 82C586 PCI/ISA bridge is replaced by
another bridge that is almost fully compatible
with the via bridge...

So the port should be a rather close basis for many
60x/7xx motorola board...

On this board, I already have ported Linux 2.2.3 and
use it both as a development and target board.

Now the questions/suggestions I have :

1) EXCEPTION CODE

As far as I know exceptions on PPC are handled like
interrupts. I dislike this very much as :

a) Except for the decrementer exception (and
maybe some other on mpc8xx), exceptions are
not recoverable and the handler just need to print
the full context and go to the firmware or debugger...
b) The interrupt switch is only necessary for the
decrementer and external interrupt (at least on
6xx,7xx).
c) The full context for exception is never saved and
thus cannot be used by debugger... I do understand
the most important for interrupts low level code
is to save the minimal context enabling to call C
code for performance reasons. On non recoverable
exception on the other hand, the most important is
to save the maximum information concerning proc status
in order to analyze the reason of the fault. At
least we will need this in order to implement the
port of RGDB on PPC

==> I wrote an API for connecting raw exceptions (and thus
raw interrupts) for mpc750. It should be valid for most
powerpc processors... I hope to find a way to make this coexist
with actual code layout. The code is actually located
in lib/libcpu/powerpc/mpc750 and is thus optional
(provided I write my own version of exec/score/cpu/powerpc/cpu.c ...)

See remark about files/directory layout organization in 4)

2) Current Implementation of ISR low level code

I do not understand why the MSR EE flags is cleared
again in exec/score/cpu/powerpc/irq_stubs.S

#if (PPC_USE_SPRG)

mfmsr r5
mfspr r6, sprg2

#else

lwz r6,msr_initial(r11)
lis r5,~PPC_MSR_DISABLE_MASK@ha
ori r5,r5,~PPC_MSR_DISABLE_MASK@l
and r6,r6,r5
mfmsr r5

#endif

Reading the doc, when a decrementer interrupt or an
external interrupt is active, the MSR EE flag is already
cleared. BTW if exception/interrupt could occur, it would
trash SRR0 and SRR1. In fact the code may be useful to set
MSR[RI] that re-enables exception processing. BTW I will need
to set other value in MSR to handle interrupts :

a) I want the MSR[IR] and MSR[DR] to be set for
performance reasons and also because I need DBAT
support to have access to PCI memory space as the
interrupt controller is in the PCI space.

Reading the code, I see others have the same kind of request :

/* SCE 980217

*

  • We need address translation ON when we call our ISR routine

mtmsr r5

*/

This is just another prof that even the lowest level
IRQ code is fundamentally board dependent and
not simply processor dependent especially when
the processor use external interrupt controller
because it has a single interrupt request line...

Note that if you look at the PPC code high level interrupt
handling code, as the "set_vector" routine that really connects
the interrupt is in the BSP/startup/genpvec.c,
the fact that IRQ handling is BSP specific is DE-FACTO
acknowledged.

I know I have already expressed this and understand that this
would require some heavy change in the code but believe
me you will reach a point where you will not be able
to find a compatible while optimum implementation for low level
interrupt handling code...) In my case this is already true...

So please consider removing low level IRQ handling from
exec/score/cpu/* and only let there exception handling code...
Exceptions are usually only processor dependent and do
not depend on external hardware mechanism to be masked or
acknowledged or re-enabled (there are probably exception but ...)

I have already done this for pc386 bsp but need to make it again.
This time I will even propose an API.

3) R2/R13 manipulation for EABI implementation

I do not understand the handling of r2 and r13 in the
EABI case. The specification for r2 says pointer to sdata2,
sbss2 section => constant. However I do not see -ffixed-r2
passed to any compilation system in make/custom/*
(for info linux does this on PPC).

So either this is a default compiler option when choosing
powerpc-rtems and thus we do not need to do anything with
this register as all the code is compiled with this compiler
and linked together OR this register may be used by rtems code
and then we do not need any special initialization or
handling.

The specification for r13 says pointer to the small data
area. r13 argumentation is the same except that as far
as I know the usage of the small data area requires
specific compiler support so that access to variables is
compiled via loading the LSB in a register and then
using r13 to get full address... It is like a small
memory model and it was present in IBM C compilers.

=> I propose to suppress any specific code for r2 and
r13 in the EABI case.

4) Code layout organization (yes again :-))

I think there are a number of design flaws in the way
the code is for ppc organized and I will try to point them out.
I have been beaten by this again on this new port, and
was beaten last year while modifying code for pc386.

a) exec/score/cpu/* vs lib/libcpu/cpu/*.

I think that too many things are put in exec/score/cpu that
have nothing to do with RTEMS internals but are rather
related to CPU feature.

This include at least :

a) registers access routine (e.g GET_MSR_Value),
b) interrupt masking/unmasking routines,
c) cache_mngt_routine,
d) mmu_mngt_routine,
e) Routines to connect the raw_exception, raw_interrupt
handler,

b) lib/libcpu/cpu/powerpc/*

With a processor family as exuberant as the powerpc family,
and their well known subtle differences (604 vs 750) or
unfortunately majors (8xx vs 60x) the directory structure
is fine (except maybe the names that are not homogeneous)

powerpc

ppc421 mpc821 ...

I only needed to add mpc750. But the fact that libcpu.a was not
produced was a pain and the fact that this organization may
duplicates code is also problematic.

So, except if the support of automake provides a better solution
I would like to propose something like this :

powerpc

mpc421 mpc821 ... mpc750 shared wrapup

with the following rules :

a) "shared" would act as a source container for sources that may
be shared among processors. Needed files would be compiled inside
the processor specific directory using the vpath Makefile
mechanism. "shared" may also contain compilation code
for routine that are really shared and not worth to inline...
(did not found many things so far as registers access routine
ARE WORTH INLINING)... In the case something is compiled there,
it should create libcpushared.a

b) layout under processor specific directory is free provided
that

1)the result of the compilation process exports :

libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu

2) each processor specific directory creates
a library called libcpuspecific.a

Note that this organization enables to have a file that
is nearly the same than in shared but that must differ
because of processor differences...

c) "wrapup" should create libcpu.a using libcpushared.a
libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu

The only thing I have no ideal solution is the way to put shared
definitions in "shared" and only processor specific definition
in "proc". To give a concrete example, most MSR bit definition
are shared among PPC processors and only some differs. if we create
a single msr.h in shared it will have ifdef. If in msr.h we
include libcpu/msr_c.h we will need to have it in each prowerpc
specific directory (even empty). Opinions are welcomed ...

Note that a similar mechanism exist in libbsp/i386 that also
contains a shared directory that is used by several bsp
like pc386 and i386ex and a similar wrapup mechanism...

NB: I have done this for mpc750 and other processors could just use
similar Makefiles...

c) The exec/score/cpu/powerpc directory layout.

I think the directory layout should be the same than the
libcpu/powerpc. As it is not, there are a lot of ifdefs
inside the code... And of course low level interrupt handling
code should be removed...

Besides that I do not understand why

1) things are compiled in the wrap directory,
2) some includes are moved to rtems/score,

I think the "preinstall" mechanism enables to put
everything in the current directory (or better in a per processor
directory),

5) Interrupt handling API

Again :-). But I think that using all the features the PIC
offers is a MUST for RT system. I already explained in the
prologue of this (long and probably boring) mail that the MCP750
boards offers an OPENPIC compliant architecture and that
the VIA 82586 PCI/ISA bridge offers a PC compatible IO and
PIC mapping. Here is a logical view of the RAVEN/VIA 82586
interrupt mapping :

| OPEN | <-----|8259|
| PIC | | | 2 ------
|(RAVEN)| | | <-----|8259|
| | | | | | 11
| | | | | | <----
| | | | | |
| | | | | |

------
| VIA PCI/ISA bridge
| x
-------- PCI interrupts

OPENPIC offers interrupt priorities among PCI interrupts
and interrupt selective masking. The 8259 offers the same kind
of feature. With actual powerpc interrupt code :

1) there is no way to specify priorities among
interrupts handler. This is REALLY a bad thing.
For me it is as importnat as having priorities
for threads...
2) for my implementation, each ISR should
contain the code that acknowledge the RAVEN
and 8259 cascade, modify interrupt mask on both
chips, and reenable interrupt at processor level,
..., restore then on interrupt return,.... This code
is actually similar to code located in some
genpvec.c powerpc files,
3) I must update _ISR_Nesting_level because
irq.inl use it...
4) the libchip code connects the ISR via set_vector
but the libchip handler code does not contain any code to
manipulate external interrupt controller hardware
in order to acknoledge the interrupt or re-enable
them (except for the target hardware of course)
So this code is broken unless set_vector adds an
additionnal prologue/epilogue before calling/returning
from in order to acknoledge/mask the raven and the
8259 PICS... => Anyway already EACH BSP MUST REWRITE
PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT
SET_VECTOR.

I would rather offer an API similar to the one provided
in libbsp/i386/shared/irq/irq.h so that :

1) Once the driver supplied methods is called the
only things the ISR has to do is to worry about the
external hardware that triggered the interrupt.
Everything on openpic/VIA/processor would have been
done by the low levels (same things as set-vector)
2) The caller will need to supply the on/off/isOn
routine that are fundamental to correctly implements
debuggers/performance monitoring is a portable way
3) A globally configurable interrupt priorities
mechanism...

I have nothing against providing a compatible
set_vector just to make libchip happy but
as I have already explained in other
mails (months ago), I really think that the ISR
connection should be handled by the BSP and that no
code containing irq connection should exist the
rtems generic layers... Thus I really dislike
libchip on this aspect because in a long term
it will force to adopt the less reach API
for interrupt handling that exists (set_vector).

Additional note : I think the _ISR_Is_in_progress()
inline routine should be :

1) Put in a processor specific section,
2) Should not rely on a global variable,

As :

a) on symmetric MP, there is one interrupt level
per CPU,
b) On processor that have an ISP (e,g 68040),
this variable is useless (MSR bit testing could
be used)
c) On PPC, instead of using the address of the
variable via CPU_IRQ_info.Nest_level a dedicated
SPR could be used.

NOTE: most of this is also true for _Thread_Dispatch_disable_level

END NOTE

Please do not take what I said in the mail as a criticism for
anyone who submitted ppc code. Any code present helped me
a lot understanding PPC behavior. I just wanted by this
mail to :

1) try to better understand the actual code,
2) propose concrete ways of enhancing current code
by providing an alternative implementation for MCP750. I
will make my best effort to try to brake nothing but this
is actually hard due to the file layout organisation.
3) make understandable some changes I will probably make
if joel let me do them :-)

Any comments/objections are welcomed as usual.

--


/ ` Eric Valette

/-- o _. Canon CRF

(_, / (_(_( Rue de la touche lambert

35517 Cesson-Sevigne Cedex
FRANCE

Tel: +33 (0)2 99 87 68 91 Fax: +33 (0)2 99 84 11 30
E-mail: valette@…

Files:
139 added
2 deleted
10 edited
11 moved

Legend:

Unmodified
Added
Removed

  • c/src/exec/score/cpu/powerpc/Makefile.in

    r255b293 rba46ffa6  
    11#
     2# $Id$
     3#
     4#       
    25#  $Id$
    36#
    … …  
    1922include $(RTEMS_ROOT)/make/directory.cfg
    2023
    21 SUB_DIRS = rtems wrap
     24SHARED_LIB=shared
    2225
    23 Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
    24         cd $(top_builddir) \
    25          && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status
     26ifeq ($(RTEMS_CPU_MODEL),mpc750)
     27CPUDIR=mpc750
     28else
     29CPUDIR=other_cpu
     30endif
     31
     32SUB_DIRS=$(CPUDIR) $(SHARED_LIB)
     33

  • c/src/exec/score/cpu/powerpc/mpc750/cpu.h

    r255b293 rba46ffa6  
    2525 *  Copyright assigned to U.S. Government, 1994.
    2626 *
    27  *  The license and distribution terms for this file may in
     27 *  The license and distribution terms for this file may be found in
    2828 *  the file LICENSE in this distribution or at
    2929 *  http://www.OARcorp.com/rtems/license.html.
    … …  
    4040
    4141#include <rtems/score/ppc.h>               /* pick up machine definitions */
     42#include <libcpu/cpu.h>
     43 
    4244#ifndef ASM
    43 struct CPU_Interrupt_frame;
    44 
    4545#include <rtems/score/ppctypes.h>
    4646#endif
    … …  
    111111 */
    112112
    113 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
     113#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
    114114
    115115/*
    … …  
    128128 */
    129129
    130 /*
    131  *  ACB: This is a lie, but it gets us a handle on a call to set up
    132  *  a variable derived from the top of the interrupt stack.
    133  */
    134 
    135 #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
     130#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
    136131
    137132/*
    … …  
    145140 */
    146141
    147 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
     142#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
    148143
    149144/*
    … …  
    153148 */
    154149
    155 #define CPU_ISR_PASSES_FRAME_POINTER 1
     150#define CPU_ISR_PASSES_FRAME_POINTER 0
    156151
    157152/*
    … …  
    305300#define CPU_LITTLE_ENDIAN                        FALSE
    306301
    307 /*
    308  *  The following defines the number of bits actually used in the
    309  *  interrupt field of the task mode.  How those bits map to the
    310  *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
    311  *
    312  *  The interrupt level is bit mapped for the PowerPC family. The
    313  *  bits are set to 0 to indicate that a particular exception source
    314  *  enabled and 1 if it is disabled.  This keeps with RTEMS convention
    315  *  that interrupt level 0 means all sources are enabled.
    316  *
    317  *  The bits are assigned to correspond to enable bits in the MSR.
    318  */
    319 
    320 #define PPC_INTERRUPT_LEVEL_ME   0x01
    321 #define PPC_INTERRUPT_LEVEL_EE   0x02
    322 #define PPC_INTERRUPT_LEVEL_CE   0x04
    323 
    324 /* XXX should these be maskable? */
    325 #if 0
    326 #define PPC_INTERRUPT_LEVEL_DE   0x08
    327 #define PPC_INTERRUPT_LEVEL_BE   0x10
    328 #define PPC_INTERRUPT_LEVEL_SE   0x20
    329 #endif
    330 
    331 #define CPU_MODES_INTERRUPT_MASK   0x00000007
    332302
    333303/*
    … …  
    420390typedef struct CPU_Interrupt_frame {
    421391    unsigned32 stacklink;       /* Ensure this is a real frame (also reg1 save) */
    422 #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
    423     unsigned32 dummy[13];       /* Used by callees: PowerOpen ABI */
    424 #else
    425     unsigned32 dummy[1];        /* Used by callees: SVR4/EABI */
    426 #endif
    427     /* This is what is left out of the primary contexts */
     392    unsigned32 calleeLr;        /* link register used by callees: SVR4/EABI */
     393  /* This is what is left out of the primary contexts */
    428394    unsigned32 gpr0;
    429395    unsigned32 gpr2;            /* play safe */
    … …  
    451417    unsigned32 pad[3];
    452418} CPU_Interrupt_frame;
    453 
    454 
     419 
    455420/*
    456421 *  The following table contains the information required to configure
    … …  
    472437
    473438  unsigned32   clicks_per_usec;        /* Timer clicks per microsecond */
    474   void       (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *);
    475439  boolean      exceptions_in_RAM;     /* TRUE if in RAM */
    476440
    477 #if (defined(ppc403) || defined(mpc860) || defined(mpc821))
    478   unsigned32   serial_per_sec;         /* Serial clocks per second */
    479   boolean      serial_external_clock;
    480   boolean      serial_xon_xoff;
    481   boolean      serial_cts_rts;
    482   unsigned32   serial_rate;
    483   unsigned32   timer_average_overhead; /* Average overhead of timer in ticks */
    484   unsigned32   timer_least_valid;      /* Least valid number from timer      */
    485   boolean      timer_internal_clock;   /* TRUE, when timer runs with CPU clk */
    486 #endif
    487 
    488 #if (defined(mpc860) || defined(mpc821))
    489   unsigned32   clock_speed;            /* Speed of CPU in Hz */
    490 #endif
    491441}   rtems_cpu_table;
    492 
    493 /*
    494  *  The following type defines an entry in the PPC's trap table.
    495  *
    496  *  NOTE: The instructions chosen are RTEMS dependent although one is
    497  *        obligated to use two of the four instructions to perform a
    498  *        long jump.  The other instructions load one register with the
    499  *        trap type (a.k.a. vector) and another with the psr.
    500  */
    501  
    502 typedef struct {
    503   unsigned32   stwu_r1;                       /* stwu  %r1, -(??+IP_END)(%1)*/
    504   unsigned32   stw_r0;                        /* stw   %r0, IP_0(%r1)       */
    505   unsigned32   li_r0_IRQ;                     /* li    %r0, _IRQ            */
    506   unsigned32   b_Handler;                     /* b     PROC (_ISR_Handler)  */
    507 } CPU_Trap_table_entry;
    508442
    509443/*
    … …  
    533467
    534468/*
     469 *  This defines the number of levels and the mask used to pick those
     470 *  bits out of a thread mode.
     471 */
     472
     473#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
     474#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
     475
     476/*
    535477 *  With some compilation systems, it is difficult if not impossible to
    536478 *  call a high-level language routine from assembly language.  This
    … …  
    550492
    551493SCORE_EXTERN struct {
    552   unsigned32 *Nest_level;
    553494  unsigned32 *Disable_level;
    554   void *Vector_table;
    555495  void *Stack;
    556 #if (PPC_ABI == PPC_ABI_POWEROPEN)
    557   unsigned32 Dispatch_r2;
    558 #else
    559   unsigned32 Default_r2;
    560 #if (PPC_ABI != PPC_ABI_GCC27)
    561   unsigned32 Default_r13;
    562 #endif
    563 #endif
    564496  volatile boolean *Switch_necessary;
    565497  boolean *Signal;
    566498
    567   unsigned32 msr_initial;
    568499} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
    569500
    … …  
    663594#define loc_string(a,b) a " (" #b ")\n"
    664595
    665 #define _CPU_MSR_Value( _msr_value ) \
    666   do { \
    667     _msr_value = 0; \
    668     asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
    669   } while (0)
    670 
    671 #define _CPU_MSR_SET( _msr_value ) \
    672 { asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
    673 
    674 #if 0
    675 #define _CPU_ISR_Disable( _isr_cookie ) \
    676   { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
    677     _isr_cookie = 0; \
    678     asm volatile (
    679         "mfmsr %0" : \
    680         "=r" ((_isr_cookie)) : \
    681         "0" ((_isr_cookie)) \
    682     ); \
    683     asm volatile (
    684         "andc %1,%0,%1" : \
    685         "=r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
    686         "0" ((_isr_cookie)), "1" ((_disable_mask)) \
    687     ); \
    688     asm volatile (
    689         "mtmsr %1" : \
    690         "=r" ((_disable_mask)) : \
    691         "0" ((_disable_mask)) \
    692     ); \
     596 
     597static inline unsigned32 _CPU_ISR_Get_level( void )
     598{
     599  register unsigned int msr;
     600  _CPU_MSR_GET(msr);
     601  if (msr & MSR_EE) return 0;
     602  else  return 1;
     603}
     604
     605static inline void _CPU_ISR_Set_level( unsigned32 level )
     606{
     607  register unsigned int msr;
     608  _CPU_MSR_GET(msr);
     609  if (!(level & CPU_MODES_INTERRUPT_MASK)) {
     610    msr |= MSR_EE;
    693611  }
    694 #endif
    695 
    696 #define _CPU_ISR_Disable( _isr_cookie ) \
    697   { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
    698     _isr_cookie = 0; \
    699     asm volatile ( \
    700         "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
    701         "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
    702         "0" ((_isr_cookie)), "1" ((_disable_mask)) \
    703         ); \
     612  else {
     613    msr &= ~MSR_EE;
    704614  }
    705 
    706 
    707 #define _CPU_Data_Cache_Block_Flush( _address ) \
    708   do { register void *__address = (_address); \
    709        register unsigned32 _zero = 0; \
    710        asm volatile ( "dcbf %0,%1" : \
    711                       "=r" (_zero), "=r" (__address) : \
    712                       "0" (_zero), "1" (__address) \
    713        ); \
    714   } while (0)
    715 
    716 
    717 /*
    718  *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
    719  *  This indicates the end of an RTEMS critical section.  The parameter
    720  *  _isr_cookie is not modified.
    721  */
    722 
    723 #define _CPU_ISR_Enable( _isr_cookie )  \
    724   { \
    725      asm volatile ( "mtmsr %0" : \
    726                    "=r" ((_isr_cookie)) : \
    727                    "0" ((_isr_cookie))); \
    728   }
    729 
    730 /*
    731  *  This temporarily restores the interrupt to _isr_cookie before immediately
    732  *  disabling them again.  This is used to divide long RTEMS critical
    733  *  sections into two or more parts.  The parameter _isr_cookie is not
    734  *  modified.
    735  *
    736  *  NOTE:  The version being used is not very optimized but it does
    737  *         not trip a problem in gcc where the disable mask does not
    738  *         get loaded.  Check this for future (post 10/97 gcc versions.
    739  */
    740 
    741 #define _CPU_ISR_Flash( _isr_cookie ) \
    742   { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \
    743     asm volatile ( \
    744       "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
    745       "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
    746       "0" ((_isr_cookie)), "1" ((_disable_mask)) \
    747     ); \
    748   }
    749 
    750 /*
    751  *  Map interrupt level in task mode onto the hardware that the CPU
    752  *  actually provides.  Currently, interrupt levels which do not
    753  *  map onto the CPU in a generic fashion are undefined.  Someday,
    754  *  it would be nice if these were "mapped" by the application
    755  *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
    756  *  8 - 255 would be available for bsp/application specific meaning.
    757  *  This could be used to manage a programmable interrupt controller
    758  *  via the rtems_task_mode directive.
    759  */
    760 
    761 unsigned32 _CPU_ISR_Calculate_level(
    762   unsigned32 new_level
    763 );
    764 
    765 void _CPU_ISR_Set_level(
    766   unsigned32 new_level
    767 );
     615  _CPU_MSR_SET(msr);
     616}
    768617 
    769 unsigned32 _CPU_ISR_Get_level( void );
    770 
    771 void _CPU_ISR_install_raw_handler(
    772   unsigned32  vector,
    773   proc_ptr    new_handler,
    774   proc_ptr   *old_handler
    775 );
    776 
    777 /* end of ISR handler macros */
    778 
    779 /*
    780  *  Simple spin delay in microsecond units for device drivers.
    781  *  This is very dependent on the clock speed of the target.
    782  */
    783 
    784 #define CPU_Get_timebase_low( _value ) \
    785     asm volatile( "mftb  %0" : "=r" (_value) )
    786 
    787 #define delay( _microseconds ) \
    788   do { \
    789     unsigned32 start, ticks, now; \
    790     CPU_Get_timebase_low( start ) ; \
    791     ticks = (_microseconds) * Cpu_table.clicks_per_usec; \
    792     do \
    793       CPU_Get_timebase_low( now ) ; \
    794     while (now - start < ticks); \
    795   } while (0)
    796 
    797 #define delay_in_bus_cycles( _cycles ) \
    798   do { \
    799     unsigned32 start, now; \
    800     CPU_Get_timebase_low( start ); \
    801     do \
    802       CPU_Get_timebase_low( now ); \
    803     while (now - start < (_cycles)); \
    804   } while (0)
    805 
    806 
     618#define _CPU_ISR_install_vector(irq, new, old) {BSP_panic("_CPU_ISR_install_vector called\n");}
    807619
    808620/* Context handler macros */
    … …  
    893705
    894706#define _CPU_Fatal_halt( _error ) \
    895   _CPU_Fatal_error(_error)
     707  _BSP_Fatal_error(_error)
    896708
    897709/* end of Fatal Error manager macros */
    … …  
    1000812);
    1001813
    1002 /*
    1003  *  _CPU_ISR_install_vector
    1004  *
    1005  *  This routine installs an interrupt vector.
    1006  */
    1007 
    1008 void _CPU_ISR_install_vector(
    1009   unsigned32  vector,
    1010   proc_ptr    new_handler,
    1011   proc_ptr   *old_handler
    1012 );
    1013814
    1014815/*

  • c/src/exec/score/cpu/powerpc/other_cpu/cpu.h

    r255b293 rba46ffa6  
    4242#ifndef ASM
    4343struct CPU_Interrupt_frame;
     44typedef void ( *ppc_isr_entry )( int, struct CPU_Interrupt_frame * );
    4445
    4546#include <rtems/score/ppctypes.h>

  • c/src/exec/score/include/rtems/score/isr.h

    r255b293 rba46ffa6  
    8383 */
    8484
    85 SCORE_EXTERN unsigned32 _ISR_Nest_level;
     85SCORE_EXTERN volatile unsigned32 _ISR_Nest_level;
    8686
    8787/*

  • c/src/exec/score/include/rtems/score/thread.h

    r255b293 rba46ffa6  
    235235 */
    236236
    237 SCORE_EXTERN unsigned32 _Thread_Dispatch_disable_level;
     237SCORE_EXTERN volatile unsigned32 _Thread_Dispatch_disable_level;
    238238
    239239/*

  • c/src/exec/score/inline/rtems/score/isr.inl

    r255b293 rba46ffa6  
    3030 */
    3131
     32#if defined(powerpc)
     33#define CPU_PROVIDES_ISR_IS_IN_PROGRESS
     34#endif
     35
     36#ifndef CPU_PROVIDES_ISR_IS_IN_PROGRESS
     37
    3238RTEMS_INLINE_ROUTINE boolean _ISR_Is_in_progress( void )
    3339{
    3440  return (_ISR_Nest_level != 0);
    3541}
     42#else
     43#include <rtems/score/c_isr.inl>
     44#endif
    3645
    3746/*PAGE

  • c/src/lib/libbsp/i386/shared/irq/irq.c

    r255b293 rba46ffa6  
    347347    }
    348348    /*
    349      * must disable slave pic anyway
     349     * must enable slave pic anyway
    350350     */
    351351    BSP_irq_enable_at_i8259s (2);
    … …  
    375375  /*
    376376   * I plan to process other thread related events here.
    377    * This will include DEBUG session requsted from keyboard...
     377   * This will include DEBUG session requested from keyboard...
    378378   */
    379379}

  • c/src/lib/libbsp/i386/shared/irq/irq_init.c

    r255b293 rba46ffa6  
    9494   * The second entry has a priority of 255 because
    9595   * it is the slave pic entry and is should always remain
    96    * unamsked.
     96   * unmasked.
    9797   */
    9898  0,0,

  • c/src/lib/libbsp/powerpc/motorola_powerpc/start/Makefile.in

    r255b293 rba46ffa6  
    66srcdir = @srcdir@
    77top_srcdir = @top_srcdir@
    8 top_builddir = ../../../../../../../..
    9 subdir = c/src/exec/score/cpu/powerpc/rtems/score
     8top_builddir = ../../../../../../..
     9subdir = c/src/lib/libbsp/powerpc/mcp750/start
    1010
    1111INSTALL = @INSTALL@
    … …  
    1616VPATH = @srcdir@
    1717
     18PGM=${ARCH}/start.o
     19
    1820# C source names, if any, go here -- minus the .c
    1921C_PIECES=
    … …  
    2123C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
    2224
    23 H_PIECES=cpu.h ppc.h ppctypes.h
    24 H_FILES=$(H_PIECES:%=$(srcdir)/%)
     25H_FILES=
    2526
    2627# Assembly source names, if any, go here -- minus the .S
    27 S_PIECES=
     28S_PIECES=start
    2829S_FILES=$(S_PIECES:%=%.S)
    2930S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
    … …  
    4142DEFINES  +=
    4243CPPFLAGS +=
    43 CFLAGS   += 
     44CFLAGS   +=
    4445
    4546LD_PATHS  +=
    … …  
    5556
    5657CLEAN_ADDITIONS +=
    57 CLOBBER_ADDITIONS += $(BUILT_SOURCES)
     58CLOBBER_ADDITIONS +=
    5859
    59 # Install the program(s), appending _g or _p as appropriate.
    60 # for include files, just use $(INSTALL_CHANGE)
    61 all: install-headers
    62 
    63 install-headers: ${H_FILES}
    64         $(INSTALL_CHANGE) -m 444 ${H_FILES} $(PROJECT_INCLUDE)/rtems/score
    65 
    66 preinstall: install-headers
     60all:    ${ARCH} $(SRCS) $(OBJS) $(PGM)
     61        $(INSTALL_VARIANT) -m 555 ${PGM} ${PROJECT_RELEASE}/lib
    6762
    6863Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status

  • c/src/lib/libcpu/powerpc/Makefile.in

    r255b293 rba46ffa6  
    1919include $(RTEMS_ROOT)/make/directory.cfg
    2020
    21 SUB_DIRS=$(wildcard $(RTEMS_CPU_MODEL))
     21ifeq ($(RTEMS_CPU_MODEL),mpc750)
     22SHARED_LIB=shared
     23endif
     24
     25SUB_DIRS=$(wildcard $(RTEMS_CPU_MODEL)) $(SHARED_LIB)
    2226
    2327Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status

  • c/src/lib/libcpu/powerpc/mpc750/Makefile.in

    r255b293 rba46ffa6  
    66srcdir = @srcdir@
    77top_srcdir = @top_srcdir@
    8 top_builddir = ../../../../../../..
    9 subdir = c/src/exec/score/cpu/powerpc/rtems
     8top_builddir = ../../../../../..
     9subdir = c/src/lib/libcpu/mpc750
    1010
    1111INSTALL = @INSTALL@
    … …  
    1919include $(RTEMS_ROOT)/make/directory.cfg
    2020
    21 SUB_DIRS = score
     21# wrapup is the one that actually builds and installs the library
     22#  from the individual .rel files built in other directories
     23SUB_DIRS=exceptions mmu clock wrapup
    2224
    2325Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status

  • cpukit/score/include/rtems/score/isr.h

    r255b293 rba46ffa6  
    8383 */
    8484
    85 SCORE_EXTERN unsigned32 _ISR_Nest_level;
     85SCORE_EXTERN volatile unsigned32 _ISR_Nest_level;
    8686
    8787/*

  • cpukit/score/include/rtems/score/thread.h

    r255b293 rba46ffa6  
    235235 */
    236236
    237 SCORE_EXTERN unsigned32 _Thread_Dispatch_disable_level;
     237SCORE_EXTERN volatile unsigned32 _Thread_Dispatch_disable_level;
    238238
    239239/*

  • cpukit/score/inline/rtems/score/isr.inl

    r255b293 rba46ffa6  
    3030 */
    3131
     32#if defined(powerpc)
     33#define CPU_PROVIDES_ISR_IS_IN_PROGRESS
     34#endif
     35
     36#ifndef CPU_PROVIDES_ISR_IS_IN_PROGRESS
     37
    3238RTEMS_INLINE_ROUTINE boolean _ISR_Is_in_progress( void )
    3339{
    3440  return (_ISR_Nest_level != 0);
    3541}
     42#else
     43#include <rtems/score/c_isr.inl>
     44#endif
    3645
    3746/*PAGE
Note: See TracChangeset for help on using the changeset viewer.