Changeset b9cc5aa in rtems


Ignore:
Timestamp:
Aug 22, 2016, 8:41:33 AM (3 years ago)
Author:
Christian Mauderer <Christian.Mauderer@…>
Branches:
master
Children:
7ec689ad
Parents:
beb289e
git-author:
Christian Mauderer <Christian.Mauderer@…> (08/22/16 08:41:33)
git-committer:
Sebastian Huber <sebastian.huber@…> (09/07/16 11:38:53)
Message:

bsp/atsam: Add SDRAM IS42S16320F-7BL.

Location:
c/src/lib/libbsp/arm/atsam
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/atsam/README

    rbeb289e rb9cc5aa  
    1010samv71n20, samv71n21, samv71q19, samv71q20 and samv71q21.  By default the BSP
    1111uses the ATSAMV71Q21 chip.  Not all variants are tested.
     12
     13Use --enable-sdram=XYZ to select the SDRAM variant where XYZ is one of
     14is42s16100e-7bli and is42s16320f-7bl. Not all variants are tested with all
     15controller and speed combinations.
    1216
    1317Use BOARD_MAINOSC=XYZ to set the main oscillator frequency in Hz (default
  • c/src/lib/libbsp/arm/atsam/configure.ac

    rbeb289e rb9cc5aa  
    5151[AC_DEFINE([__SAMV71Q21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000])
    5252
     53AC_ARG_ENABLE(
     54[sdram],
     55[AS_HELP_STRING([--enable-sdram],[select a SDRAM variant (default is42s16100e-7bli)])],
     56[case "${enableval}" in
     57  is42s16100e-7bli) AC_DEFINE([ATSAM_SDRAM_IS42S16100E_7BLI],[1],[SDRAM variant]) EXTSDRAM=0x00200000 ;;
     58  is42s16320f-7bl) AC_DEFINE([ATSAM_SDRAM_IS42S16320F_7BL],[1],[SDRAM variant]) EXTSDRAM=0x04000000 ;;
     59  *) AC_MSG_ERROR([bad value ${enableval} for SDRAM variant]) ;;
     60esac],
     61[AC_DEFINE([ATSAM_SDRAM_IS42S16100E_7BLI],[1],[SDRAM variant]) EXTSDRAM=0x00200000])
     62
    5363RTEMS_BSPOPTS_SET([BOARD_MAINOSC],[*],[12000000])
    5464RTEMS_BSPOPTS_HELP([BOARD_MAINOSC],[Main oscillator frequency in Hz (default 12MHz)])
     
    7787ATSAM_LINKCMD([ATSAM_MEMORY_INTFLASH_SIZE],[size of internal flash in bytes],[${INTFLASH}])
    7888ATSAM_LINKCMD([ATSAM_MEMORY_INTSRAM_SIZE],[size of internal SRAM in bytes],[${INTSRAM}])
    79 ATSAM_LINKCMD([ATSAM_MEMORY_SDRAM_SIZE],[size of external SDRAM in bytes],[0x00200000])
     89ATSAM_LINKCMD([ATSAM_MEMORY_SDRAM_SIZE],[size of external SDRAM in bytes],[${EXTSDRAM}])
    8090ATSAM_LINKCMD([ATSAM_MEMORY_QSPIFLASH_SIZE],[size of QSPI flash in bytes],[0x00200000])
    8191
  • c/src/lib/libbsp/arm/atsam/startup/sdram-config.c

    rbeb289e rb9cc5aa  
    1313 */
    1414
     15#include <bspopts.h>
    1516#include <chip.h>
    1617#include <include/board_memories.h>
    1718
     19#if defined ATSAM_SDRAM_IS42S16100E_7BLI
    1820const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
     21  /* FIXME: a lot of these values should be calculated using CPU frequency */
    1922  .sdramc_tr = 1562,
    2023  .sdramc_cr =
     
    3336  .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED | SDRAMC_CFR1_TMRD(2)
    3437};
     38
     39#elif defined ATSAM_SDRAM_IS42S16320F_7BL
     40#define CLOCK_CYCLES_FROM_NS_MAX(ns) \
     41    (((ns) * (BOARD_MCK / 1000ul / 1000ul)) / 1000ul)
     42#define CLOCK_CYCLES_FROM_NS_MIN(ns) (CLOCK_CYCLES_FROM_NS_MAX(ns) + 1)
     43
     44const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
     45  /* 8k refresh cycles every 64ms => 7.8125us */
     46  .sdramc_tr = CLOCK_CYCLES_FROM_NS_MAX(7812ul),
     47  .sdramc_cr =
     48      SDRAMC_CR_NC_COL10
     49    | SDRAMC_CR_NR_ROW13
     50    | SDRAMC_CR_CAS_LATENCY3
     51    | SDRAMC_CR_NB_BANK4
     52    | SDRAMC_CR_DBW
     53    /* t_WR = 30ns min (t_RC - t_RP - t_RCD;
     54     * see data sheet November 2015 page 55);
     55     * add some security margin */
     56    | SDRAMC_CR_TWR(CLOCK_CYCLES_FROM_NS_MIN(40))
     57    | SDRAMC_CR_TRC_TRFC(CLOCK_CYCLES_FROM_NS_MIN(60))
     58    | SDRAMC_CR_TRP(CLOCK_CYCLES_FROM_NS_MIN(15))
     59    | SDRAMC_CR_TRCD(CLOCK_CYCLES_FROM_NS_MIN(15))
     60    | SDRAMC_CR_TRAS(CLOCK_CYCLES_FROM_NS_MIN(37))
     61    | SDRAMC_CR_TXSR(CLOCK_CYCLES_FROM_NS_MIN(67)),
     62  .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
     63  .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED |
     64      SDRAMC_CFR1_TMRD(CLOCK_CYCLES_FROM_NS_MIN(14))
     65};
     66
     67#if CLOCK_CYCLES_FROM_NS_MIN(67) > 0xF
     68  /* Prevent the fields to be out of range by checking the one with the biggest
     69   * value. */
     70  #error SDRAM calculation does not work for the selected clock frequency
     71#endif
     72
     73#else
     74  #error SDRAM not supported.
     75#endif
Note: See TracChangeset for help on using the changeset viewer.