Changeset b900f507 in rtems


Ignore:
Timestamp:
Feb 12, 2020, 7:53:35 AM (7 weeks ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
bf39a9e
Parents:
adf7e753
git-author:
Sebastian Huber <sebastian.huber@…> (02/12/20 07:53:35)
git-committer:
Sebastian Huber <sebastian.huber@…> (02/12/20 08:08:35)
Message:

arm/xilinx-zynq: Split console driver files

This avoids to pull in via printk() the Termios support which pulls in
the file system support. This fixes a spconfig02 test failure.

Files:
2 added
4 edited

Legend:

Unmodified
Added
Removed
  • bsps/arm/shared/serial/zynq-uart.c

    radf7e753 rb900f507  
    3131
    3232#include <bspopts.h>
    33 
    34 /*
    35  * Make weak and let the user override.
    36  */
    37 uint32_t zynq_uart_input_clock(void) __attribute__ ((weak));
    38 
    39 uint32_t zynq_uart_input_clock(void)
    40 {
    41   return ZYNQ_CLOCK_UART;
    42 }
    43 
    44 static int zynq_cal_baud_rate(uint32_t  baudrate,
    45                               uint32_t* brgr,
    46                               uint32_t* bauddiv,
    47                               uint32_t  modereg)
    48 {
    49   uint32_t brgr_value;    /* Calculated value for baud rate generator */
    50   uint32_t calcbaudrate;  /* Calculated baud rate */
    51   uint32_t bauderror;     /* Diff between calculated and requested baud rate */
    52   uint32_t best_error = 0xFFFFFFFF;
    53   uint32_t percenterror;
    54   uint32_t bdiv;
    55   uint32_t inputclk = zynq_uart_input_clock();
    56 
    57   /*
    58    * Make sure the baud rate is not impossilby large.
    59    * Fastest possible baud rate is Input Clock / 2.
    60    */
    61   if ((baudrate * 2) > inputclk) {
    62     return -1;
    63   }
    64   /*
    65    * Check whether the input clock is divided by 8
    66    */
    67   if(modereg & ZYNQ_UART_MODE_CLKS) {
    68     inputclk = inputclk / 8;
    69   }
    70 
    71   /*
    72    * Determine the Baud divider. It can be 4to 254.
    73    * Loop through all possible combinations
    74    */
    75   for (bdiv = 4; bdiv < 255; bdiv++) {
    76 
    77     /*
    78      * Calculate the value for BRGR register
    79      */
    80     brgr_value = inputclk / (baudrate * (bdiv + 1));
    81 
    82     /*
    83      * Calculate the baud rate from the BRGR value
    84      */
    85     calcbaudrate = inputclk/ (brgr_value * (bdiv + 1));
    86 
    87     /*
    88      * Avoid unsigned integer underflow
    89      */
    90     if (baudrate > calcbaudrate) {
    91       bauderror = baudrate - calcbaudrate;
    92     }
    93     else {
    94       bauderror = calcbaudrate - baudrate;
    95     }
    96 
    97     /*
    98      * Find the calculated baud rate closest to requested baud rate.
    99      */
    100     if (best_error > bauderror) {
    101       *brgr = brgr_value;
    102       *bauddiv = bdiv;
    103       best_error = bauderror;
    104     }
    105   }
    106 
    107   /*
    108    * Make sure the best error is not too large.
    109    */
    110   percenterror = (best_error * 100) / baudrate;
    111 #define XUARTPS_MAX_BAUD_ERROR_RATE              3      /* max % error allowed */
    112   if (XUARTPS_MAX_BAUD_ERROR_RATE < percenterror) {
    113     return -1;
    114   }
    115 
    116   return 0;
    117 }
    118 
    119 void zynq_uart_initialize(rtems_termios_device_context *base)
    120 {
    121   zynq_uart_context *ctx = (zynq_uart_context *) base;
    122   volatile zynq_uart *regs = ctx->regs;
    123   uint32_t brgr = 0x3e;
    124   uint32_t bauddiv = 0x6;
    125 
    126   zynq_cal_baud_rate(ZYNQ_UART_DEFAULT_BAUD, &brgr, &bauddiv, regs->mode);
    127 
    128   regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN);
    129   regs->control = ZYNQ_UART_CONTROL_RXDIS
    130     | ZYNQ_UART_CONTROL_TXDIS
    131     | ZYNQ_UART_CONTROL_RXRES
    132     | ZYNQ_UART_CONTROL_TXRES;
    133   regs->mode = ZYNQ_UART_MODE_CHMODE(ZYNQ_UART_MODE_CHMODE_NORMAL)
    134     | ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_NONE)
    135     | ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_8);
    136   regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr);
    137   regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv);
    138   regs->rx_fifo_trg_lvl = ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(0);
    139   regs->rx_timeout = ZYNQ_UART_RX_TIMEOUT_RTO(0);
    140   regs->control = ZYNQ_UART_CONTROL_RXEN
    141     | ZYNQ_UART_CONTROL_TXEN
    142     | ZYNQ_UART_CONTROL_RSTTO;
    143 }
    14433
    14534#ifdef ZYNQ_CONSOLE_USE_INTERRUPTS
     
    221110#endif
    222111
    223 int zynq_uart_read_polled(rtems_termios_device_context *base)
    224 {
    225   zynq_uart_context *ctx = (zynq_uart_context *) base;
    226   volatile zynq_uart *regs = ctx->regs;
    227 
    228   if ((regs->channel_sts & ZYNQ_UART_CHANNEL_STS_REMPTY) != 0) {
    229     return -1;
    230   } else {
    231     return ZYNQ_UART_TX_RX_FIFO_FIFO_GET(regs->tx_rx_fifo);
    232   }
    233 }
    234 
    235 void zynq_uart_write_polled(
    236   rtems_termios_device_context *base,
    237   char c
    238 )
    239 {
    240   zynq_uart_context *ctx = (zynq_uart_context *) base;
    241   volatile zynq_uart *regs = ctx->regs;
    242 
    243   while ((regs->channel_sts & ZYNQ_UART_CHANNEL_STS_TFUL) != 0) {
    244     /* Wait */
    245   }
    246 
    247   regs->tx_rx_fifo = ZYNQ_UART_TX_RX_FIFO_FIFO(c);
    248 }
    249 
    250112static void zynq_uart_write_support(
    251113  rtems_termios_device_context *base,
     
    314176#endif
    315177};
    316 
    317 void zynq_uart_reset_tx_flush(zynq_uart_context *ctx)
    318 {
    319   volatile zynq_uart *regs = ctx->regs;
    320   int                 c = 4;
    321 
    322   while (c-- > 0)
    323     zynq_uart_write_polled(&ctx->base, '\r');
    324 
    325   while ((regs->channel_sts & ZYNQ_UART_CHANNEL_STS_TEMPTY) == 0) {
    326     /* Wait */
    327   }
    328 }
  • bsps/arm/xilinx-zynq/console/console-config.c

    radf7e753 rb900f507  
    2626 */
    2727
    28 #include <rtems/console.h>
    29 #include <rtems/bspIo.h>
    30 
    3128#include <bsp/irq.h>
    3229#include <bsp/zynq-uart.h>
    33 
    34 #include <bspopts.h>
    3530
    3631zynq_uart_context zynq_uart_instances[2] = {
     
    4540  }
    4641};
    47 
    48 rtems_status_code console_initialize(
    49   rtems_device_major_number major,
    50   rtems_device_minor_number minor,
    51   void *arg
    52 )
    53 {
    54   size_t i;
    55 
    56   rtems_termios_initialize();
    57 
    58   for (i = 0; i < RTEMS_ARRAY_SIZE(zynq_uart_instances); ++i) {
    59     char uart[] = "/dev/ttySX";
    60 
    61     uart[sizeof(uart) - 2] = (char) ('0' + i);
    62     rtems_termios_device_install(
    63       &uart[0],
    64       &zynq_uart_handler,
    65       NULL,
    66       &zynq_uart_instances[i].base
    67     );
    68 
    69     if (i == BSP_CONSOLE_MINOR) {
    70       link(&uart[0], CONSOLE_DEVICE_NAME);
    71     }
    72   }
    73 
    74   return RTEMS_SUCCESSFUL;
    75 }
  • c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am

    radf7e753 rb900f507  
    6161librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios.c
    6262librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/console/console-config.c
     63librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/console/console-init.c
    6364librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynq/console/debug-console.c
    6465librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/serial/zynq-uart.c
     66librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/serial/zynq-uart-polled.c
    6567
    6668# Clock
  • c/src/lib/libbsp/arm/xilinx-zynqmp/Makefile.am

    radf7e753 rb900f507  
    6262librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xilinx-zynqmp/console/console-config.c
    6363librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/serial/zynq-uart.c
     64librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/serial/zynq-uart-polled.c
    6465
    6566# Clock
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