Changeset b8fdbe2 in rtems-libbsd


Ignore:
Timestamp:
Oct 4, 2017, 12:15:59 PM (19 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
647dd08ae2aa69b935c2847ea450fb824322ecae, c6261f97870562d4c797cfb1ff1ba0affb85a916
Children:
798d308
Parents:
2fcf5aa
git-author:
Sebastian Huber <sebastian.huber@…> (10/04/17 12:15:59)
git-committer:
Sebastian Huber <sebastian.huber@…> (10/25/17 12:29:37)
Message:

ffec: Use RACC[SHIFT16]

This avoids the move of entire receive frames to meet the alignment
requirements of the IP header and so on.

Add FECFLAG_RACC feature flag for this similar to the Linux driver.

Update #3090.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • freebsd/sys/dev/ffec/if_ffec.c

    r2fcf5aa rb8fdbe2  
    109109#define FECFLAG_GBE             (1 << 16)
    110110#define FECFLAG_AVB             (1 << 17)
     111#define FECFLAG_RACC            (1 << 18)
    111112
    112113/*
     
    116117        {"fsl,imx51-fec",       FECTYPE_GENERIC},
    117118        {"fsl,imx53-fec",       FECTYPE_IMX53},
    118         {"fsl,imx6q-fec",       FECTYPE_IMX6 | FECFLAG_GBE},
    119         {"fsl,mvf600-fec",      FECTYPE_MVF},
     119        {"fsl,imx6q-fec",       FECTYPE_IMX6 | FECFLAG_GBE | FECFLAG_RACC},
     120        {"fsl,mvf600-fec",      FECTYPE_MVF | FECFLAG_RACC},
    120121        {"fsl,mvf-fec",         FECTYPE_MVF},
    121         {"fsl,imx7d-fec",       FECTYPE_IMX6 | FECFLAG_GBE | FECFLAG_AVB},
     122        {"fsl,imx7d-fec",       FECTYPE_IMX6 | FECFLAG_GBE | FECFLAG_AVB |
     123                                    FECFLAG_RACC},
    122124        {NULL,                  FECTYPE_NONE},
    123125};
     
    754756        struct bus_dma_segment seg;
    755757
    756         /*
    757          * We need to leave at least ETHER_ALIGN bytes free at the beginning of
    758          * the buffer to allow the data to be re-aligned after receiving it (by
    759          * copying it backwards ETHER_ALIGN bytes in the same buffer).  We also
    760          * have to ensure that the beginning of the buffer is aligned to the
    761          * hardware's requirements.
    762          */
    763         m_adj(m, roundup(ETHER_ALIGN, sc->rxbuf_align));
     758        if ((sc->fectype & FECFLAG_RACC) == 0) {
     759                /*
     760                 * The RACC[SHIFT16] feature is not used.  So, we need to leave
     761                 * at least ETHER_ALIGN bytes free at the beginning of the
     762                 * buffer to allow the data to be re-aligned after receiving it
     763                 * (by copying it backwards ETHER_ALIGN bytes in the same
     764                 * buffer).  We also have to ensure that the beginning of the
     765                 * buffer is aligned to the hardware's requirements.
     766                 */
     767                m_adj(m, roundup(ETHER_ALIGN, sc->rxbuf_align));
     768        }
    764769
    765770        error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
     
    797802        struct mbuf *m, *newmbuf;
    798803        struct ffec_bufmap *bmap;
    799         uint8_t *dst, *src;
    800804        int error;
    801805
     
    841845        m->m_pkthdr.rcvif = sc->ifp;
    842846
    843         src = mtod(m, uint8_t*);
    844         dst = src - ETHER_ALIGN;
    845         bcopy(src, dst, len);
    846         m->m_data = dst;
     847        if (sc->fectype & FECFLAG_RACC) {
     848                /* We use the RACC[SHIFT16] feature */
     849                m->m_data = mtod(m, uint8_t *) + 2;
     850        } else {
     851                uint8_t *dst, *src;
     852
     853                src = mtod(m, uint8_t*);
     854                dst = src - ETHER_ALIGN;
     855                bcopy(src, dst, len);
     856                m->m_data = dst;
     857        }
    847858        sc->ifp->if_input(sc->ifp, m);
    848859
     
    12181229        WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS);
    12191230
     1231        if (sc->fectype & FECFLAG_RACC) {
     1232                /*
     1233                 * RACC - Receive Accelerator Function Configuration.
     1234                 */
     1235                regval = RD4(sc, FEC_RACC_REG);
     1236                WR4(sc, FEC_RACC_REG, regval | FEC_RACC_SHIFT16);
     1237        }
     1238
    12201239        /*
    12211240         * ECR - Ethernet control register.
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