Ignore:
Timestamp:
Jun 24, 2019, 8:16:59 PM (2 months ago)
Author:
Christian Mauderer <christian.mauderer@…>
Branches:
master
Children:
5cbee18
Parents:
5803f37
git-author:
Christian Mauderer <christian.mauderer@…> (06/24/19 20:16:59)
git-committer:
Christian Mauderer <oss@…> (06/29/19 07:37:24)
Message:

bsp/beagle: Partial re-write of I2C driver.

The old driver worked well for EEPROMS with the RTEMS EEPROM driver. But
it had problems with a lot of other situations. Although it's not a
direct port, the new driver is heavily modeled after the FreeBSD ti_i2c
driver.

Closes #3764.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • bsps/arm/beagle/include/bsp/i2c.h

    r5803f37 rb89d6cc  
    2525
    2626#include <rtems.h>
     27#include <bsp.h>
    2728#include <dev/i2c/i2c.h>
    28 #include <bsp.h>
    2929
    3030#ifdef __cplusplus
     
    3232#endif /* __cplusplus */
    3333
    34 
    35 /* I2C Configuration Register (I2C_CON): */
    36 
    37 #define BBB_I2C_CON_EN  (1 << 15)  /* I2C module enable */
    38 #define BBB_I2C_CON_BE  (1 << 14)  /* Big endian mode */
    39 #define BBB_I2C_CON_STB (1 << 11)  /* Start byte mode (master mode only) */
    40 #define BBB_I2C_CON_MST (1 << 10)  /* Master/slave mode */
    41 #define BBB_I2C_CON_TRX (1 << 9)   /* Transmitter/receiver mode */
    42            /* (master mode only) */
    43 #define BBB_I2C_CON_XA  (1 << 8)   /* Expand address */
    44 #define BBB_I2C_CON_STP (1 << 1)   /* Stop condition (master mode only) */
    45 #define BBB_I2C_CON_STT (1 << 0)   /* Start condition (master mode only) */
    46 #define BBB_I2C_CON_CLR 0x0  /* Clear configuration register */
    47 /* I2C Status Register (I2C_STAT): */
    48 
    49 #define BBB_I2C_STAT_SBD  (1 << 15) /* Single byte data */
    50 #define BBB_I2C_STAT_BB (1 << 12) /* Bus busy */
    51 #define BBB_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
    52 #define BBB_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
    53 #define BBB_I2C_STAT_AAS  (1 << 9)  /* Address as slave */
    54 #define BBB_I2C_STAT_GC (1 << 5)
    55 #define BBB_I2C_STAT_XRDY (1 << 4)  /* Transmit data ready */
    56 #define BBB_I2C_STAT_RRDY (1 << 3)  /* Receive data ready */
    57 #define BBB_I2C_STAT_ARDY (1 << 2)  /* Register access ready */
    58 #define BBB_I2C_STAT_NACK (1 << 1)  /* No acknowledgment interrupt enable */
    59 #define BBB_I2C_STAT_AL (1 << 0)  /* Arbitration lost interrupt enable */
    60 
    61 /* I2C Interrupt Enable Register (I2C_IE): */
    62 #define BBB_I2C_IE_GC_IE  (1 << 5)
    63 #define BBB_I2C_IE_XRDY_IE  (1 << 4) /* Transmit data ready interrupt enable */
    64 #define BBB_I2C_IE_RRDY_IE  (1 << 3) /* Receive data ready interrupt enable */
    65 #define BBB_I2C_IE_ARDY_IE  (1 << 2) /* Register access ready interrupt enable */
    66 #define BBB_I2C_IE_NACK_IE  (1 << 1) /* No acknowledgment interrupt enable */
    67 #define BBB_I2C_IE_AL_IE  (1 << 0) /* Arbitration lost interrupt enable */
    68 
    69 /* I2C SYSC Register (I2C_SYSC): */
    70 #define BBB_I2C_SYSC_SRST (1 << 1)
    71 
    72 #define BBB_I2C_TIMEOUT 1000
    73 
    74 #define BBB_I2C_SYSS_RDONE            (1 << 0)  /* Internel reset monitoring */
    75 
    76 #define BBB_CONFIG_SYS_I2C_SPEED    100000
    77 #define BBB_CONFIG_SYS_I2C_SLAVE    1
    78 #define BBB_I2C_ALL_FLAGS 0x7FFF
    79 #define BBB_I2C_ALL_IRQ_FLAGS 0xFFFF
    80 
    8134#define BBB_I2C_SYSCLK 48000000
    8235#define BBB_I2C_INTERNAL_CLK 12000000
    83 #define BBB_I2C_SPEED_CLK 100000
    84 
    85 #define BBB_I2C_IRQ_ERROR \
    86   ( AM335X_I2C_IRQSTATUS_NACK \
    87     | AM335X_I2C_IRQSTATUS_ROVR \
    88     | AM335X_I2C_IRQSTATUS_AL \
    89     | AM335X_I2C_IRQSTATUS_ARDY \
    90     | AM335X_I2C_IRQSTATUS_RRDY \
    91     | AM335X_I2C_IRQSTATUS_XRDY \
    92     | AM335X_I2C_IRQSTATUS_XUDF )
    93 
    94 #define BBB_I2C_IRQ_USED \
    95   ( AM335X_I2C_IRQSTATUS_ARDY \
    96     | AM335X_I2C_IRQSTATUS_XRDY )
    9736
    9837#define BBB_I2C_0_BUS_PATH "/dev/i2c-0"
     
    10342#define BBB_I2C1_IRQ 71
    10443#define BBB_I2C2_IRQ 30
    105 
    106 #define BBB_MODE2 2
    107 #define BBB_MODE3 3
    10844
    10945typedef enum {
     
    15288} bbb_i2c_regs;
    15389
    154 typedef struct bbb_i2c_bus {
    155   i2c_bus base;
    156   volatile bbb_i2c_regs *regs;
    157   i2c_msg *msgs;
    158   uint32_t msg_todo;
    159   uint32_t current_msg_todo;
    160   uint8_t *current_msg_byte;
    161   uint32_t current_todo;
    162   bool read;
    163   bool hold;
    164   rtems_id task_id;
    165   rtems_vector_number irq;
    166   uint32_t input_clock;
    167   uint32_t already_transferred;
    168 } bbb_i2c_bus;
    169 
    17090int am335x_i2c_bus_register(
    17191  const char         *bus_path,
    17292  uintptr_t           register_base,
    173   uint32_t            input_clock,
     93  uint32_t            input_clock, /* FIXME: Unused. Left for compatibility. */
    17494  rtems_vector_number irq
    17595);
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