Changeset b812f84 in rtems
- Timestamp:
- 08/01/00 20:01:14 (23 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 9bb1a93
- Parents:
- 499d443
- Files:
-
- 29 added
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
aclocal/bsp-alias.m4
r499d443 rb812f84 8 8 [# account for "aliased" bsps which share source code 9 9 case $1 in 10 simcpu32) $2=sim68000 ;; # BSVC CPU32 variant 10 11 c3xsim) $2=c4xsim ;; # TI C3x Simulator in gdb 11 12 mcp750) $2=motorola_powerpc ;; # Motorola PPC board variant -
aclocal/check-bsps.m4
r499d443 rb812f84 28 28 motorola_powerpc) rtems_bsp="$rtems_bsp mvme2307 mcp750";; 29 29 pc386) rtems_bsp="$rtems_bsp pc386 pc486 pc586 pc686";; 30 sim68000) rtems_bsp="$rtems_bsp simcpu32";; 30 31 *) $1="[$]$1 $file";; 31 32 esac; -
c/ACKNOWLEDGEMENTS
r499d443 rb812f84 169 169 support and the rxgen960 board support package. 170 170 171 + Joel Sherrill <joel@OARcorp.com> for the i960sim BSP that works 172 with the i960 instruction set simulator in gdb. 171 + Joel Sherrill <joel@OARcorp.com> for the BSPs that work with 172 numerous simulators including psim, i960sim, c4xsim, h8sim, armulator, 173 sim68000, and simcpu32. Most of these BSPs work with instruction 174 set simulators in gdb. 173 175 174 176 + Darlene Stewart <Darlene.Stewart@nrc.ca> and Charles Gauthier -
c/TESTED
r499d443 rb812f84 33 33 i960 i960rp rxgen960 (note 1) 34 34 m68k mfc5200 no BSP (note 9) 35 m68k m68000 sim68000 (BSVC) (note 5 -- under development) 36 m68k cpu32 simcpu32 (BSVC) (note 5 -- under development) 35 37 m68k m68000 efi68k (note 1) 36 38 m68k m68020 Motorola MVME136 (note 1, 6)
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