Changeset b7e2596 in rtems


Ignore:
Timestamp:
Mar 25, 2003, 6:37:02 PM (17 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
26cdc2a
Parents:
13f2628
Message:

2003-03-25 Thomas Doerfler <Thomas.Doerfler@…>

PR 368/filesystems

  • mpc8xx/include/mpc8xx.h: Add PCMCIA registers.
Location:
c/src/lib/libcpu/powerpc
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/ChangeLog

    r13f2628 rb7e2596  
     12003-03-25      Thomas Doerfler <Thomas.Doerfler@imd-systems.de>
     2
     3        PR 368/filesystems
     4        * mpc8xx/include/mpc8xx.h: Add PCMCIA registers.
     5
    162003-03-25      Till Straumann <strauman@slac.stanford.edu>
    27
  • c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h

    r13f2628 rb7e2596  
    768768/*
    769769*************************************************************************
     770*                 PCMCIA Control Registers
     771*************************************************************************
     772*/
     773#define M8xx_PCMCIA_POR_BSIZE_1B    (0x00 << (31-4))
     774#define M8xx_PCMCIA_POR_BSIZE_2B    (0x01 << (31-4))
     775#define M8xx_PCMCIA_POR_BSIZE_4B    (0x03 << (31-4))
     776#define M8xx_PCMCIA_POR_BSIZE_8B    (0x02 << (31-4))
     777#define M8xx_PCMCIA_POR_BSIZE_16B   (0x06 << (31-4))
     778#define M8xx_PCMCIA_POR_BSIZE_32B   (0x07 << (31-4))
     779#define M8xx_PCMCIA_POR_BSIZE_64B   (0x05 << (31-4))
     780#define M8xx_PCMCIA_POR_BSIZE_128B  (0x04 << (31-4))
     781#define M8xx_PCMCIA_POR_BSIZE_256B  (0x0C << (31-4))
     782#define M8xx_PCMCIA_POR_BSIZE_512B  (0x0D << (31-4))
     783#define M8xx_PCMCIA_POR_BSIZE_1KB   (0x0F << (31-4))
     784#define M8xx_PCMCIA_POR_BSIZE_2KB   (0x0E << (31-4))
     785#define M8xx_PCMCIA_POR_BSIZE_4KB   (0x0A << (31-4))
     786#define M8xx_PCMCIA_POR_BSIZE_8KB   (0x0B << (31-4))
     787#define M8xx_PCMCIA_POR_BSIZE_16KB  (0x09 << (31-4))
     788#define M8xx_PCMCIA_POR_BSIZE_32KB  (0x08 << (31-4))
     789#define M8xx_PCMCIA_POR_BSIZE_64KB  (0x18 << (31-4))
     790#define M8xx_PCMCIA_POR_BSIZE_128KB (0x19 << (31-4))
     791#define M8xx_PCMCIA_POR_BSIZE_256KB (0x1B << (31-4))
     792#define M8xx_PCMCIA_POR_BSIZE_512KB (0x1A << (31-4))
     793#define M8xx_PCMCIA_POR_BSIZE_1MB   (0x1E << (31-4))
     794#define M8xx_PCMCIA_POR_BSIZE_2MB   (0x1F << (31-4))
     795#define M8xx_PCMCIA_POR_BSIZE_4MB   (0x1D << (31-4))
     796#define M8xx_PCMCIA_POR_BSIZE_8MB   (0x1C << (31-4))
     797#define M8xx_PCMCIA_POR_BSIZE_16MB  (0x14 << (31-4))
     798#define M8xx_PCMCIA_POR_BSIZE_32MB  (0x15 << (31-4))
     799#define M8xx_PCMCIA_POR_BSIZE_64MB  (0x17 << (31-4))
     800
     801#define M8xx_PCMCIA_POR_PSHT(x)     (((x) & 0x0f) << (31-15))
     802#define M8xx_PCMCIA_POR_PSST(x)     (((x) & 0x0f) << (31-19))
     803#define M8xx_PCMCIA_POR_PSL(x)      (((x) & 0x1f) << (31-24))
     804#define M8xx_PCMCIA_POR_PPS_8       ((0) << (31-19))
     805#define M8xx_PCMCIA_POR_PPS_16      ((1) << (31-19))
     806
     807#define M8xx_PCMCIA_POR_PRS_MEM     ((0) << (31-28))
     808#define M8xx_PCMCIA_POR_PRS_ATT     ((2) << (31-28))
     809#define M8xx_PCMCIA_POR_PRS_IO      ((3) << (31-28))
     810#define M8xx_PCMCIA_POR_PRS_DMA     ((4) << (31-28))
     811#define M8xx_PCMCIA_POR_PRS_DML     ((5) << (31-28))
     812
     813#define M8xx_PCMCIA_POR_PSLOT_A     ((0) << (31-29))
     814#define M8xx_PCMCIA_POR_PSLOT_B     ((1) << (31-29))
     815
     816#define M8xx_PCMCIA_POR_WP          ((1) << (31-30))
     817#define M8xx_PCMCIA_POR_VALID       ((1) << (31-31))
     818
     819#define M8xx_PCMCIA_PGCR_CIRQLVL(x) (((x) & 0xff) << (31- 7))
     820#define M8xx_PCMCIA_PGCR_CSCHLVL(x) (((x) & 0xff) << (31-15))
     821#define M8xx_PCMCIA_PGCR_CDRQ_OFF    ((0) << (31-17))
     822#define M8xx_PCMCIA_PGCR_CDRQ_IOIS16 ((2) << (31-17))
     823#define M8xx_PCMCIA_PGCR_CDRQ_SPKR   ((3) << (31-17))
     824#define M8xx_PCMCIA_PGCR_COE         ((1) << (31-24))
     825#define M8xx_PCMCIA_PGCR_CRESET      ((1) << (31-25))
     826
     827#define M8xx_PCMCIA_PIPR_CAVS1      ((1) << (31- 0))
     828#define M8xx_PCMCIA_PIPR_CAVS2      ((1) << (31- 1))
     829#define M8xx_PCMCIA_PIPR_CAWP       ((1) << (31- 2))
     830#define M8xx_PCMCIA_PIPR_CACD2      ((1) << (31- 3))
     831#define M8xx_PCMCIA_PIPR_CACD1      ((1) << (31- 4))
     832#define M8xx_PCMCIA_PIPR_CABVD2     ((1) << (31- 5))
     833#define M8xx_PCMCIA_PIPR_CABVD1     ((1) << (31- 6))
     834#define M8xx_PCMCIA_PIPR_CARDY      ((1) << (31- 7))
     835#define M8xx_PCMCIA_PIPR_CBVS1      ((1) << (31-16))
     836#define M8xx_PCMCIA_PIPR_CBVS2      ((1) << (31-17))
     837#define M8xx_PCMCIA_PIPR_CBWP       ((1) << (31-18))
     838#define M8xx_PCMCIA_PIPR_CBCD2      ((1) << (31-19))
     839#define M8xx_PCMCIA_PIPR_CBCD1      ((1) << (31-20))
     840#define M8xx_PCMCIA_PIPR_CBBVD2     ((1) << (31-21))
     841#define M8xx_PCMCIA_PIPR_CBBVD1     ((1) << (31-22))
     842#define M8xx_PCMCIA_PIPR_CBRDY      ((1) << (31-23))
     843
     844
     845#define M8xx_SYPCR_BMT(x)       ((x)<<8)    /* Bus monitor timing */
     846#define M8xx_SYPCR_BME          (1<<7)      /* Bus monitor enable */
     847#define M8xx_SYPCR_SWF          (1<<3)      /* Software watchdog freeze */
     848#define M8xx_SYPCR_SWE          (1<<2)      /* Software watchdog enable */
     849#define M8xx_SYPCR_SWRI         (1<<1)      /* Watchdog reset/interrupt sel. */
     850#define M8xx_SYPCR_SWP          (1<<0)      /* Software watchdog prescale */
     851
     852/*
     853*************************************************************************
    770854*                        Memory Control Registers                       *
    771855*************************************************************************
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