Changeset b73e57b in rtems
- Timestamp:
- 07/09/99 17:08:48 (25 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 93180ea2
- Parents:
- cc17eba
- Files:
-
- 19 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/exec/score/cpu/sparc/asm.h
rcc17eba rb73e57b 45 45 /* XXX The following ifdef magic fixes the problem but results in a warning */ 46 46 /* XXX when compiling assembly code. */ 47 47 48 #ifndef __USER_LABEL_PREFIX__ 48 49 #define __USER_LABEL_PREFIX__ _ -
c/src/exec/score/cpu/sparc/cpu_asm.S
rcc17eba rb73e57b 499 499 */ 500 500 501 /* This is a fix for ERC32 with FPU rev.B or rev.C */ 502 503 #if defined(FPU_REVB) 504 505 501 506 mov %l0, %g5 502 subcc %l3, 0x11, %g0 507 and %l3, 0x0ff, %g4 508 subcc %g4, 0x08, %g0 509 be fpu_revb 510 subcc %g4, 0x11, %g0 503 511 bl dont_fix_pil 504 subcc % l3, 0x1f, %g0512 subcc %g4, 0x1f, %g0 505 513 bg dont_fix_pil 506 sll % l3, 8, %g4514 sll %g4, 8, %g4 507 515 and %g4, SPARC_PSR_PIL_MASK, %g4 508 516 andn %l0, SPARC_PSR_PIL_MASK, %g5 509 517 or %g4, %g5, %g5 518 srl %l0, 12, %g4 519 andcc %g4, 1, %g0 520 be dont_fix_pil 521 nop 522 ba,a enable_irq 523 524 525 fpu_revb: 526 srl %l0, 12, %g4 ! check if EF is set in %psr 527 andcc %g4, 1, %g0 528 be dont_fix_pil ! if FPU disabled than continue as normal 529 and %l3, 0xff, %g4 530 subcc %g4, 0x08, %g0 531 bne enable_irq ! if not a FPU exception then do two fmovs 532 set __sparc_fq, %g4 533 st %fsr, [%g4] ! if FQ is not empty and FQ[1] = fmovs 534 ld [%g4], %g4 ! than this is bug 3.14 535 srl %g4, 13, %g4 536 andcc %g4, 1, %g0 537 be dont_fix_pil 538 set __sparc_fq, %g4 539 std %fq, [%g4] 540 ld [%g4+4], %g4 541 set 0x81a00020, %g5 542 subcc %g4, %g5, %g0 543 bne,a dont_fix_pil2 544 wr %l0, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** 545 ba,a simple_return 546 547 enable_irq: 548 or %g5, SPARC_PSR_PIL_MASK, %g4 549 wr %g4, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** 550 nop; nop; nop 551 fmovs %f0, %f0 552 ba dont_fix_pil 553 fmovs %f0, %f0 554 555 .data 556 .global __sparc_fq 557 .align 8 558 __sparc_fq: 559 .word 0,0 560 561 .text 562 /* end of ERC32 FPU rev.B/C fix */ 563 564 #else 565 566 mov %l0, %g5 567 subcc %g4, 0x11, %g0 568 bl dont_fix_pil 569 subcc %g4, 0x1f, %g0 570 bg dont_fix_pil 571 sll %g4, 8, %g4 572 and %g4, SPARC_PSR_PIL_MASK, %g4 573 andn %l0, SPARC_PSR_PIL_MASK, %g5 574 or %g4, %g5, %g5 575 #endif 576 510 577 dont_fix_pil: 511 578 wr %g5, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** 579 dont_fix_pil2: 512 580 513 581 /* -
c/src/exec/score/cpu/sparc/erc32.h
rcc17eba rb73e57b 346 346 unsigned32 _level; \ 347 347 \ 348 sparc_disable_interrupts( _level); \348 _level = sparc_disable_interrupts(); \ 349 349 ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \ 350 350 ERC32_MEC.Interrupt_Force = (1 << (_source)); \ … … 362 362 unsigned32 _level; \ 363 363 \ 364 sparc_disable_interrupts( _level); \364 _level = sparc_disable_interrupts(); \ 365 365 ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \ 366 366 sparc_enable_interrupts( _level ); \ … … 371 371 unsigned32 _level; \ 372 372 \ 373 sparc_disable_interrupts( _level); \373 _level = sparc_disable_interrupts(); \ 374 374 ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \ 375 375 sparc_enable_interrupts( _level ); \ … … 381 381 unsigned32 _mask = 1 << (_source); \ 382 382 \ 383 sparc_disable_interrupts( _level); \383 _level = sparc_disable_interrupts(); \ 384 384 (_previous) = ERC32_MEC.Interrupt_Mask; \ 385 385 ERC32_MEC.Interrupt_Mask = _previous | _mask; \ … … 393 393 unsigned32 _mask = 1 << (_source); \ 394 394 \ 395 sparc_disable_interrupts( _level); \395 _level = sparc_disable_interrupts(); \ 396 396 ERC32_MEC.Interrupt_Mask = \ 397 397 (ERC32_MEC.Interrupt_Mask & ~_mask) | (_previous); \ … … 465 465 \ 466 466 __value = ((_value) & 0x0f); \ 467 sparc_disable_interrupts( _level); \467 _level = sparc_disable_interrupts(); \ 468 468 _control = _ERC32_MEC_Timer_Control_Mirror; \ 469 469 _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \ … … 494 494 \ 495 495 __value = ((_value) & 0x0f) << 8; \ 496 sparc_disable_interrupts( _level); \496 _level = sparc_disable_interrupts(); \ 497 497 _control = _ERC32_MEC_Timer_Control_Mirror; \ 498 498 _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \ -
c/src/exec/score/cpu/sparc/rtems/score/cpu.h
rcc17eba rb73e57b 726 726 #ifndef ASM 727 727 728 extern unsigned int sparc_disable_interrupts(); 729 extern void sparc_enable_interrupts(); 730 728 731 /* ISR handler macros */ 729 732 … … 734 737 735 738 #define _CPU_ISR_Disable( _level ) \ 736 sparc_disable_interrupts( _level)739 (_level) = sparc_disable_interrupts() 737 740 738 741 /* … … 744 747 #define _CPU_ISR_Enable( _level ) \ 745 748 sparc_enable_interrupts( _level ) 746 747 749 /* 748 750 * This temporarily restores the interrupt to _level before immediately … … 762 764 763 765 #define _CPU_ISR_Set_level( _newlevel ) \ 764 sparc_ set_interrupt_level( _newlevel)766 sparc_enable_interrupts( _newlevel << 8) 765 767 766 768 unsigned32 _CPU_ISR_Get_level( void ); … … 841 843 unsigned32 level; \ 842 844 \ 843 sparc_disable_interrupts( level); \845 level = sparc_disable_interrupts(); \ 844 846 asm volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \ 845 847 while (1); /* loop forever */ \ -
c/src/exec/score/cpu/sparc/rtems/score/sparc.h
rcc17eba rb73e57b 197 197 */ 198 198 199 /* 199 200 #define sparc_disable_interrupts( _level ) \ 200 201 do { \ … … 205 206 sparc_set_psr( _newlevel ); \ 206 207 } while ( 0 ) 207 208 208 209 #define sparc_enable_interrupts( _level ) \ 209 210 do { \ … … 215 216 sparc_set_psr( _tmp ); \ 216 217 } while ( 0 ) 218 */ 217 219 218 220 #define sparc_flash_interrupts( _level ) \ … … 224 226 } while ( 0 ) 225 227 228 /* 226 229 #define sparc_set_interrupt_level( _new_level ) \ 227 230 do { \ … … 234 237 sparc_set_psr( _new_psr_level ); \ 235 238 } while ( 0 ) 239 */ 236 240 237 241 #define sparc_get_interrupt_level( _level ) \ -
c/src/lib/libbsp/sparc/erc32/start/start.S
rcc17eba rb73e57b 151 151 */ 152 152 153 SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 80 - 82 153 TRAP( 0x80, SYM(syscall) ); ! 80 syscall SW trap 154 SOFT_TRAP; SOFT_TRAP; ! 81 - 82 154 155 TRAP( 0x83, SYM(window_flush_trap_handler) ); ! 83 flush windows SW trap 155 156 … … 213 214 set 0xfe080000, %g1 214 215 andcc %g1, %g2, %g0 215 bne 1f 216 set 0x00101000, %g1 ! 2M ROM, 4M RAM 217 ! set the Memory Configuration 218 st %g1, [ %g3 + ERC32_MEC_MEMORY_CONFIGURATION_OFFSET ] 219 220 set SYM(RAM_END), %sp ! End of work-space area 221 st %sp, [%g6] 216 bne 2f 217 218 /* Set the correct memory size in MEC memory config register */ 219 220 set SYM(PROM_SIZE), %l0 221 set 0, %l1 222 srl %l0, 18, %l0 223 1: 224 tst %l0 225 srl %l0, 1, %l0 226 bne,a 1b 227 inc %l1 228 sll %l1, 8, %l1 229 230 set SYM(RAM_SIZE), %l0 231 srl %l0, 19, %l0 232 1: 233 tst %l0 234 srl %l0, 1, %l0 235 bne,a 1b 236 inc %l1 237 sll %l1, 10, %l1 238 239 ! set the Memory Configuration 240 st %l1, [ %g3 + ERC32_MEC_MEMORY_CONFIGURATION_OFFSET ] 241 242 set SYM(RAM_START), %l1 ! Cannot use RAM_END due to bug in linker 243 set SYM(RAM_SIZE), %l2 244 add %l1, %l2, %sp 245 st %sp, [%g6] 246 222 247 223 248 set SYM(CLOCK_SPEED), %g6 ! Use 14 MHz in simulator … … 226 251 227 252 /* Common initialisation */ 228 1:253 2: 229 254 set WIM_INIT, %g1 ! Initialize WIM 230 255 mov %g1, %wim … … 299 324 PUBLIC(BSP_fatal_return) 300 325 SYM(BSP_fatal_return): 326 mov 1, %g1 301 327 ta 0 ! Halt if _main returns ... 302 328 nop -
c/src/lib/libbsp/sparc/erc32/startsis/startsis.S
rcc17eba rb73e57b 151 151 */ 152 152 153 SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 80 - 82 153 TRAP( 0x80, SYM(syscall) ); ! 80 syscall SW trap 154 SOFT_TRAP; SOFT_TRAP; ! 81 - 82 154 155 TRAP( 0x83, SYM(window_flush_trap_handler) ); ! 83 flush windows SW trap 155 156 … … 213 214 set 0xfe080000, %g1 214 215 andcc %g1, %g2, %g0 215 bne 1f 216 set 0x00101000, %g1 ! 2M ROM, 4M RAM 217 ! set the Memory Configuration 218 st %g1, [ %g3 + ERC32_MEC_MEMORY_CONFIGURATION_OFFSET ] 219 220 set SYM(RAM_END), %sp ! End of work-space area 221 st %sp, [%g6] 216 bne 2f 217 218 /* Set the correct memory size in MEC memory config register */ 219 220 set SYM(PROM_SIZE), %l0 221 set 0, %l1 222 srl %l0, 18, %l0 223 1: 224 tst %l0 225 srl %l0, 1, %l0 226 bne,a 1b 227 inc %l1 228 sll %l1, 8, %l1 229 230 set SYM(RAM_SIZE), %l0 231 srl %l0, 19, %l0 232 1: 233 tst %l0 234 srl %l0, 1, %l0 235 bne,a 1b 236 inc %l1 237 sll %l1, 10, %l1 238 239 ! set the Memory Configuration 240 st %l1, [ %g3 + ERC32_MEC_MEMORY_CONFIGURATION_OFFSET ] 241 242 set SYM(RAM_START), %l1 ! Cannot use RAM_END due to bug in linker 243 set SYM(RAM_SIZE), %l2 244 add %l1, %l2, %sp 245 st %sp, [%g6] 246 222 247 223 248 set SYM(CLOCK_SPEED), %g6 ! Use 14 MHz in simulator … … 226 251 227 252 /* Common initialisation */ 228 1:253 2: 229 254 set WIM_INIT, %g1 ! Initialize WIM 230 255 mov %g1, %wim … … 299 324 PUBLIC(BSP_fatal_return) 300 325 SYM(BSP_fatal_return): 326 mov 1, %g1 301 327 ta 0 ! Halt if _main returns ... 302 328 nop -
c/src/lib/libbsp/sparc/erc32/startup/bspclean.c
rcc17eba rb73e57b 31 31 /* 32 32 * "halt" by trapping to the simulator command line. 33 * set %g1 to 1 to detect clean exit. 33 34 */ 34 35 35 36 36 asm volatile( " ta 0" );37 asm volatile( "mov 1, %g1; ta 0" ); 37 38 } -
c/src/lib/libbsp/sparc/erc32/startup/linkcmds
rcc17eba rb73e57b 37 37 * _CLOCK_SPEED in Mhz (used to program the counter/timers) 38 38 * 39 * _PROM_SIZE size of PROM (permissible values are 4K, 8K, 16K40 * 32K, 64K, 128K, 256K, and 512K)39 * _PROM_SIZE size of PROM (permissible values are 128K, 256K, 40 * 512K, 1M, 2M, 4M, 8M and 16M) 41 41 * _RAM_SIZE size of RAM (permissible values are 256K, 512K, 42 * 1M B, 2Mb, 4Mb, 8Mb, 16Mb, and 32Mb)42 * 1M, 2M, 4M, 8M, 16M, and 32M) 43 43 * 44 * MAKE SURE THESE MATCH THE MEMORY DESCRIPTION SECTION!!!45 44 */ 46 45 47 /* 48 _CLOCK_SPEED = 10; 49 */ 46 /* Default values, can be overridden */ 50 47 51 _PROM_SIZE = 512K;52 _RAM_SIZE = 2M;48 _PROM_SIZE = 2M; 49 _RAM_SIZE = 4M; 53 50 54 51 _RAM_START = 0x02000000; 55 52 _RAM_END = _RAM_START + _RAM_SIZE; 56 RAM_END = _RAM_END;57 53 58 54 _PROM_START = 0x00000000; 59 55 _PROM_END = _PROM_START + _PROM_SIZE; 56 57 /* 58 * Alternate names without leading _. 59 */ 60 61 PROM_START = _PROM_START; 62 PROM_SIZE = _PROM_SIZE; 63 PROM_END = _PROM_END; 64 65 RAM_START = _RAM_START; 66 RAM_SIZE = _RAM_SIZE; 67 RAM_END = _RAM_END; 60 68 61 69 /* … … 66 74 ERC32_MEC = 0x01f80000; 67 75 76 /* these are the maximum values */ 77 68 78 MEMORY 69 79 { 70 rom : ORIGIN = 0x00000000, LENGTH = 512K71 ram : ORIGIN = 0x02000000, LENGTH = 2M80 rom : ORIGIN = 0x00000000, LENGTH = 16 81 ram : ORIGIN = 0x02000000, LENGTH = 32M 72 82 } 73 83 -
c/src/lib/libbsp/sparc/erc32/startup/spurious.c
rcc17eba rb73e57b 149 149 */ 150 150 151 asm volatile( " ta 0x0" );151 asm volatile( "mov 1, %g1; ta 0x0" ); 152 152 } 153 153 … … 178 178 */ 179 179 180 if (( trap == 5 || trap == 6 || trap == 0x83 ) || 181 (( trap >= 0x70 ) && ( trap <= 0x80 ))) 180 if (( trap == 5 || trap == 6 ) || 181 (( trap >= 0x11 ) && ( trap <= 0x1f )) || 182 (( trap >= 0x70 ) && ( trap <= 0x83 ))) 182 183 continue; 183 184 -
c/src/lib/libbsp/sparc/erc32/wrapup/Makefile.in
rcc17eba rb73e57b 18 18 BSP_PIECES=startup console clock timer gnatsupp 19 19 # pieces to pick up out of libcpu/sparc 20 CPU_PIECES=reg_win 20 CPU_PIECES=reg_win syscall 21 21 GENERIC_PIECES= 22 22 -
c/src/lib/libcpu/sparc/Makefile.in
rcc17eba rb73e57b 19 19 include $(RTEMS_ROOT)/make/directory.cfg 20 20 21 SUB_DIRS=reg_win 21 SUB_DIRS=reg_win syscall 22 22 23 23 Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status -
c/src/lib/libcpu/sparc/include/erc32.h
rcc17eba rb73e57b 346 346 unsigned32 _level; \ 347 347 \ 348 sparc_disable_interrupts( _level); \348 _level = sparc_disable_interrupts(); \ 349 349 ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \ 350 350 ERC32_MEC.Interrupt_Force = (1 << (_source)); \ … … 362 362 unsigned32 _level; \ 363 363 \ 364 sparc_disable_interrupts( _level); \364 _level = sparc_disable_interrupts(); \ 365 365 ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \ 366 366 sparc_enable_interrupts( _level ); \ … … 371 371 unsigned32 _level; \ 372 372 \ 373 sparc_disable_interrupts( _level); \373 _level = sparc_disable_interrupts(); \ 374 374 ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \ 375 375 sparc_enable_interrupts( _level ); \ … … 381 381 unsigned32 _mask = 1 << (_source); \ 382 382 \ 383 sparc_disable_interrupts( _level); \383 _level = sparc_disable_interrupts(); \ 384 384 (_previous) = ERC32_MEC.Interrupt_Mask; \ 385 385 ERC32_MEC.Interrupt_Mask = _previous | _mask; \ … … 393 393 unsigned32 _mask = 1 << (_source); \ 394 394 \ 395 sparc_disable_interrupts( _level); \395 _level = sparc_disable_interrupts(); \ 396 396 ERC32_MEC.Interrupt_Mask = \ 397 397 (ERC32_MEC.Interrupt_Mask & ~_mask) | (_previous); \ … … 465 465 \ 466 466 __value = ((_value) & 0x0f); \ 467 sparc_disable_interrupts( _level); \467 _level = sparc_disable_interrupts(); \ 468 468 _control = _ERC32_MEC_Timer_Control_Mirror; \ 469 469 _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \ … … 494 494 \ 495 495 __value = ((_value) & 0x0f) << 8; \ 496 sparc_disable_interrupts( _level); \496 _level = sparc_disable_interrupts(); \ 497 497 _control = _ERC32_MEC_Timer_Control_Mirror; \ 498 498 _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \ -
cpukit/score/cpu/sparc/asm.h
rcc17eba rb73e57b 45 45 /* XXX The following ifdef magic fixes the problem but results in a warning */ 46 46 /* XXX when compiling assembly code. */ 47 47 48 #ifndef __USER_LABEL_PREFIX__ 48 49 #define __USER_LABEL_PREFIX__ _ -
cpukit/score/cpu/sparc/cpu_asm.S
rcc17eba rb73e57b 499 499 */ 500 500 501 /* This is a fix for ERC32 with FPU rev.B or rev.C */ 502 503 #if defined(FPU_REVB) 504 505 501 506 mov %l0, %g5 502 subcc %l3, 0x11, %g0 507 and %l3, 0x0ff, %g4 508 subcc %g4, 0x08, %g0 509 be fpu_revb 510 subcc %g4, 0x11, %g0 503 511 bl dont_fix_pil 504 subcc % l3, 0x1f, %g0512 subcc %g4, 0x1f, %g0 505 513 bg dont_fix_pil 506 sll % l3, 8, %g4514 sll %g4, 8, %g4 507 515 and %g4, SPARC_PSR_PIL_MASK, %g4 508 516 andn %l0, SPARC_PSR_PIL_MASK, %g5 509 517 or %g4, %g5, %g5 518 srl %l0, 12, %g4 519 andcc %g4, 1, %g0 520 be dont_fix_pil 521 nop 522 ba,a enable_irq 523 524 525 fpu_revb: 526 srl %l0, 12, %g4 ! check if EF is set in %psr 527 andcc %g4, 1, %g0 528 be dont_fix_pil ! if FPU disabled than continue as normal 529 and %l3, 0xff, %g4 530 subcc %g4, 0x08, %g0 531 bne enable_irq ! if not a FPU exception then do two fmovs 532 set __sparc_fq, %g4 533 st %fsr, [%g4] ! if FQ is not empty and FQ[1] = fmovs 534 ld [%g4], %g4 ! than this is bug 3.14 535 srl %g4, 13, %g4 536 andcc %g4, 1, %g0 537 be dont_fix_pil 538 set __sparc_fq, %g4 539 std %fq, [%g4] 540 ld [%g4+4], %g4 541 set 0x81a00020, %g5 542 subcc %g4, %g5, %g0 543 bne,a dont_fix_pil2 544 wr %l0, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** 545 ba,a simple_return 546 547 enable_irq: 548 or %g5, SPARC_PSR_PIL_MASK, %g4 549 wr %g4, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** 550 nop; nop; nop 551 fmovs %f0, %f0 552 ba dont_fix_pil 553 fmovs %f0, %f0 554 555 .data 556 .global __sparc_fq 557 .align 8 558 __sparc_fq: 559 .word 0,0 560 561 .text 562 /* end of ERC32 FPU rev.B/C fix */ 563 564 #else 565 566 mov %l0, %g5 567 subcc %g4, 0x11, %g0 568 bl dont_fix_pil 569 subcc %g4, 0x1f, %g0 570 bg dont_fix_pil 571 sll %g4, 8, %g4 572 and %g4, SPARC_PSR_PIL_MASK, %g4 573 andn %l0, SPARC_PSR_PIL_MASK, %g5 574 or %g4, %g5, %g5 575 #endif 576 510 577 dont_fix_pil: 511 578 wr %g5, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** 579 dont_fix_pil2: 512 580 513 581 /* -
cpukit/score/cpu/sparc/rtems/asm.h
rcc17eba rb73e57b 45 45 /* XXX The following ifdef magic fixes the problem but results in a warning */ 46 46 /* XXX when compiling assembly code. */ 47 47 48 #ifndef __USER_LABEL_PREFIX__ 48 49 #define __USER_LABEL_PREFIX__ _ -
cpukit/score/cpu/sparc/rtems/score/cpu.h
rcc17eba rb73e57b 726 726 #ifndef ASM 727 727 728 extern unsigned int sparc_disable_interrupts(); 729 extern void sparc_enable_interrupts(); 730 728 731 /* ISR handler macros */ 729 732 … … 734 737 735 738 #define _CPU_ISR_Disable( _level ) \ 736 sparc_disable_interrupts( _level)739 (_level) = sparc_disable_interrupts() 737 740 738 741 /* … … 744 747 #define _CPU_ISR_Enable( _level ) \ 745 748 sparc_enable_interrupts( _level ) 746 747 749 /* 748 750 * This temporarily restores the interrupt to _level before immediately … … 762 764 763 765 #define _CPU_ISR_Set_level( _newlevel ) \ 764 sparc_ set_interrupt_level( _newlevel)766 sparc_enable_interrupts( _newlevel << 8) 765 767 766 768 unsigned32 _CPU_ISR_Get_level( void ); … … 841 843 unsigned32 level; \ 842 844 \ 843 sparc_disable_interrupts( level); \845 level = sparc_disable_interrupts(); \ 844 846 asm volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \ 845 847 while (1); /* loop forever */ \ -
cpukit/score/cpu/sparc/rtems/score/sparc.h
rcc17eba rb73e57b 197 197 */ 198 198 199 /* 199 200 #define sparc_disable_interrupts( _level ) \ 200 201 do { \ … … 205 206 sparc_set_psr( _newlevel ); \ 206 207 } while ( 0 ) 207 208 208 209 #define sparc_enable_interrupts( _level ) \ 209 210 do { \ … … 215 216 sparc_set_psr( _tmp ); \ 216 217 } while ( 0 ) 218 */ 217 219 218 220 #define sparc_flash_interrupts( _level ) \ … … 224 226 } while ( 0 ) 225 227 228 /* 226 229 #define sparc_set_interrupt_level( _new_level ) \ 227 230 do { \ … … 234 237 sparc_set_psr( _new_psr_level ); \ 235 238 } while ( 0 ) 239 */ 236 240 237 241 #define sparc_get_interrupt_level( _level ) \ -
make/custom/erc32.cfg
rcc17eba rb73e57b 61 61 # the wall time required to execute the RTEMS test suites. 62 62 # 63 # FPU_REVB (erc32_bsp) 64 # If defined, enables work-around for bug 3.14 in FPU rev.B or rev.C 65 # 63 66 64 67 define make-target-options … … 70 73 @echo "#define CONSOLE_USE_POLLED ~CONSOLE_USE_INTERRUPTS" >>$@ 71 74 @echo "/* #define SIMSPARC_FAST_IDLE 1 */" >>$@ 75 @echo "#define FPU_REVB 1" >>$@ 72 76 endef 73 77
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