Changeset b72e847b in rtems


Ignore:
Timestamp:
Aug 4, 2008, 8:35:25 PM (11 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.8
Children:
9f170c9
Parents:
bd029d87
Message:

2008-08-04 Joel Sherrill <joel.sherrill@…>

PR 1294/bsps

  • rtems/score/cpu.h, rtems/score/sparc.h: Correct prototype and usage of sparc_disable_interrupts.
Location:
cpukit/score/cpu/sparc
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • cpukit/score/cpu/sparc/ChangeLog

    rbd029d87 rb72e847b  
     12008-08-04      Joel Sherrill <joel.sherrill@OARcorp.com>
     2
     3        PR 1294/bsps
     4        * rtems/score/cpu.h, rtems/score/sparc.h: Correct prototype and usage
     5        of sparc_disable_interrupts.
     6
    172008-02-20      Alexandru Bugnar <a-bugnar@criticalsoftware.com>
    28

  • cpukit/score/cpu/sparc/rtems/score/cpu.h

    rbd029d87 rb72e847b  
    714714#ifndef ASM
    715715
    716 extern unsigned int sparc_disable_interrupts();
    717 extern void sparc_enable_interrupts();
    718 
    719716/*
    720717 *  ISR handler macros

  • cpukit/score/cpu/sparc/rtems/score/sparc.h

    rbd029d87 rb72e847b  
    206206/*
    207207 *  Manipulate the interrupt level in the psr
    208  *
    209  */
    210 
    211 /*
    212 #define sparc_disable_interrupts( _level ) \
    213   do { \
    214     register unsigned int _newlevel; \
    215     \
    216     sparc_get_psr( _level ); \
    217     (_newlevel) = (_level) | SPARC_PSR_PIL_MASK; \
    218     sparc_set_psr( _newlevel ); \
    219   } while ( 0 )
    220 
    221 #define sparc_enable_interrupts( _level ) \
    222   do { \
    223     unsigned int _tmp; \
    224     \
    225     sparc_get_psr( _tmp ); \
    226     _tmp &= ~SPARC_PSR_PIL_MASK; \
    227     _tmp |= (_level) & SPARC_PSR_PIL_MASK; \
    228     sparc_set_psr( _tmp ); \
    229   } while ( 0 )
    230 */
     208 */
     209
     210uint32_t sparc_disable_interrupts(void);
     211void sparc_enable_interrupts(uint32_t);
    231212 
    232213#define sparc_flash_interrupts( _level ) \
    … …  
    235216    \
    236217    sparc_enable_interrupts( (_level) ); \
    237     sparc_disable_interrupts( _ignored ); \
    238   } while ( 0 )
    239 
    240 /*
    241 #define sparc_set_interrupt_level( _new_level ) \
    242   do { \
    243     register uint32_t   _new_psr_level = 0; \
    244     \
    245     sparc_get_psr( _new_psr_level ); \
    246     _new_psr_level &= ~SPARC_PSR_PIL_MASK; \
    247     _new_psr_level |= \
    248       (((_new_level) << SPARC_PSR_PIL_BIT_POSITION) & SPARC_PSR_PIL_MASK); \
    249     sparc_set_psr( _new_psr_level ); \
    250   } while ( 0 )
    251 */
     218    _ignored = sparc_disable_interrupts(); \
     219  } while ( 0 )
    252220
    253221#define sparc_get_interrupt_level( _level ) \
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