Ignore:
Timestamp:
Jun 27, 2018, 6:54:13 AM (2 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
8f035cb
Parents:
2987c4f
git-author:
Sebastian Huber <sebastian.huber@…> (06/27/18 06:54:13)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/29/18 08:04:37)
Message:

riscv: Remove mstatus from thread context

The mstatus register contains no thread-specific state which must be
saved/restored during a context switch. Machine interrupts (MIE) must
be enabled during a context switch.

Create separate CPU_Interrupt_frame structure.

Update #3433.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h

    r2987c4f rb706b4a  
    3939#if __riscv_xlen == 32
    4040
    41 #define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 140
     41#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 128
    4242
    43 #define CPU_INTERRUPT_FRAME_SIZE 144
     43#define CPU_INTERRUPT_FRAME_SIZE 140
    4444
    4545#elif __riscv_xlen == 64
    4646
    47 #define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 280
     47#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 256
    4848
    49 #define CPU_INTERRUPT_FRAME_SIZE 288
     49#define CPU_INTERRUPT_FRAME_SIZE 280
    5050
    5151#endif /* __riscv_xlen */
     
    5656extern "C" {
    5757#endif
     58
     59typedef struct {
     60  unsigned long x[32];
     61  unsigned long mstatus;
     62  unsigned long mcause;
     63  unsigned long mepc;
     64} CPU_Interrupt_frame;
    5865
    5966#ifdef RTEMS_SMP
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