Changeset b706b4a in rtems


Ignore:
Timestamp:
Jun 27, 2018, 6:54:13 AM (10 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
8f035cb
Parents:
2987c4f
git-author:
Sebastian Huber <sebastian.huber@…> (06/27/18 06:54:13)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/29/18 08:04:37)
Message:

riscv: Remove mstatus from thread context

The mstatus register contains no thread-specific state which must be
saved/restored during a context switch. Machine interrupts (MIE) must
be enabled during a context switch.

Create separate CPU_Interrupt_frame structure.

Update #3433.

Location:
cpukit/score/cpu/riscv
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/riscv/include/rtems/score/cpu.h

    r2987c4f rb706b4a  
    4848#define CPU_INLINE_ENABLE_DISPATCH       FALSE
    4949#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
    50 #define CPU_ISR_PASSES_FRAME_POINTER 1
     50
     51#define CPU_ISR_PASSES_FRAME_POINTER FALSE
     52
    5153#define CPU_HARDWARE_FP                  FALSE
    5254#define CPU_SOFTWARE_FP                  FALSE
     
    7375  unsigned long x[32];
    7476
    75   /* Special purpose registers */
    76   unsigned long mstatus;
    77   unsigned long mcause;
    78   unsigned long mepc;
    7977  uint32_t isr_dispatch_disable;
    8078#ifdef RTEMS_SMP
     
    9088  double  some_float_register;
    9189} Context_Control_fp;
    92 
    93 typedef Context_Control CPU_Interrupt_frame;
    9490
    9591#define CPU_CONTEXT_FP_SIZE  0
  • cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h

    r2987c4f rb706b4a  
    3939#if __riscv_xlen == 32
    4040
    41 #define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 140
     41#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 128
    4242
    43 #define CPU_INTERRUPT_FRAME_SIZE 144
     43#define CPU_INTERRUPT_FRAME_SIZE 140
    4444
    4545#elif __riscv_xlen == 64
    4646
    47 #define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 280
     47#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 256
    4848
    49 #define CPU_INTERRUPT_FRAME_SIZE 288
     49#define CPU_INTERRUPT_FRAME_SIZE 280
    5050
    5151#endif /* __riscv_xlen */
     
    5656extern "C" {
    5757#endif
     58
     59typedef struct {
     60  unsigned long x[32];
     61  unsigned long mstatus;
     62  unsigned long mcause;
     63  unsigned long mepc;
     64} CPU_Interrupt_frame;
    5865
    5966#ifdef RTEMS_SMP
  • cpukit/score/cpu/riscv/riscv-context-initialize.c

    r2987c4f rb706b4a  
    3636#include <rtems/score/cpu.h>
    3737#include <rtems/score/address.h>
    38 #include <rtems/score/riscv-utility.h>
    3938
    4039void _CPU_Context_Initialize(
     
    6059
    6160  context->isr_dispatch_disable = 0;
    62 
    63   /* Enable interrupts and FP */
    64   context->mstatus = MSTATUS_FS | MSTATUS_MIE;
    6561}
  • cpukit/score/cpu/riscv/riscv-context-switch.S

    r2987c4f rb706b4a  
    4545        GET_SELF_CPU_CONTROL    a2
    4646        lw      a3, PER_CPU_ISR_DISPATCH_DISABLE(a2)
    47 
    48         /* Disable interrupts and store all registers */
    49         csrr    t0, mstatus
    50         SREG    t0, (32 * CPU_SIZEOF_POINTER)(a0)
    51 
    52         csrci   mstatus, RISCV_MSTATUS_MIE
    5347
    5448        SREG    x1, (1 * CPU_SIZEOF_POINTER)(a0)
     
    120114        LREG    x30, (30 * CPU_SIZEOF_POINTER)(a1)
    121115
    122         /* Load mstatus */
    123         LREG    x31, (32 * CPU_SIZEOF_POINTER)(a1)
    124         csrw    mstatus, x31
    125 
    126         LREG    x30, (30 * CPU_SIZEOF_POINTER)(a1)
    127 
    128116        LREG    x11, (11 * CPU_SIZEOF_POINTER)(a1)
    129117
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