Changeset b6f9b5f1 in rtems


Ignore:
Timestamp:
Mar 1, 2000, 6:08:53 PM (21 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
45a79f38
Parents:
8eacefcc
Message:

Added routines to get and set C3x IOF register. The code is conditionally
compiled and there is no comparable code for the C4x.

Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/c4x/c4xio.h

    r8eacefcc rb6f9b5f1  
    99
    1010/*
    11  *  The following section of C4x timer code is based on C40 specific
    12  *  timer code from Ran Cabell <rcabell@norfolk.infi.net>.  The
    13  *  only C3x/C4x difference spotted was the address of the timer.
    14  *  The names have been changed to be more RTEMS like.
     11 *  Address defines
    1512 */
    16 
    17 struct c4x_timer {
    18     volatile int tcontrol;
    19     volatile int r1[3];
    20     volatile int tcounter;
    21     volatile int r2[3];
    22     volatile int tperiod;
    23 };
    2413
    2514#ifdef _TMS320C40
     
    3019#endif
    3120
     21/* XXX how portable */
     22
     23/* C32 Internal Control Registers */
     24#define C4X_STRB0_REG   0x808064
     25#define C4X_STRB1_REG   0x808068
     26#define C4X_IOSTRB_REG  0x808060
     27
     28/* C32 Internal RAM Locations */
     29/* XXX how long */
     30#define C4X_RAM_BLK_0   0x87fe00
     31#define C4X_RAM_BLK_1   0x87ff00
     32
     33/*
     34 *  Data Structures to Overlay the Peripherals on the CPU
     35 */
     36
     37struct c4x_timer {
     38  volatile int tcontrol;
     39  volatile int r1[3];
     40  volatile int tcounter;
     41  volatile int r2[3];
     42  volatile int tperiod;
     43};
     44
     45
     46
     47
     48/*
     49 *  Timer Support Routines
     50 *
     51 *  The following section of C4x timer code is based on C40 specific
     52 *  timer code from Ran Cabell <rcabell@norfolk.infi.net>.  The
     53 *  only C3x/C4x difference spotted was the address of the timer.
     54 *  The names have been changed to be more RTEMS like.
     55 */
     56
     57#define c4x_timer_get_control( _timer ) (volatile int)(_timer->tcontrol)
     58
     59#define c4x_timer_set_control( _timer, _value ) \
     60  do { \
     61     (volatile int)(_timer->tcontrol) = _value; \
     62  } while (0);
     63
    3264#define c4x_timer_start( _timer ) \
    33     _timer->tcontrol=0x02c1
     65    c4x_timer_set_control(_timer, 0x02c1 )
    3466
    3567#define c4x_timer_stop( _timer ) _timer->tcontrol = 0
     
    4981  } while (0);
    5082
     83/*
     84 *  IO Flags
     85 *
     86 *  NOTE: iof on c3x, iiof on c4x
     87 */
     88
     89#ifdef _TMS320C40
     90
     91#else
     92
     93static inline unsigned32 c3x_get_iof( void )
     94{
     95  register unsigned32 iof_value;
     96
     97  __asm__ volatile ("ldi iof, %0" : "=r" (iof_value));
     98  return iof_value;
     99}
     100
     101static inline void c3x_set_iof( unsigned32 value )
     102{
     103  __asm__ volatile ("ldi  %0,iof" : : "g" (value) : "iof", "cc");
     104}
     105
     106#endif
     107
     108
    51109#endif
    52110/* end if include file */
  • cpukit/score/cpu/c4x/c4xio.h

    r8eacefcc rb6f9b5f1  
    99
    1010/*
    11  *  The following section of C4x timer code is based on C40 specific
    12  *  timer code from Ran Cabell <rcabell@norfolk.infi.net>.  The
    13  *  only C3x/C4x difference spotted was the address of the timer.
    14  *  The names have been changed to be more RTEMS like.
     11 *  Address defines
    1512 */
    16 
    17 struct c4x_timer {
    18     volatile int tcontrol;
    19     volatile int r1[3];
    20     volatile int tcounter;
    21     volatile int r2[3];
    22     volatile int tperiod;
    23 };
    2413
    2514#ifdef _TMS320C40
     
    3019#endif
    3120
     21/* XXX how portable */
     22
     23/* C32 Internal Control Registers */
     24#define C4X_STRB0_REG   0x808064
     25#define C4X_STRB1_REG   0x808068
     26#define C4X_IOSTRB_REG  0x808060
     27
     28/* C32 Internal RAM Locations */
     29/* XXX how long */
     30#define C4X_RAM_BLK_0   0x87fe00
     31#define C4X_RAM_BLK_1   0x87ff00
     32
     33/*
     34 *  Data Structures to Overlay the Peripherals on the CPU
     35 */
     36
     37struct c4x_timer {
     38  volatile int tcontrol;
     39  volatile int r1[3];
     40  volatile int tcounter;
     41  volatile int r2[3];
     42  volatile int tperiod;
     43};
     44
     45
     46
     47
     48/*
     49 *  Timer Support Routines
     50 *
     51 *  The following section of C4x timer code is based on C40 specific
     52 *  timer code from Ran Cabell <rcabell@norfolk.infi.net>.  The
     53 *  only C3x/C4x difference spotted was the address of the timer.
     54 *  The names have been changed to be more RTEMS like.
     55 */
     56
     57#define c4x_timer_get_control( _timer ) (volatile int)(_timer->tcontrol)
     58
     59#define c4x_timer_set_control( _timer, _value ) \
     60  do { \
     61     (volatile int)(_timer->tcontrol) = _value; \
     62  } while (0);
     63
    3264#define c4x_timer_start( _timer ) \
    33     _timer->tcontrol=0x02c1
     65    c4x_timer_set_control(_timer, 0x02c1 )
    3466
    3567#define c4x_timer_stop( _timer ) _timer->tcontrol = 0
     
    4981  } while (0);
    5082
     83/*
     84 *  IO Flags
     85 *
     86 *  NOTE: iof on c3x, iiof on c4x
     87 */
     88
     89#ifdef _TMS320C40
     90
     91#else
     92
     93static inline unsigned32 c3x_get_iof( void )
     94{
     95  register unsigned32 iof_value;
     96
     97  __asm__ volatile ("ldi iof, %0" : "=r" (iof_value));
     98  return iof_value;
     99}
     100
     101static inline void c3x_set_iof( unsigned32 value )
     102{
     103  __asm__ volatile ("ldi  %0,iof" : : "g" (value) : "iof", "cc");
     104}
     105
     106#endif
     107
     108
    51109#endif
    52110/* end if include file */
  • cpukit/score/cpu/c4x/rtems/tic4x/c4xio.h

    r8eacefcc rb6f9b5f1  
    99
    1010/*
    11  *  The following section of C4x timer code is based on C40 specific
    12  *  timer code from Ran Cabell <rcabell@norfolk.infi.net>.  The
    13  *  only C3x/C4x difference spotted was the address of the timer.
    14  *  The names have been changed to be more RTEMS like.
     11 *  Address defines
    1512 */
    16 
    17 struct c4x_timer {
    18     volatile int tcontrol;
    19     volatile int r1[3];
    20     volatile int tcounter;
    21     volatile int r2[3];
    22     volatile int tperiod;
    23 };
    2413
    2514#ifdef _TMS320C40
     
    3019#endif
    3120
     21/* XXX how portable */
     22
     23/* C32 Internal Control Registers */
     24#define C4X_STRB0_REG   0x808064
     25#define C4X_STRB1_REG   0x808068
     26#define C4X_IOSTRB_REG  0x808060
     27
     28/* C32 Internal RAM Locations */
     29/* XXX how long */
     30#define C4X_RAM_BLK_0   0x87fe00
     31#define C4X_RAM_BLK_1   0x87ff00
     32
     33/*
     34 *  Data Structures to Overlay the Peripherals on the CPU
     35 */
     36
     37struct c4x_timer {
     38  volatile int tcontrol;
     39  volatile int r1[3];
     40  volatile int tcounter;
     41  volatile int r2[3];
     42  volatile int tperiod;
     43};
     44
     45
     46
     47
     48/*
     49 *  Timer Support Routines
     50 *
     51 *  The following section of C4x timer code is based on C40 specific
     52 *  timer code from Ran Cabell <rcabell@norfolk.infi.net>.  The
     53 *  only C3x/C4x difference spotted was the address of the timer.
     54 *  The names have been changed to be more RTEMS like.
     55 */
     56
     57#define c4x_timer_get_control( _timer ) (volatile int)(_timer->tcontrol)
     58
     59#define c4x_timer_set_control( _timer, _value ) \
     60  do { \
     61     (volatile int)(_timer->tcontrol) = _value; \
     62  } while (0);
     63
    3264#define c4x_timer_start( _timer ) \
    33     _timer->tcontrol=0x02c1
     65    c4x_timer_set_control(_timer, 0x02c1 )
    3466
    3567#define c4x_timer_stop( _timer ) _timer->tcontrol = 0
     
    4981  } while (0);
    5082
     83/*
     84 *  IO Flags
     85 *
     86 *  NOTE: iof on c3x, iiof on c4x
     87 */
     88
     89#ifdef _TMS320C40
     90
     91#else
     92
     93static inline unsigned32 c3x_get_iof( void )
     94{
     95  register unsigned32 iof_value;
     96
     97  __asm__ volatile ("ldi iof, %0" : "=r" (iof_value));
     98  return iof_value;
     99}
     100
     101static inline void c3x_set_iof( unsigned32 value )
     102{
     103  __asm__ volatile ("ldi  %0,iof" : : "g" (value) : "iof", "cc");
     104}
     105
     106#endif
     107
     108
    51109#endif
    52110/* end if include file */
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