Changeset b6977f7 in rtems-docs

Aug 23, 2017, 7:23:23 AM (4 years ago)
Sebastian Huber <sebastian.huber@…>
5, am, master

cpu-supplement/powerpc: Rewrite

Remove obsolete and duplicated information. Reference the ABI
specifications. Add 64-bit caveats.

Update #3082.

1 edited


  • cpu-supplement/powerpc.rst

    rfeb6832 rb6977f7  
    77PowerPC Specific Information
    10 This chapter discusses the PowerPC architecture dependencies in this port of
    11 RTEMS.  The PowerPC family has a wide variety of implementations by a range of
    12 vendors.  Consequently, there are many, many CPU models within it.
    14 It is highly recommended that the PowerPC RTEMS application developer obtain
    15 and become familiar with the documentation for the processor being used as well
    16 as the specification for the revision of the PowerPC architecture which
    17 corresponds to that processor.
    19 **PowerPC Architecture Documents**
    21 For information on the PowerPC architecture, refer to the following documents
    22 available from Motorola and IBM:
    24 - *PowerPC Microprocessor Family: The Programming Environment*
    25   (Motorola Document MPRPPCFPE-01).
    27 - *IBM PPC403GB Embedded Controller User's Manual*.
    29 - *PoweRisControl MPC500 Family RCPU RISC Central Processing
    30   Unit Reference Manual* (Motorola Document RCPUURM/AD).
    32 - *PowerPC 601 RISC Microprocessor User's Manual*
    33   (Motorola Document MPR601UM/AD).
    35 - *PowerPC 603 RISC Microprocessor User's Manual*
    36   (Motorola Document MPR603UM/AD).
    38 - *PowerPC 603e RISC Microprocessor User's Manual*
    39   (Motorola Document MPR603EUM/AD).
    41 - *PowerPC 604 RISC Microprocessor User's Manual*
    42   (Motorola Document MPR604UM/AD).
    44 - *PowerPC MPC821 Portable Systems Microprocessor User's Manual*
    45   (Motorola Document MPC821UM/AD).
    47 - *PowerQUICC MPC860 User's Manual*
    48   (Motorola Document MPC860UM/AD).
    50 Motorola maintains an on-line electronic library for the PowerPC at the
    51 following URL:
    53 -
    55 This site has a a wealth of information and examples.  Many of the manuals are
    56 available from that site in electronic format.
    58 **PowerPC Processor Simulator Information**
    60 PSIM is a program which emulates the Instruction Set Architecture of the
    61 PowerPC microprocessor family.  It is reely available in source code form under
    62 the terms of the GNU General Public License (version 2 or later).  PSIM can be
    63 integrated with the GNU Debugger (gdb) to execute and debug PowerPC executables
    64 on non-PowerPC hosts.  PSIM supports the addition of user provided device
    65 models which can be used to allow one to develop and debug embedded
    66 applications using the simulator.
    68 The latest version of PSIM is included in GDB and enabled on pre-built binaries
    69 provided by the RTEMS Project.
    71 CPU Model Dependent Features
    72 ============================
    74 This section presents the set of features which vary across PowerPC
    75 implementations and are of importance to RTEMS.  The set of CPU model feature
    76 macros are defined in the file ``cpukit/score/cpu/powerpc/powerpc.h`` based
    77 upon the particular CPU model specified on the compilation command line.
    79 Alignment
    80 ---------
    82 The macro PPC_ALIGNMENT is set to the PowerPC model's worst case alignment
    83 requirement for data types on a byte boundary.  This value is used to derive
    84 the alignment restrictions for memory allocated from regions and partitions.
    86 Cache Alignment
    87 ---------------
    89 The macro PPC_CACHE_ALIGNMENT is set to the line size of the cache.  It is used
    90 to align the entry point of critical routines so that as much code as possible
    91 can be retrieved with the initial read into cache.  This is done for the
    92 interrupt handler as well as the context switch routines.
    94 In addition, the "shortcut" data structure used by the PowerPC implementation
    95 to ease access to data elements frequently accessed by RTEMS routines
    96 implemented in assembly language is aligned using this value.
    98 Maximum Interrupts
    99 ------------------
    101 The macro PPC_INTERRUPT_MAX is set to the number of exception sources supported
    102 by this PowerPC model.
    104 Has Double Precision Floating Point
    105 -----------------------------------
    107 The macro PPC_HAS_DOUBLE is set to 1 to indicate that the PowerPC model has
    108 support for double precision floating point numbers.  This is important because
    109 the floating point registers need only be four bytes wide (not eight) if double
    110 precision is not supported.
    112 Critical Interrupts
    113 -------------------
    115 The macro PPC_HAS_RFCI is set to 1 to indicate that the PowerPC model has the
    116 Critical Interrupt capability as defined by the IBM 403 models.
    118 Use Multiword Load/Store Instructions
    119 -------------------------------------
    121 The macro PPC_USE_MULTIPLE is set to 1 to indicate that multiword load and
    122 store instructions should be used to perform context switch operations.  The
    123 relative efficiency of multiword load and store instructions versus an
    124 equivalent set of single word load and store instructions varies based upon the
    125 PowerPC model.
    127 Instruction Cache Size
    128 ----------------------
    130 The macro PPC_I_CACHE is set to the size in bytes of the instruction cache.
    132 Data Cache Size
    133 ---------------
    135 The macro PPC_D_CACHE is set to the size in bytes of the data cache.
    137 Debug Model
    138 -----------
    140 The macro PPC_DEBUG_MODEL is set to indicate the debug support features present
    141 in this CPU model.  The following debug support feature sets are currently
    142 supported:
    145     indicates that the single-step trace enable (SE) and branch trace enable
    146     (BE) bits in the MSR are supported by this CPU model.
    149     indicates that only the single-step trace enable (SE) bit in the MSR is
    150     supported by this CPU model.
    152 *``PPC_DEBUG_MODEL_IBM4xx``*
    153     indicates that the debug exception enable (DE) bit in the MSR is supported
    154     by this CPU model.  At this time, this particular debug feature set has
    155     only been seen in the IBM 4xx series.
    157 Low Power Model
    158 ~~~~~~~~~~~~~~~
    160 The macro PPC_LOW_POWER_MODE is set to indicate the low power model supported
    161 by this CPU model.  The following low power modes are currently supported.
    164     indicates that this CPU model has no low power mode support.
    167     indicates that this CPU model follows the low power model defined for the
    168     PPC603e.
    21353   with software floating point support and no AltiVec
    215 Calling Conventions
    216 ===================
     55#. ``me6500/m64``: 64-bit instruction set for e6500 core with FPU and
     56   AltiVec
    218 RTEMS supports the Embedded Application Binary Interface (EABI) calling
    219 convention.  Documentation for EABI is available by sending a message with a
    220 subject line of "EABI" to
     58#. ``me6500/m64/nof/noaltivec``: 64-bit instruction set for e6500 core
     59   with software floating point support and no AltiVec
    222 Programming Model
    223 -----------------
     61Application Binary Interface
    225 This section discusses the programming model for the PowerPC architecture.
     64In 32-bit PowerPC configurations the ABI defined by
     65`Power Architecture 32-bit Application Binary Interface Supplement 1.0 - Embedded <>`_
     66is used.
    227 Non-Floating Point Registers
    228 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    230 The PowerPC architecture defines thirty-two non-floating point registers
    231 directly visible to the programmer.  In thirty-two bit implementations, each
    232 register is thirty-two bits wide.  In sixty-four bit implementations, each
    233 register is sixty-four bits wide.
    235 These registers are referred to as ``gpr0`` to ``gpr31``.
    237 Some of the registers serve defined roles in the EABI programming model.  The
    238 following table describes the role of each of these registers:
    240 +---------------+----------------+------------------------------+
    241 | Register Name | Alternate Name |         Description          |
    242 +---------------+----------------+------------------------------+
    243 |      r1       |      sp        |         stack pointer        |
    244 +---------------+----------------+------------------------------+
    245 |               |                |  global pointer to the Small |
    246 |      r2       |      na        |     Constant Area (SDA2)     |
    247 +---------------+----------------+------------------------------+
    248 |    r3 - r12   |      na        | parameter and result passing |
    249 +---------------+----------------+------------------------------+
    250 |               |                |  global pointer to the Small |
    251 |      r13      |      na        |         Data Area (SDA)      |
    252 +---------------+----------------+------------------------------+
    254 Floating Point Registers
    255 ~~~~~~~~~~~~~~~~~~~~~~~~
    257 The PowerPC architecture includes thirty-two, sixty-four bit floating point
    258 registers.  All PowerPC floating point instructions interpret these registers
    259 as 32 double precision floating point registers, regardless of whether the
    260 processor has 64-bit or 32-bit implementation.
    262 The floating point status and control register (fpscr) records exceptions and
    263 the type of result generated by floating-point operations.  Additionally, it
    264 controls the rounding mode of operations and allows the reporting of floating
    265 exceptions to be enabled or disabled.
     68In 64-bit PowerPC configurations the ABI defined by
     69`Power Architecture 64-Bit ELF V2 ABI Specification, Version 1.1 <>`_
     70is used.
    26772Special Registers
    268 ~~~~~~~~~~~~~~~~~
    270 The PowerPC architecture includes a number of special registers which are
    271 critical to the programming model:
     75The following special-purpose registers are used by RTEMS:
    27377*Special-Purpose Register General 0 (SPRG0)*
    274     On SMP configurations, this register contains the address of the per-CPU
     78    In SMP configurations, this register contains the address of the per-CPU
    27579    control of the processor.
    28286    This register contains the address of interrupt stack area begin.
    284 *Machine State Register*
    285     The MSR contains the processor mode, power management mode, endian mode,
    286     exception information, privilege level, floating point available and
    287     floating point excepiton mode, address translation information and the
    288     exception prefix.
    290 *Link Register*
    291     The LR contains the return address after a function call.  This register
    292     must be saved before a subsequent subroutine call can be made.  The use of
    293     this register is discussed further in the *Call and Return Mechanism*
    294     section below.
    296 *Count Register*
    297     The CTR contains the iteration variable for some loops.  It may also be
    298     used for indirect function calls and jumps.
    300 Call and Return Mechanism
    301 -------------------------
    303 The PowerPC architecture supports a simple yet effective call and return
    304 mechanism.  A subroutine is invoked via the "branch and link" (``bl``) and
    305 "brank and link absolute" (``bla``) instructions.  This instructions place the
    306 return address in the Link Register (LR).  The callee returns to the caller by
    307 executing a "branch unconditional to the link register" (``blr``) instruction.
    308 Thus the callee returns to the caller via a jump to the return address which is
    309 stored in the LR.
    311 The previous contents of the LR are not automatically saved by either the
    312 ``bl`` or ``bla``.  It is the responsibility of the callee to save the contents
    313 of the LR before invoking another subroutine.  If the callee invokes another
    314 subroutine, it must restore the LR before executing the ``blr`` instruction to
    315 return to the caller.
    317 It is important to note that the PowerPC subroutine call and return mechanism
    318 does not automatically save and restore any registers.
    320 The LR may be accessed as special purpose register 8 (``SPR8``) using the "move
    321 from special register" (``mfspr``) and "move to special register" (``mtspr``)
    322 instructions.
    324 Calling Mechanism
    325 -----------------
    327 All RTEMS directives are invoked using the regular PowerPC EABI calling
    328 convention via the ``bl`` or``bla`` instructions.
    330 Register Usage
    331 --------------
    333 As discussed above, the call instruction does not automatically save any
    334 registers.  It is the responsibility of the callee to save and restore any
    335 registers which must be preserved across subroutine calls.  The callee is
    336 responsible for saving callee-preserved registers to the program stack and
    337 restoring them before returning to the caller.
    339 Parameter Passing
    340 -----------------
    342 RTEMS assumes that arguments are placed in the general purpose registers with
    343 the first argument in register 3 (``r3``), the second argument in general
    344 purpose register 4 (``r4``), and so forth until the seventh argument is in
    345 general purpose register 10 (``r10``).  If there are more than seven arguments,
    346 then subsequent arguments are placed on the program stack.  The following
    347 pseudo-code illustrates the typical sequence used to call a RTEMS directive
    348 with three (3) arguments:
    350 .. code-block:: c
    352     load third argument into r5
    353     load second argument into r4
    354     load first argument into r3
    355     invoke directive
    35788Memory Model
    360 Flat Memory Model
    361 -----------------
    363 The PowerPC architecture supports a variety of memory models.  RTEMS supports
    364 the PowerPC using a flat memory model with paging disabled.  In this mode, the
    365 PowerPC automatically converts every address from a logical to a physical
    366 address each time it is used.  The PowerPC uses information provided in the
    367 Block Address Translation (BAT) to convert these addresses.
    369 Implementations of the PowerPC architecture may be thirty-two or sixty-four
    370 bit.  The PowerPC architecture supports a flat thirty-two or sixty-four bit
    371 address space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4
    372 gigabytes) in thirty-two bit implementations or to 0xFFFFFFFFFFFFFFFF in
    373 sixty-four bit implementations.  Each address is represented by either a
    374 thirty-two bit or sixty-four bit value and is byte addressable.  The address
    375 may be used to reference a single byte, half-word (2-bytes), word (4 bytes), or
    376 in sixty-four bit implementations a doubleword (8 bytes).  Memory accesses
    377 within the address space are performed in big or little endian fashion by the
    378 PowerPC based upon the current setting of the Little-endian mode enable bit
    379 (LE) in the Machine State Register (MSR).  While the processor is in big endian
    380 mode, memory accesses which are not properly aligned generate an "alignment
    381 exception" (vector offset 0x00600).  In little endian mode, the PowerPC
    382 architecture does not require the processor to generate alignment exceptions.
    384 The following table lists the alignment requirements for a variety of data
    385 accesses:
    387 ==============  ======================
    388 Data Type       Alignment Requirement
    389 ==============  ======================
    390 byte            1
    391 half-word       2
    392 word            4
    393 doubleword      8
    394 ==============  ======================
    396 Doubleword load and store operations are only available in PowerPC CPU models
    397 which are sixty-four bit implementations.
    399 RTEMS does not directly support any PowerPC Memory Management Units, therefore,
    400 virtual memory or segmentation systems involving the PowerPC are not supported.
     91The memory model is flat.
    40293Interrupt Processing
    405 Although RTEMS hides many of the processor dependent details of interrupt
    406 processing, it is important to understand how the RTEMS interrupt manager is
    407 mapped onto the processor's unique architecture. Discussed in this chapter are
    408 the PowerPC's interrupt response and control mechanisms as they pertain to
    409 RTEMS.
    411 RTEMS and associated documentation uses the terms interrupt and vector.  In the
    412 PowerPC architecture, these terms correspond to exception and exception
    413 handler, respectively.  The terms will be used interchangeably in this manual.
    415 Synchronous Versus Asynchronous Exceptions
    416 ------------------------------------------
    418 In the PowerPC architecture exceptions can be either precise or imprecise and
    419 either synchronous or asynchronous.  Asynchronous exceptions occur when an
    420 external event interrupts the processor.  Synchronous exceptions are caused by
    421 the actions of an instruction. During an exception SRR0 is used to calculate
    422 where instruction processing should resume.  All instructions prior to the
    423 resume instruction will have completed execution.  SRR1 is used to store the
    424 machine status.
    426 There are two asynchronous nonmaskable, highest-priority exceptions system
    427 reset and machine check.  There are two asynchrononous maskable low-priority
    428 exceptions external interrupt and decrementer.  Nonmaskable execptions are
    429 never delayed, therefore if two nonmaskable, asynchronous exceptions occur in
    430 immediate succession, the state information saved by the first exception may be
    431 overwritten when the subsequent exception occurs.
    433 The PowerPC arcitecure defines one imprecise exception, the imprecise floating
    434 point enabled exception.  All other synchronous exceptions are precise.  The
    435 synchronization occuring during asynchronous precise exceptions conforms to the
    436 requirements for context synchronization.
    438 Vectoring of Interrupt Handler
    439 ------------------------------
    441 Upon determining that an exception can be taken the PowerPC automatically
    442 performs the following actions:
    444 - an instruction address is loaded into SRR0
    446 - bits 33-36 and 42-47 of SRR1 are loaded with information specific to the
    447   exception.
    449 - bits 0-32, 37-41, and 48-63 of SRR1 are loaded with corresponding bits from
    450   the MSR.
    452 - the MSR is set based upon the exception type.
    454 - instruction fetch and execution resumes, using the new MSR value, at a
    455   location specific to the execption type.
    457 If the interrupt handler was installed as an RTEMS interrupt handler, then upon
    458 receipt of the interrupt, the processor passes control to the RTEMS interrupt
    459 handler which performs the following actions:
    461 - saves the state of the interrupted task on it's stack,
    463 - saves all registers which are not normally preserved by the calling sequence
    464   so the user's interrupt service routine can be written in a high-level
    465   language.
    467 - if this is the outermost (i.e. non-nested) interrupt, then the RTEMS
    468   interrupt handler switches from the current stack to the interrupt stack,
    470 - enables exceptions,
    472 - invokes the vectors to a user interrupt service routine (ISR).
    474 Asynchronous interrupts are ignored while exceptions are disabled.  Synchronous
    475 interrupts which occur while are disabled result in the CPU being forced into
    476 an error mode.
    478 A nested interrupt is processed similarly with the exception that the current
    479 stack need not be switched to the interrupt stack.
    48196Interrupt Levels
    484 The PowerPC architecture supports only a single external asynchronous interrupt
    485 source.  This interrupt source may be enabled and disabled via the External
    486 Interrupt Enable (EE) bit in the Machine State Register (MSR).  Thus only two
    487 level (enabled and disabled) of external device interrupt priorities are
    488 directly supported by the PowerPC architecture.
     99There are exactly two interrupt levels on PowerPC with respect to RTEMS.  Level
     100zero corresponds to interrupts enabled.  Level one corresponds to interrupts
    490 Some PowerPC implementations include a Critical Interrupt capability which is
    491 often used to receive interrupts from high priority external devices.
     103Interrupt Stack
    493 The RTEMS interrupt level mapping scheme for the PowerPC is not a numeric level
    494 as on most RTEMS ports.  It is a bit mapping in which the least three
    495 significiant bits of the interrupt level are mapped directly to the enabling of
    496 specific interrupt sources as follows:
    498 *Critical Interrupt*
    499     Setting bit 0 (the least significant bit) of the interrupt level enables
    500     the Critical Interrupt source, if it is available on this CPU model.
    502 *Machine Check*
    503     Setting bit 1 of the interrupt level enables Machine Check execptions.
    505 *External Interrupt*
    506     Setting bit 2 of the interrupt level enables External Interrupt execptions.
    508 All other bits in the RTEMS task interrupt level are ignored.
     106The interrupt stack size can be configured via the
     107``CONFIGURE_INTERRUPT_STACK_SIZE`` application configuration option.
    510109Default Fatal Error Processing
    513 The default fatal error handler for this architecture performs the following
    514 actions:
    516 - places the error code in r3, and
    518 - executes a trap instruction which results in a Program Exception.
    520 If the Program Exception returns, then the following actions are performed:
    522 - disables all processor exceptions by loading a 0 into the MSR, and
    524 - goes into an infinite loop to simulate a halt processor instruction.
     112The default fatal error handler is BSP-specific.
    526114Symmetric Multiprocessing
    535123Thread-local storage is supported.
    537 Board Support Packages
    538 ======================
     12564-bit Caveats
    540 System Reset
    541 ------------
     128* The thread pointer is `r13` in contrast to `r2` used in the 32-bit ABI.
    543 An RTEMS based application is initiated or re-initiated when the PowerPC
    544 processor is reset.  The PowerPC architecture defines a Reset Exception, but
    545 leaves the details of the CPU state as implementation specific.  Please refer
    546 to the User's Manual for the CPU model in question.
     130* The TOC pointer is `r2`.  It must be initialized as part of the C run-time
     131  setup.  A valid stack pointer is not enough to call C functions.  They may
     132  use the TOC to get addresses and constants.
    548 In general, at power-up the PowerPC begin execution at address 0xFFF00100 in
    549 supervisor mode with all exceptions disabled.  For soft resets, the CPU will
    550 vector to either 0xFFF00100 or 0x00000100 depending upon the setting of the
    551 Exception Prefix bit in the MSR.  If during a soft reset, a Machine Check
    552 Exception occurs, then the CPU may execute a hard reset.
     134* The TOC must be within the first 4GiB of the address space.  This simplifies
     135  the interrupt prologue.
    554 Processor Initialization
    555 ------------------------
     138  `PPC_REG_CMP` macros are available for assembly code to provide register size
     139  operations selected by the GCC `m32` and `m64` options.
    557 If this PowerPC implementation supports on-chip caching and this is to be
    558 utilized, then it should be enabled during the reset application initialization
    559 code.  On-chip caching has been observed to prevent some emulators from working
    560 properly, so it may be necessary to run with caching disabled to use these
    561 emulators.
    563 In addition to the requirements described in the*Board Support Packages*
    564 chapter of the RTEMS C Applications User's Manual for the reset code which is
    565 executed before the call to ``rtems_initialize_executive``, the PowrePC version
    566 has the following specific requirements:
    568 - Must leave the PR bit of the Machine State Register (MSR) set to 0 so the
    569   PowerPC remains in the supervisor state.
    571 - Must set stack pointer (sp or r1) such that a minimum stack size of
    572   MINIMUM_STACK_SIZE bytes is provided for the RTEMS initialization sequence.
    574 - Must disable all external interrupts (i.e. clear the EI (EE) bit of the
    575   machine state register).
    577 - Must enable traps so window overflow and underflow conditions can be properly
    578   handled.
    580 - Must initialize the PowerPC's initial Exception Table with default handlers.
     141* The `MSR[CM]` bit must be set all the time, otherwise the MMU translation my
     142  yield unexpected results.  The `EPCR[ICM]` or `EPCR[GICM]` bits may be used
     143  to enable the 64-bit compute mode for exceptions.
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