Changeset b2ec2d15 in rtems


Ignore:
Timestamp:
Apr 22, 2014, 5:46:56 AM (5 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
3fe1e43
Parents:
e5120a5
git-author:
Sebastian Huber <sebastian.huber@…> (04/22/14 05:46:56)
git-committer:
Sebastian Huber <sebastian.huber@…> (04/28/14 07:26:19)
Message:

sparc: Optimize context switch

The registers g2 through g4 are reserved for applications. GCC uses
them as volatile registers by default. So they are treated like
volatile registers in RTEMS as well.

Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/shared/irq_asm.S

    re5120a5 rb2ec2d15  
    5353        PUBLIC(_CPU_Context_switch)
    5454SYM(_CPU_Context_switch):
    55         std     %g2, [%o0 + G2_OFFSET]       ! save the global registers
    56         std     %g4, [%o0 + G4_OFFSET]
     55        st      %g5, [%o0 + G5_OFFSET]       ! save the global registers
    5756        std     %g6, [%o0 + G6_OFFSET]
    5857
     
    186185        nop
    187186
    188         ldd     [%o1 + G2_OFFSET], %g2        ! restore the global registers
    189         ldd     [%o1 + G4_OFFSET], %g4
     187        ld      [%o1 + G5_OFFSET], %g5        ! restore the global registers
    190188        ldd     [%o1 + G6_OFFSET], %g6
    191189
  • cpukit/score/cpu/sparc/cpu.c

    re5120a5 rb2ec2d15  
    3636  )
    3737
    38 SPARC_ASSERT_OFFSET(g2_g3, G2);
    39 SPARC_ASSERT_OFFSET(g4, G4);
    4038SPARC_ASSERT_OFFSET(g5, G5);
    4139SPARC_ASSERT_OFFSET(g6, G6);
    4240SPARC_ASSERT_OFFSET(g7, G7);
    43 SPARC_ASSERT_OFFSET(l0, L0);
    44 SPARC_ASSERT_OFFSET(l1, L1);
     41
     42RTEMS_STATIC_ASSERT(
     43  offsetof(Context_Control, l0_and_l1) == L0_OFFSET,
     44  Context_Control_offset_L0
     45);
     46
     47RTEMS_STATIC_ASSERT(
     48  offsetof(Context_Control, l0_and_l1) + 4 == L1_OFFSET,
     49  Context_Control_offset_L1
     50);
     51
    4552SPARC_ASSERT_OFFSET(l2, L2);
    4653SPARC_ASSERT_OFFSET(l3, L3);
     
    6269SPARC_ASSERT_OFFSET(isr_dispatch_disable, ISR_DISPATCH_DISABLE_STACK);
    6370
    64 RTEMS_STATIC_ASSERT(
    65   (offsetof(Context_Control, g2_g3)
    66      + offsetof(Context_Control, g4)) / 2 == G3_OFFSET,
    67   Context_Control_offset_G3
    68 );
    69 
    7071/*
    7172 *  This initializes the set of opcodes placed in each trap
  • cpukit/score/cpu/sparc/rtems/score/cpu.h

    re5120a5 rb2ec2d15  
    405405 * for the SPARC architecture according to "SYSTEM V APPLICATION BINARY
    406406 * INTERFACE - SPARC Processor Supplement", Third Edition.
     407 *
     408 * The registers g2 through g4 are reserved for applications.  GCC uses them as
     409 * volatile registers by default.  So they are treated like volatile registers
     410 * in RTEMS as well.
    407411 */
    408412typedef struct {
    409   /**
    410    * Using a double g2_g3 will put everything in this structure on a
    411    * double word boundary which allows us to use double word loads
    412    * and stores safely in the context switch.
    413    */
    414   double     g2_g3;
    415   /** This will contain the contents of the g4 register. */
    416   uint32_t   g4;
     413  /** This will contain reserved space for alignment. */
     414  uint32_t   reserved_for_alignment;
    417415  /** This will contain the contents of the g5 register. */
    418416  uint32_t   g5;
     
    422420  uint32_t   g7;
    423421
    424   /** This will contain the contents of the l0 register. */
    425   uint32_t   l0;
    426   /** This will contain the contents of the l1 register. */
    427   uint32_t   l1;
     422  /**
     423   * This will contain the contents of the l0 and l1 registers.
     424   *
     425   * Using a double l0_and_l1 will put everything in this structure on a double
     426   * word boundary which allows us to use double word loads and stores safely
     427   * in the context switch.
     428   */
     429  double     l0_and_l1;
    428430  /** This will contain the contents of the l2 register. */
    429431  uint32_t   l2;
     
    489491
    490492/** This macro defines an offset into the context for use in assembly. */
    491 #define G2_OFFSET    0x00
    492 /** This macro defines an offset into the context for use in assembly. */
    493 #define G3_OFFSET    0x04
    494 /** This macro defines an offset into the context for use in assembly. */
    495 #define G4_OFFSET    0x08
    496 /** This macro defines an offset into the context for use in assembly. */
    497 #define G5_OFFSET    0x0C
    498 /** This macro defines an offset into the context for use in assembly. */
    499 #define G6_OFFSET    0x10
    500 /** This macro defines an offset into the context for use in assembly. */
    501 #define G7_OFFSET    0x14
    502 
    503 /** This macro defines an offset into the context for use in assembly. */
    504 #define L0_OFFSET    0x18
    505 /** This macro defines an offset into the context for use in assembly. */
    506 #define L1_OFFSET    0x1C
    507 /** This macro defines an offset into the context for use in assembly. */
    508 #define L2_OFFSET    0x20
    509 /** This macro defines an offset into the context for use in assembly. */
    510 #define L3_OFFSET    0x24
    511 /** This macro defines an offset into the context for use in assembly. */
    512 #define L4_OFFSET    0x28
    513 /** This macro defines an offset into the context for use in assembly. */
    514 #define L5_OFFSET    0x2C
    515 /** This macro defines an offset into the context for use in assembly. */
    516 #define L6_OFFSET    0x30
    517 /** This macro defines an offset into the context for use in assembly. */
    518 #define L7_OFFSET    0x34
    519 
    520 /** This macro defines an offset into the context for use in assembly. */
    521 #define I0_OFFSET    0x38
    522 /** This macro defines an offset into the context for use in assembly. */
    523 #define I1_OFFSET    0x3C
    524 /** This macro defines an offset into the context for use in assembly. */
    525 #define I2_OFFSET    0x40
    526 /** This macro defines an offset into the context for use in assembly. */
    527 #define I3_OFFSET    0x44
    528 /** This macro defines an offset into the context for use in assembly. */
    529 #define I4_OFFSET    0x48
    530 /** This macro defines an offset into the context for use in assembly. */
    531 #define I5_OFFSET    0x4C
    532 /** This macro defines an offset into the context for use in assembly. */
    533 #define I6_FP_OFFSET 0x50
    534 /** This macro defines an offset into the context for use in assembly. */
    535 #define I7_OFFSET    0x54
    536 
    537 /** This macro defines an offset into the context for use in assembly. */
    538 #define O6_SP_OFFSET 0x58
    539 /** This macro defines an offset into the context for use in assembly. */
    540 #define O7_OFFSET    0x5C
    541 
    542 /** This macro defines an offset into the context for use in assembly. */
    543 #define PSR_OFFSET   0x60
    544 /** This macro defines an offset into the context for use in assembly. */
    545 #define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x64
     493#define G5_OFFSET    0x04
     494/** This macro defines an offset into the context for use in assembly. */
     495#define G6_OFFSET    0x08
     496/** This macro defines an offset into the context for use in assembly. */
     497#define G7_OFFSET    0x0C
     498
     499/** This macro defines an offset into the context for use in assembly. */
     500#define L0_OFFSET    0x10
     501/** This macro defines an offset into the context for use in assembly. */
     502#define L1_OFFSET    0x14
     503/** This macro defines an offset into the context for use in assembly. */
     504#define L2_OFFSET    0x18
     505/** This macro defines an offset into the context for use in assembly. */
     506#define L3_OFFSET    0x1C
     507/** This macro defines an offset into the context for use in assembly. */
     508#define L4_OFFSET    0x20
     509/** This macro defines an offset into the context for use in assembly. */
     510#define L5_OFFSET    0x24
     511/** This macro defines an offset into the context for use in assembly. */
     512#define L6_OFFSET    0x28
     513/** This macro defines an offset into the context for use in assembly. */
     514#define L7_OFFSET    0x2C
     515
     516/** This macro defines an offset into the context for use in assembly. */
     517#define I0_OFFSET    0x30
     518/** This macro defines an offset into the context for use in assembly. */
     519#define I1_OFFSET    0x34
     520/** This macro defines an offset into the context for use in assembly. */
     521#define I2_OFFSET    0x38
     522/** This macro defines an offset into the context for use in assembly. */
     523#define I3_OFFSET    0x3C
     524/** This macro defines an offset into the context for use in assembly. */
     525#define I4_OFFSET    0x40
     526/** This macro defines an offset into the context for use in assembly. */
     527#define I5_OFFSET    0x44
     528/** This macro defines an offset into the context for use in assembly. */
     529#define I6_FP_OFFSET 0x48
     530/** This macro defines an offset into the context for use in assembly. */
     531#define I7_OFFSET    0x4C
     532
     533/** This macro defines an offset into the context for use in assembly. */
     534#define O6_SP_OFFSET 0x50
     535/** This macro defines an offset into the context for use in assembly. */
     536#define O7_OFFSET    0x54
     537
     538/** This macro defines an offset into the context for use in assembly. */
     539#define PSR_OFFSET   0x58
     540/** This macro defines an offset into the context for use in assembly. */
     541#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x5C
    546542
    547543/** This defines the size of the context area for use in assembly. */
  • doc/cpu_supplement/sparc.t

    re5120a5 rb2ec2d15  
    398398@end ifset
    399399
     400The registers g2 through g4 are reserved for applications.  GCC uses them as
     401volatile registers by default.  So they are treated like volatile registers in
     402RTEMS as well.
    400403
    401404@subsubsection Floating Point Registers
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