Index: c/src/lib/libcpu/arm/ChangeLog
===================================================================
--- c/src/lib/libcpu/arm/ChangeLog	(revision 368c27c700a0cd72f34652aa6c0f06b13d461714)
+++ c/src/lib/libcpu/arm/ChangeLog	(revision b2a4e861dc031f45a2bc74dc1ed1279e5942d057)
@@ -1,2 +1,8 @@
+2005-06-01	Philippe Simons <loki_666@fastmail.fm>
+
+	* Makefile.am: Add s3c2400/lcd/lcd.c, s3c2400/clock/support.c
+	* s3c2400/clock/clockdrv.c: Update to use get_PCLK()
+	* s3c2400/timer/timer.c: Update to use get_PCLK()
+
 2005-05-17      Jennifer Averett <jennifer.averett@oarcorp.com>
 
Index: c/src/lib/libcpu/arm/Makefile.am
===================================================================
--- c/src/lib/libcpu/arm/Makefile.am	(revision 368c27c700a0cd72f34652aa6c0f06b13d461714)
+++ c/src/lib/libcpu/arm/Makefile.am	(revision b2a4e861dc031f45a2bc74dc1ed1279e5942d057)
@@ -97,5 +97,5 @@
 ## s3c2400/clock
 noinst_PROGRAMS += s3c2400/clock.rel
-s3c2400_clock_rel_SOURCES = s3c2400/clock/clockdrv.c
+s3c2400_clock_rel_SOURCES = s3c2400/clock/clockdrv.c s3c2400/clock/support.c
 s3c2400_clock_rel_CPPFLAGS = $(AM_CPPFLAGS)
 s3c2400_clock_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
@@ -106,4 +106,10 @@
 s3c2400_timer_rel_CPPFLAGS = $(AM_CPPFLAGS)
 s3c2400_timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+## s3c2400/lcd
+noinst_PROGRAMS += s3c2400/lcd.rel
+s3c2400_lcd_rel_SOURCES = s3c2400/lcd/lcd.c
+s3c2400_lcd_rel_CPPFLAGS = $(AM_CPPLAGS)
+s3c2400_lcd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
 
 ## s3c2400/interrupt
Index: c/src/lib/libcpu/arm/s3c2400/clock/clockdrv.c
===================================================================
--- c/src/lib/libcpu/arm/s3c2400/clock/clockdrv.c	(revision 368c27c700a0cd72f34652aa6c0f06b13d461714)
+++ c/src/lib/libcpu/arm/s3c2400/clock/clockdrv.c	(revision b2a4e861dc031f45a2bc74dc1ed1279e5942d057)
@@ -78,11 +78,5 @@
         cr=rTCFG1 & 0xFFF0FFFF; \
         rTCFG1=(cr | (3<<16)); \
-        /* compute MPLL freq */ \
-        m = M_MDIV + 8; \
-        p = M_PDIV + 2; \
-        s = M_SDIV; \
-        freq =(BSP_OSC_FREQ * m) / (p << s); \
-        /* PCLK = MPLL/4 */ \
-        freq = freq / 4; \
+        freq = get_PCLK(); \
         /* set TIMER4 counter, input freq=PLCK/16/16Mhz*/ \
         freq = (freq /16)/16; \
Index: c/src/lib/libcpu/arm/s3c2400/clock/support.c
===================================================================
--- c/src/lib/libcpu/arm/s3c2400/clock/support.c	(revision b2a4e861dc031f45a2bc74dc1ed1279e5942d057)
+++ c/src/lib/libcpu/arm/s3c2400/clock/support.c	(revision b2a4e861dc031f45a2bc74dc1ed1279e5942d057)
@@ -0,0 +1,59 @@
+#include <rtems.h>
+#include <bsp.h>
+#include <s3c2400.h>
+
+#define MPLL 0
+#define UPLL 1
+
+/* ------------------------------------------------------------------------- */
+/* NOTE: This describes the proper use of this file.
+ *
+ * BSP_OSC_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+/* ------------------------------------------------------------------------- */
+
+static uint32_t get_PLLCLK(int pllreg)
+{
+    uint32_t r, m, p, s;
+
+    if (pllreg == MPLL)
+	r = rMPLLCON;
+    else if (pllreg == UPLL)
+	r = rUPLLCON;
+    else
+	return 0;
+
+    m = ((r & 0xFF000) >> 12) + 8;
+    p = ((r & 0x003F0) >> 4) + 2;
+    s = r & 0x3;
+
+    return((BSP_OSC_FREQ * m) / (p << s));
+}
+
+/* return FCLK frequency */
+uint32_t get_FCLK(void)
+{
+    return(get_PLLCLK(MPLL));
+}
+
+/* return HCLK frequency */
+uint32_t get_HCLK(void)
+{
+    return((rCLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
+}
+
+/* return PCLK frequency */
+uint32_t get_PCLK(void)
+{
+    return((rCLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
+}
+
+/* return UCLK frequency */
+uint32_t get_UCLK(void)
+{
+    return(get_PLLCLK(UPLL));
+}
+
Index: c/src/lib/libcpu/arm/s3c2400/include/s3c2400.h
===================================================================
--- c/src/lib/libcpu/arm/s3c2400/include/s3c2400.h	(revision 368c27c700a0cd72f34652aa6c0f06b13d461714)
+++ c/src/lib/libcpu/arm/s3c2400/include/s3c2400.h	(revision b2a4e861dc031f45a2bc74dc1ed1279e5942d057)
@@ -6,6 +6,6 @@
  ************************************************/
 
-#ifndef __S3C2400_H__
-#define __S3C2400_H__
+#ifndef S3C2400_H_
+#define S3C2400_H_
 
 /* Memory control */
@@ -96,5 +96,5 @@
 #define rDITHMODE       (*(volatile unsigned *)0x14A0004C)
 #define rTPAL           (*(volatile unsigned *)0x14A00050)
-#define GP32_PALETTE            (*(volatile unsigned *)0x14A00400)      /* SJS */
+#define GP32_PALETTE    (*(volatile unsigned *)0x14A00400)      /* SJS */
 
 
@@ -427,7 +427,181 @@
                  }
 /* Wait until rINTPND is changed for the case that the ISR is very short. */
+
+//////////////////////////////////////////////////////////////////////////////
+// Typedefs                                                                 //
+//////////////////////////////////////////////////////////////////////////////
+typedef union {
+	struct _reg {
+		unsigned STOP_BIT:1;	// Enters STOP mode. This bit isn't be cleared automatically.
+		unsigned SL_IDLE:1;		// SL_IDLE mode option. This bit isn't be cleared automatically. To enter SL_IDLE mode, CLKCON register has to be 0xe.
+		unsigned IDLE_BIT:1;	// Enters IDLE mode. This bit isn't be cleared automatically.
+		unsigned LCDC:1;		// Controls HCLK into LCDC block
+		unsigned USB_host:1;	// Controls HCLK into USB host block
+		unsigned USB_device:1;	// Controls PCLK into USB device block
+		unsigned PWMTIMER:1;	// Controls PCLK into PWMTIMER block
+		unsigned MMC:1;			// Controls PCLK into MMC interface block
+		unsigned UART0:1;		// Controls PCLK into UART0 block
+		unsigned UART1:1;		// Controls PCLK into UART1 block
+		unsigned GPIO:1;		// Controls PCLK into GPIO block
+		unsigned RTC:1;			// Controls PCLK into RTC control block. Even if this bit is cleared to 0, RTC timer is alive.
+		unsigned ADC:1;			// Controls PCLK into ADC block
+		unsigned IIC:1;			// Controls PCLK into IIC block
+		unsigned IIS:1;			// Controls PCLK into IIS block
+		unsigned SPI:1;			// Controls PCLK into SPI block
+	} reg;
+	unsigned long all;
+} CLKCON;
+
+typedef union
+{
+	struct {
+		unsigned ENVID:1;		// LCD video output and the logic 1=enable/0=disable.
+		unsigned BPPMODE:4;		// 1011 = 8 bpp for TFT, 1100 = 16 bpp for TFT, 1110 = 16 bpp TFT skipmode
+		unsigned PNRMODE:2;		// TFT: 3
+		unsigned MMODE:1;		// This bit determines the toggle rate of the VM. 0 = Each Frame, 1 = The rate defined by the MVAL
+		unsigned CLKVAL:10;		// TFT: VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL >= 1)
+		unsigned LINECNT:10;	// (read only) These bits provide the status of the line counter. Down count from LINEVAL to 0
+	} reg;
+	unsigned long all;
+} LCDCON1;
+
+typedef union { 
+	struct {
+		unsigned VSPW:6;		// TFT: Vertical sync pulse width determines the VSYNC pulse's high level width by counting the number of inactive lines.
+		unsigned VFPD:8;		// TFT: Vertical front porch is the number of inactive lines at the end of a frame, before vertical synchronization period.
+		unsigned LINEVAL:10;	// TFT/STN: These bits determine the vertical size of LCD panel.
+		unsigned VBPD:8;		// TFT: Vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period.
+	} reg;
+	unsigned long all;
+} LCDCON2;
+
+typedef union {
+	struct {
+		unsigned HFPD:8;		// TFT: Horizontal front porch is the number of VCLK periods between the end of active data and the rising edge of HSYNC.
+		unsigned HOZVAL:11;		// TFT/STN: These bits determine the horizontal size of LCD panel. 2n bytes.
+		unsigned HBPD:7;		// TFT: Horizontal back porch is the number of VCLK periods between the falling edge of HSYNC and the start of active data.
+	} reg;
+	unsigned long all;
+} LCDCON3;
+
+typedef union {
+	struct {
+		unsigned HSPW:8;		// TFT: Horizontal sync pulse width determines the HSYNC pulse's high level width by counting the number of the VCLK.
+		unsigned MVAL:8;		// STN:
+		unsigned ADDVAL:8;		// TFT: Palette Index offset value
+		unsigned PALADDEN:1;	// TFT: Palette Index offset enable. 0 = Disable 1 = Enable
+	} reg;
+	unsigned long all;
+} LCDCON4;
+
+typedef union {
+	struct {
+		unsigned HWSWP:1;		// STN/TFT: Half-Word swap control bit. 0 = Swap Disable 1 = Swap Enable
+		unsigned BSWP:1;		// STN/TFT: Byte swap control bit. 0 = Swap Disable 1 = Swap Enable
+		unsigned ENLEND:1;		// TFT: LEND output signal enable/disable. 0 = Disable LEND signal. 1 = Enable LEND signal
+		unsigned RESERVED1:1;
+		unsigned INVENDLINE:1;	// TFT: This bit indicates the LEND signal polarity. 0 = normal 1 = inverted
+		unsigned RESERVED2:1;
+		unsigned INVVDEN:1;		// TFT: This bit indicates the VDEN signal polarity. 0 = normal 1 = inverted
+		unsigned INVVD:1;		// STN/TFT: This bit indicates the VD (video data) pulse polarity. 0 = Normal. 1 = VD is inverted.
+		unsigned INVVFRAME:1;	// STN/TFT: This bit indicates the VFRAME/VSYNC pulse polarity. 0 = normal 1 = inverted
+		unsigned INVVLINE:1;	// STN/TFT: This bit indicates the VLINE/HSYNC pulse polarity. 0 = normal 1 = inverted
+		unsigned INVVCLK:1;		// STN/TFT: This bit controls the polarity of the VCLK active edge. 0 = The video data is fetched at VCLK falling edge. 1 = The video data is fetched at VCLK rising edge
+		unsigned RESERVED3:2;
+		unsigned SELFREF:1;		// STN:
+		unsigned SLOWCLKSYNC:1;	// STN:
+		unsigned RESERVED4:2;	// must be 0
+		unsigned HSTATUS:2;		// TFT: Horizontal Status (Read only) 00 = HSYNC 01 = BACK Porch. 10 = ACTIVE 11 = FRONT Porch
+		unsigned VSTATUS:2;		// TFT: Vertical Status (Read only). 00 = VSYNC 01 = BACK Porch. 10 = ACTIVE 11 = FRONT Porch
+	} reg;
+	unsigned long all;
+} LCDCON5;
+
+typedef union {
+	struct {
+		unsigned LCDBASEU:21;	// For single-scan LCD: These bits indicate A[21:1] of the start address of the LCD frame buffer.
+		unsigned LCDBANK:7;		// A[28:22]
+	} reg;
+	unsigned long all;
+} LCDSADDR1;
+
+typedef union {
+	struct {
+		unsigned LCDBASEL:21;	// For single scan LCD: These bits indicate A[21:1] of the end address of the LCD frame buffer. LCDBASEL = ((the fame end address) >>1) + 1 = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1)
+	} reg;
+	unsigned long all;
+} LCDSADDR2;
+
+typedef union {
+	struct {
+		unsigned PAGEWIDTH:11;	// Virtual screen page width(the number of half words) This value defines the width of the view port in the frame
+		unsigned OFFSIZE:11;	// Virtual screen offset size(the number of half words) This value defines the difference between the address of the last half word displayed on the previous LCD line and the address of the first half word to be displayed in the new LCD line.
+	} reg;
+	unsigned long all;
+} LCDSADDR3;
+
+//
+//
+//
+
+typedef union {
+	struct {
+		unsigned IISIFENA:1;	// IIS interface enable (start)
+		unsigned IISPSENA:1;	// IIS prescaler enable
+		unsigned RXCHIDLE:1;	// Receive channel idle command
+		unsigned TXCHIDLE:1;	// Transmit channel idle command
+		unsigned RXDMAENA:1;	// Receive DMA service request enable
+		unsigned TXDMAENA:1;	// Transmit DMA service request enable
+		unsigned RXFIFORDY:1;	// Receive FIFO ready flag (read only)
+		unsigned TXFIFORDY:1;	// Transmit FIFO ready flag (read only)
+		unsigned LRINDEX:1;		// Left/right channel index (read only)
+	} reg;
+	unsigned long all;
+} IISCON;
+
+typedef union {
+	struct {
+		unsigned SBCLKFS:2;		// Serial bit clock frequency select
+		unsigned MCLKFS:1;		// Master clock frequency select
+		unsigned SDBITS:1;		// Serial data bit per channel
+		unsigned SIFMT:1;		// Serial interface format
+		unsigned ACTLEVCH:1;	// Active level pf left/right channel
+		unsigned TXRXMODE:2;	// Transmit/receive mode select
+		unsigned MODE:1;		// Master/slave mode select
+	} reg;
+	unsigned long all;
+} IISMOD;
+
+typedef union {
+	struct {
+		unsigned PSB:5;			// Prescaler control B
+		unsigned PSA:5;			// Prescaler control A
+	} reg;
+	unsigned long all;
+} IISPSR;
+
+typedef union {
+	struct {
+		unsigned RXFIFOCNT:4;	// (read only)
+		unsigned TXFIFOCNT:4;	// (read only)
+		unsigned RXFIFOENA:1;	//
+		unsigned TXFIFOENA:1;	//
+		unsigned RXFIFOMODE:1;	//
+		unsigned TXFIFOMODE:1;	//
+	} reg;
+	unsigned long all;
+} IISSFIFCON;
+
+typedef union {
+	struct {
+		unsigned FENTRY:16;		//
+	} reg;
+	unsigned long all;
+} IISSFIF;
+
+
 #define LCD_WIDTH 240
-#define LCD_HEIGH 320
-#define LCD_ASPECT ((flaot)(LCD_WIDTH/LCD_HEIGHT))
+#define LCD_HEIGHT 320
+#define LCD_ASPECT ((float)(LCD_WIDTH/LCD_HEIGHT))
 
 #define GP32_KEY_SELECT 512
@@ -442,3 +616,3 @@
 #define GP32_KEY_RIGHT 4
 
-#endif /*__S3C2400_H__*/
+#endif /*S3C2400_H_*/
Index: c/src/lib/libcpu/arm/s3c2400/lcd/lcd.c
===================================================================
--- c/src/lib/libcpu/arm/s3c2400/lcd/lcd.c	(revision b2a4e861dc031f45a2bc74dc1ed1279e5942d057)
+++ c/src/lib/libcpu/arm/s3c2400/lcd/lcd.c	(revision b2a4e861dc031f45a2bc74dc1ed1279e5942d057)
@@ -0,0 +1,156 @@
+#include <rtems.h>
+#include <bsp.h>
+#include <s3c2400.h>
+
+void gp32_setFramebuffer(void *add) {
+   uint32_t addr = (uint32_t) add;
+   uint32_t LCDBANK  =  addr >> 22;
+   uint32_t LCDBASEU = (addr & 0x3FFFFF) >> 1;
+   uint32_t LCDBASEL;
+   uint16_t OFFSIZE = 0;
+   uint16_t PAGEWIDTH;
+   uint16_t vidmode = ((rLCDCON1>>1) & 15)-8;
+   const uint8_t faktor[]= {15,30,60,120,240};
+
+   LCDBASEL  = LCDBASEU + 320*faktor[vidmode];
+   PAGEWIDTH = faktor[vidmode];
+
+   rLCDSADDR1 = (LCDBANK<<21) | (LCDBASEU<<0) ;
+   rLCDSADDR2 = (LCDBASEL<<0) ;
+   rLCDSADDR3 = (OFFSIZE<<11) | (PAGEWIDTH<<0) ;
+}
+
+short gp32_initFramebufferN(void *add,uint32_t bitmode,uint32_t refreshrate) {
+   uint32_t addr = (uint32_t) add;
+   uint32_t GPHCLK = get_HCLK();
+   {  uint16_t BPPMODE = 12;     
+      uint16_t CLKVAL = 3;       
+      uint16_t ENVID = 1;
+      uint16_t MMODE = 0;
+      uint16_t PNRMODE = 3;
+      switch (bitmode) {
+         case 16 : BPPMODE=12; break;
+         case  8 : BPPMODE=11; break;
+         case  4 : BPPMODE=10; break;
+         case  2 : BPPMODE= 9; break;
+         case  1 : BPPMODE= 8; break;
+	 default : BPPMODE= 12; break;
+      }
+      /* Get the correct CLKVAL for refreshrate
+         works in all bitmodes now :)
+      */
+      if (refreshrate <  50) refreshrate = 50;
+      if (refreshrate > 120) refreshrate =120;
+      CLKVAL = (GPHCLK/(83385*2*refreshrate))-1;
+      if (CLKVAL == 0) CLKVAL=1;
+      refreshrate = GPHCLK / (83385*2*(CLKVAL+1));
+      rLCDCON1 = (CLKVAL<<8) | (MMODE<<7) | (PNRMODE<<5) | (BPPMODE<<1) | (ENVID<<0) ;
+   }
+   {  uint16_t LINEVAL = 320-1;
+      uint16_t VBPD = 1;
+      uint16_t VFPD = 2;
+      uint16_t VSPW = 1;
+      rLCDCON2 = 0;
+      rLCDCON2 = (VBPD<<24) | (LINEVAL<<14) | (VFPD<<6) | (VSPW<<0) ;
+   }
+   {  uint16_t HBPD = 6;
+      uint16_t HFPD = 2;
+      uint16_t HOZVAL = 240-1;
+      rLCDCON3 = 0;
+      rLCDCON3 = (HBPD<<19) | (HOZVAL<<8) | (HFPD<<0) ;
+   }
+   {  uint16_t ADDVAL = 0;
+      uint16_t HSPW = 4;
+      uint16_t MVAL = 0;
+      uint16_t PALADDEN = 0;
+      rLCDCON4 = 0;
+      rLCDCON4 = (PALADDEN<<24) | (ADDVAL<<16) | (MVAL<<8) | (HSPW<<0) ;
+   }
+   {  uint16_t BSWP = 0;
+      uint16_t ENLEND = 0;
+      uint16_t HWSWP = 1;
+      uint16_t INVENDLINE = 0;
+      uint16_t INVVCLK = 1;
+      uint16_t INVVD = 0;
+      uint16_t INVVDEN = 0;
+      uint16_t INVVFRAME = 1;
+      uint16_t INVVLINE = 1;
+      if (bitmode<16) { BSWP=1;HWSWP=0; }
+      rLCDCON5 = 0;
+      rLCDCON5 = (INVVCLK<<10) | (INVVLINE<<9) | (INVVFRAME<<8) | (INVVD<<7) | (INVVDEN<<6)
+               | (INVENDLINE<<4) | (ENLEND<<2) | (BSWP<<1) | (HWSWP<<0) ;
+   }
+   gp32_setFramebuffer((uint32_t*)addr);
+
+return refreshrate;
+}
+
+short gp32_initFramebufferBP(void *add,uint32_t bitmode,uint32_t refreshrate) {
+  uint32_t addr = (uint32_t) add;
+  uint32_t GPHCLK = get_HCLK();
+  {  uint16_t BPPMODE = 12;     
+     uint16_t CLKVAL = 3;       
+     uint16_t ENVID = 1;
+     uint16_t MMODE = 0;
+     uint16_t PNRMODE = 3;
+     switch (bitmode) {
+        case 16 : BPPMODE=12; break;
+        case  8 : BPPMODE=11; break;
+        case  4 : BPPMODE=10; break;
+        case  2 : BPPMODE= 9; break;
+        case  1 : BPPMODE= 8; break;
+     }
+     /* Get the correct CLKVAL for refreshrate
+        works in all bitmodes now :)
+     */
+     if (refreshrate <  50) refreshrate = 50;
+     if (refreshrate > 120) refreshrate =120;
+     CLKVAL = (GPHCLK/(109850*2*refreshrate))-1;
+     if (CLKVAL == 0) CLKVAL=1;
+     refreshrate = GPHCLK / (109850*2*(CLKVAL+1));
+     rLCDCON1 = (CLKVAL<<8) | (MMODE<<7) | (PNRMODE<<5) | (BPPMODE<<1) | (ENVID<<0);
+  }
+  {  uint16_t LINEVAL = 320-1;
+     uint16_t VBPD = 8;
+     uint16_t VFPD = 2;
+     uint16_t VSPW = 5;
+     rLCDCON2 = 0;
+     rLCDCON2 = (VBPD<<24) | (LINEVAL<<14) | (VFPD<<6) | (VSPW<<0);
+  }
+  {  uint16_t HBPD = 50;
+     uint16_t HFPD = 2;
+     uint16_t HOZVAL = 240-1;
+     rLCDCON3 = 0;
+     rLCDCON3 = (HBPD<<19) | (HOZVAL<<8) | (HFPD<<0);
+  }
+  {  uint16_t ADDVAL = 0;
+     uint16_t HSPW = 30;
+     uint16_t MVAL = 0;
+     uint16_t PALADDEN = 0;
+     rLCDCON4 = 0;
+     rLCDCON4 = (PALADDEN<<24) | (ADDVAL<<16) | (MVAL<<8) | (HSPW<<0);
+  }
+  {  uint16_t BSWP = 0;
+     uint16_t ENLEND = 0;
+     uint16_t HWSWP = 1;
+     uint16_t INVENDLINE = 0;
+     uint16_t INVVCLK = 1;
+     uint16_t INVVD = 0;
+     uint16_t INVVDEN = 0;
+     uint16_t INVVFRAME = 1;
+     uint16_t INVVLINE = 1;
+     if (bitmode<16) { BSWP=1;HWSWP=0; }
+     rLCDCON5 = 0;
+     rLCDCON5 = (INVVCLK<<10) | (INVVLINE<<9) | (INVVFRAME<<8) | (INVVD<<7) | (INVVDEN<<6)
+              | (INVENDLINE<<4) | (ENLEND<<2) | (BSWP<<1) | (HWSWP<<0);
+  }
+  gp32_setFramebuffer((uint32_t*)addr);
+
+return refreshrate;
+}
+
+void gp32_setPalette( unsigned char pos, uint16_t color) {
+	unsigned long *palette=(unsigned long *)0x14A00400;
+	while ((rLCDCON5>>19) == 2);
+	palette[pos]=color;
+}
Index: c/src/lib/libcpu/arm/s3c2400/timer/timer.c
===================================================================
--- c/src/lib/libcpu/arm/s3c2400/timer/timer.c	(revision 368c27c700a0cd72f34652aa6c0f06b13d461714)
+++ c/src/lib/libcpu/arm/s3c2400/timer/timer.c	(revision b2a4e861dc031f45a2bc74dc1ed1279e5942d057)
@@ -37,7 +37,4 @@
 {
     uint32_t cr;
-    uint32_t m;
-    uint32_t p;
-    uint32_t s;
 
     /* stop TIMER1*/ 
@@ -49,15 +46,6 @@
     rTCFG1=(cr | (0<<4));
 
-    /* compute MPLL freq */
-    m = M_MDIV + 8;
-    p = M_PDIV + 2;
-    s = M_SDIV;
-    g_freq =(BSP_OSC_FREQ * m) / (p << s);
-
-    /* PCLK = MPLL/4 */ 
-    g_freq = g_freq / 4; 
-
     /* input freq=PLCK/2 Mhz*/ 
-    g_freq = g_freq / 2000; 
+    g_freq = get_PCLK() / 2000; 
     rTCNTB1 = 0xFFFF;
 
