Changeset b2a4e861 in rtems
- Timestamp:
- 06/02/05 13:45:53 (17 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 00ed1c9
- Parents:
- 32cf23b1
- Location:
- c/src/lib/libcpu/arm
- Files:
-
- 2 added
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libcpu/arm/ChangeLog
r32cf23b1 rb2a4e861 1 2005-06-01 Philippe Simons <loki_666@fastmail.fm> 2 3 * Makefile.am: Add s3c2400/lcd/lcd.c, s3c2400/clock/support.c 4 * s3c2400/clock/clockdrv.c: Update to use get_PCLK() 5 * s3c2400/timer/timer.c: Update to use get_PCLK() 6 1 7 2005-05-17 Jennifer Averett <jennifer.averett@oarcorp.com> 2 8 -
c/src/lib/libcpu/arm/Makefile.am
r32cf23b1 rb2a4e861 97 97 ## s3c2400/clock 98 98 noinst_PROGRAMS += s3c2400/clock.rel 99 s3c2400_clock_rel_SOURCES = s3c2400/clock/clockdrv.c 99 s3c2400_clock_rel_SOURCES = s3c2400/clock/clockdrv.c s3c2400/clock/support.c 100 100 s3c2400_clock_rel_CPPFLAGS = $(AM_CPPFLAGS) 101 101 s3c2400_clock_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) … … 106 106 s3c2400_timer_rel_CPPFLAGS = $(AM_CPPFLAGS) 107 107 s3c2400_timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) 108 109 ## s3c2400/lcd 110 noinst_PROGRAMS += s3c2400/lcd.rel 111 s3c2400_lcd_rel_SOURCES = s3c2400/lcd/lcd.c 112 s3c2400_lcd_rel_CPPFLAGS = $(AM_CPPLAGS) 113 s3c2400_lcd_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) 108 114 109 115 ## s3c2400/interrupt -
c/src/lib/libcpu/arm/s3c2400/clock/clockdrv.c
r32cf23b1 rb2a4e861 78 78 cr=rTCFG1 & 0xFFF0FFFF; \ 79 79 rTCFG1=(cr | (3<<16)); \ 80 /* compute MPLL freq */ \ 81 m = M_MDIV + 8; \ 82 p = M_PDIV + 2; \ 83 s = M_SDIV; \ 84 freq =(BSP_OSC_FREQ * m) / (p << s); \ 85 /* PCLK = MPLL/4 */ \ 86 freq = freq / 4; \ 80 freq = get_PCLK(); \ 87 81 /* set TIMER4 counter, input freq=PLCK/16/16Mhz*/ \ 88 82 freq = (freq /16)/16; \ -
c/src/lib/libcpu/arm/s3c2400/include/s3c2400.h
r32cf23b1 rb2a4e861 6 6 ************************************************/ 7 7 8 #ifndef __S3C2400_H__9 #define __S3C2400_H__8 #ifndef S3C2400_H_ 9 #define S3C2400_H_ 10 10 11 11 /* Memory control */ … … 96 96 #define rDITHMODE (*(volatile unsigned *)0x14A0004C) 97 97 #define rTPAL (*(volatile unsigned *)0x14A00050) 98 #define GP32_PALETTE 98 #define GP32_PALETTE (*(volatile unsigned *)0x14A00400) /* SJS */ 99 99 100 100 … … 427 427 } 428 428 /* Wait until rINTPND is changed for the case that the ISR is very short. */ 429 430 ////////////////////////////////////////////////////////////////////////////// 431 // Typedefs // 432 ////////////////////////////////////////////////////////////////////////////// 433 typedef union { 434 struct _reg { 435 unsigned STOP_BIT:1; // Enters STOP mode. This bit isn't be cleared automatically. 436 unsigned SL_IDLE:1; // SL_IDLE mode option. This bit isn't be cleared automatically. To enter SL_IDLE mode, CLKCON register has to be 0xe. 437 unsigned IDLE_BIT:1; // Enters IDLE mode. This bit isn't be cleared automatically. 438 unsigned LCDC:1; // Controls HCLK into LCDC block 439 unsigned USB_host:1; // Controls HCLK into USB host block 440 unsigned USB_device:1; // Controls PCLK into USB device block 441 unsigned PWMTIMER:1; // Controls PCLK into PWMTIMER block 442 unsigned MMC:1; // Controls PCLK into MMC interface block 443 unsigned UART0:1; // Controls PCLK into UART0 block 444 unsigned UART1:1; // Controls PCLK into UART1 block 445 unsigned GPIO:1; // Controls PCLK into GPIO block 446 unsigned RTC:1; // Controls PCLK into RTC control block. Even if this bit is cleared to 0, RTC timer is alive. 447 unsigned ADC:1; // Controls PCLK into ADC block 448 unsigned IIC:1; // Controls PCLK into IIC block 449 unsigned IIS:1; // Controls PCLK into IIS block 450 unsigned SPI:1; // Controls PCLK into SPI block 451 } reg; 452 unsigned long all; 453 } CLKCON; 454 455 typedef union 456 { 457 struct { 458 unsigned ENVID:1; // LCD video output and the logic 1=enable/0=disable. 459 unsigned BPPMODE:4; // 1011 = 8 bpp for TFT, 1100 = 16 bpp for TFT, 1110 = 16 bpp TFT skipmode 460 unsigned PNRMODE:2; // TFT: 3 461 unsigned MMODE:1; // This bit determines the toggle rate of the VM. 0 = Each Frame, 1 = The rate defined by the MVAL 462 unsigned CLKVAL:10; // TFT: VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL >= 1) 463 unsigned LINECNT:10; // (read only) These bits provide the status of the line counter. Down count from LINEVAL to 0 464 } reg; 465 unsigned long all; 466 } LCDCON1; 467 468 typedef union { 469 struct { 470 unsigned VSPW:6; // TFT: Vertical sync pulse width determines the VSYNC pulse's high level width by counting the number of inactive lines. 471 unsigned VFPD:8; // TFT: Vertical front porch is the number of inactive lines at the end of a frame, before vertical synchronization period. 472 unsigned LINEVAL:10; // TFT/STN: These bits determine the vertical size of LCD panel. 473 unsigned VBPD:8; // TFT: Vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period. 474 } reg; 475 unsigned long all; 476 } LCDCON2; 477 478 typedef union { 479 struct { 480 unsigned HFPD:8; // TFT: Horizontal front porch is the number of VCLK periods between the end of active data and the rising edge of HSYNC. 481 unsigned HOZVAL:11; // TFT/STN: These bits determine the horizontal size of LCD panel. 2n bytes. 482 unsigned HBPD:7; // TFT: Horizontal back porch is the number of VCLK periods between the falling edge of HSYNC and the start of active data. 483 } reg; 484 unsigned long all; 485 } LCDCON3; 486 487 typedef union { 488 struct { 489 unsigned HSPW:8; // TFT: Horizontal sync pulse width determines the HSYNC pulse's high level width by counting the number of the VCLK. 490 unsigned MVAL:8; // STN: 491 unsigned ADDVAL:8; // TFT: Palette Index offset value 492 unsigned PALADDEN:1; // TFT: Palette Index offset enable. 0 = Disable 1 = Enable 493 } reg; 494 unsigned long all; 495 } LCDCON4; 496 497 typedef union { 498 struct { 499 unsigned HWSWP:1; // STN/TFT: Half-Word swap control bit. 0 = Swap Disable 1 = Swap Enable 500 unsigned BSWP:1; // STN/TFT: Byte swap control bit. 0 = Swap Disable 1 = Swap Enable 501 unsigned ENLEND:1; // TFT: LEND output signal enable/disable. 0 = Disable LEND signal. 1 = Enable LEND signal 502 unsigned RESERVED1:1; 503 unsigned INVENDLINE:1; // TFT: This bit indicates the LEND signal polarity. 0 = normal 1 = inverted 504 unsigned RESERVED2:1; 505 unsigned INVVDEN:1; // TFT: This bit indicates the VDEN signal polarity. 0 = normal 1 = inverted 506 unsigned INVVD:1; // STN/TFT: This bit indicates the VD (video data) pulse polarity. 0 = Normal. 1 = VD is inverted. 507 unsigned INVVFRAME:1; // STN/TFT: This bit indicates the VFRAME/VSYNC pulse polarity. 0 = normal 1 = inverted 508 unsigned INVVLINE:1; // STN/TFT: This bit indicates the VLINE/HSYNC pulse polarity. 0 = normal 1 = inverted 509 unsigned INVVCLK:1; // STN/TFT: This bit controls the polarity of the VCLK active edge. 0 = The video data is fetched at VCLK falling edge. 1 = The video data is fetched at VCLK rising edge 510 unsigned RESERVED3:2; 511 unsigned SELFREF:1; // STN: 512 unsigned SLOWCLKSYNC:1; // STN: 513 unsigned RESERVED4:2; // must be 0 514 unsigned HSTATUS:2; // TFT: Horizontal Status (Read only) 00 = HSYNC 01 = BACK Porch. 10 = ACTIVE 11 = FRONT Porch 515 unsigned VSTATUS:2; // TFT: Vertical Status (Read only). 00 = VSYNC 01 = BACK Porch. 10 = ACTIVE 11 = FRONT Porch 516 } reg; 517 unsigned long all; 518 } LCDCON5; 519 520 typedef union { 521 struct { 522 unsigned LCDBASEU:21; // For single-scan LCD: These bits indicate A[21:1] of the start address of the LCD frame buffer. 523 unsigned LCDBANK:7; // A[28:22] 524 } reg; 525 unsigned long all; 526 } LCDSADDR1; 527 528 typedef union { 529 struct { 530 unsigned LCDBASEL:21; // For single scan LCD: These bits indicate A[21:1] of the end address of the LCD frame buffer. LCDBASEL = ((the fame end address) >>1) + 1 = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1) 531 } reg; 532 unsigned long all; 533 } LCDSADDR2; 534 535 typedef union { 536 struct { 537 unsigned PAGEWIDTH:11; // Virtual screen page width(the number of half words) This value defines the width of the view port in the frame 538 unsigned OFFSIZE:11; // Virtual screen offset size(the number of half words) This value defines the difference between the address of the last half word displayed on the previous LCD line and the address of the first half word to be displayed in the new LCD line. 539 } reg; 540 unsigned long all; 541 } LCDSADDR3; 542 543 // 544 // 545 // 546 547 typedef union { 548 struct { 549 unsigned IISIFENA:1; // IIS interface enable (start) 550 unsigned IISPSENA:1; // IIS prescaler enable 551 unsigned RXCHIDLE:1; // Receive channel idle command 552 unsigned TXCHIDLE:1; // Transmit channel idle command 553 unsigned RXDMAENA:1; // Receive DMA service request enable 554 unsigned TXDMAENA:1; // Transmit DMA service request enable 555 unsigned RXFIFORDY:1; // Receive FIFO ready flag (read only) 556 unsigned TXFIFORDY:1; // Transmit FIFO ready flag (read only) 557 unsigned LRINDEX:1; // Left/right channel index (read only) 558 } reg; 559 unsigned long all; 560 } IISCON; 561 562 typedef union { 563 struct { 564 unsigned SBCLKFS:2; // Serial bit clock frequency select 565 unsigned MCLKFS:1; // Master clock frequency select 566 unsigned SDBITS:1; // Serial data bit per channel 567 unsigned SIFMT:1; // Serial interface format 568 unsigned ACTLEVCH:1; // Active level pf left/right channel 569 unsigned TXRXMODE:2; // Transmit/receive mode select 570 unsigned MODE:1; // Master/slave mode select 571 } reg; 572 unsigned long all; 573 } IISMOD; 574 575 typedef union { 576 struct { 577 unsigned PSB:5; // Prescaler control B 578 unsigned PSA:5; // Prescaler control A 579 } reg; 580 unsigned long all; 581 } IISPSR; 582 583 typedef union { 584 struct { 585 unsigned RXFIFOCNT:4; // (read only) 586 unsigned TXFIFOCNT:4; // (read only) 587 unsigned RXFIFOENA:1; // 588 unsigned TXFIFOENA:1; // 589 unsigned RXFIFOMODE:1; // 590 unsigned TXFIFOMODE:1; // 591 } reg; 592 unsigned long all; 593 } IISSFIFCON; 594 595 typedef union { 596 struct { 597 unsigned FENTRY:16; // 598 } reg; 599 unsigned long all; 600 } IISSFIF; 601 602 429 603 #define LCD_WIDTH 240 430 #define LCD_HEIGH 320431 #define LCD_ASPECT ((fl aot)(LCD_WIDTH/LCD_HEIGHT))604 #define LCD_HEIGHT 320 605 #define LCD_ASPECT ((float)(LCD_WIDTH/LCD_HEIGHT)) 432 606 433 607 #define GP32_KEY_SELECT 512 … … 442 616 #define GP32_KEY_RIGHT 4 443 617 444 #endif /* __S3C2400_H__*/618 #endif /*S3C2400_H_*/ -
c/src/lib/libcpu/arm/s3c2400/timer/timer.c
r32cf23b1 rb2a4e861 37 37 { 38 38 uint32_t cr; 39 uint32_t m;40 uint32_t p;41 uint32_t s;42 39 43 40 /* stop TIMER1*/ … … 49 46 rTCFG1=(cr | (0<<4)); 50 47 51 /* compute MPLL freq */52 m = M_MDIV + 8;53 p = M_PDIV + 2;54 s = M_SDIV;55 g_freq =(BSP_OSC_FREQ * m) / (p << s);56 57 /* PCLK = MPLL/4 */58 g_freq = g_freq / 4;59 60 48 /* input freq=PLCK/2 Mhz*/ 61 g_freq = g _freq/ 2000;49 g_freq = get_PCLK() / 2000; 62 50 rTCNTB1 = 0xFFFF; 63 51
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