Changeset b1b5ddf0 in rtems


Ignore:
Timestamp:
May 15, 2015, 11:17:16 AM (5 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
7e19330e, e893061
Parents:
a0001d6
git-author:
Sebastian Huber <sebastian.huber@…> (05/15/15 11:17:16)
git-committer:
Sebastian Huber <sebastian.huber@…> (05/15/15 11:23:03)
Message:

smptests/smpcache01: Restructure

Restructure to avoid large maximum thread dispatch disabled times.

Location:
testsuites/smptests/smpcache01
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • testsuites/smptests/smpcache01/init.c

    ra0001d6 rb1b5ddf0  
    4242}
    4343
    44 static void test_cache_message( void *arg )
     44static void test_action( void *arg )
    4545{
    4646  rtems_test_assert(arg == &ctx);
     
    4949}
    5050
    51 static void cache_manager_smp_functions( size_t set_size,
    52     cpu_set_t *cpu_set )
     51typedef void ( *test_case )(
     52  size_t set_size,
     53  const cpu_set_t *cpu_set,
     54  SMP_barrier_State *bs
     55);
     56
     57static void test_cache_flush_multiple_data_lines(
     58  size_t set_size,
     59  const cpu_set_t *cpu_set,
     60  SMP_barrier_State *bs
     61)
    5362{
    5463  rtems_cache_flush_multiple_data_lines_processor_set( &data_to_flush,
    5564      sizeof(data_to_flush), set_size, cpu_set );
     65}
     66
     67static void test_cache_invalidate_multiple_data_lines(
     68  size_t set_size,
     69  const cpu_set_t *cpu_set,
     70  SMP_barrier_State *bs
     71)
     72{
    5673  rtems_cache_invalidate_multiple_data_lines_processor_set( &data_to_flush,
    5774      sizeof(data_to_flush), set_size, cpu_set );
     75}
     76
     77static void test_cache_flush_entire_data(
     78  size_t set_size,
     79  const cpu_set_t *cpu_set,
     80  SMP_barrier_State *bs
     81)
     82{
    5883  rtems_cache_flush_entire_data_processor_set( set_size, cpu_set );
     84}
     85
     86static void test_cache_invalidate_entire_instruction(
     87  size_t set_size,
     88  const cpu_set_t *cpu_set,
     89  SMP_barrier_State *bs
     90)
     91{
    5992  rtems_cache_invalidate_entire_instruction();
     93}
     94
     95static void test_cache_invalidate_multiple_instruction_lines(
     96  size_t set_size,
     97  const cpu_set_t *cpu_set,
     98  SMP_barrier_State *bs
     99)
     100{
    60101  rtems_cache_invalidate_multiple_instruction_lines( &function_to_flush,
    61102      4 /* arbitrary size */ );
    62103}
    63104
    64 static void standard_funcs_test( size_t set_size, cpu_set_t *cpu_set )
    65 {
    66   cache_manager_smp_functions( set_size, cpu_set );
    67 }
    68 
    69 static void standard_funcs_isrdisabled_test( size_t set_size,
    70     cpu_set_t *cpu_set, SMP_barrier_State *bs  )
    71 {
    72   ISR_Level isr_level;
    73 
    74   _ISR_Disable_without_giant( isr_level );
    75 
    76   _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() );
    77 
    78   cache_manager_smp_functions( set_size, cpu_set );
    79 
    80   _ISR_Enable_without_giant( isr_level );
    81 }
    82 
    83 static void standard_funcs_giant_taken_test( size_t set_size,
    84     cpu_set_t *cpu_set, SMP_barrier_State *bs )
    85 {
    86   if ( rtems_get_current_processor() == 0)
    87     _Thread_Disable_dispatch();
    88 
    89   _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() );
    90 
    91   cache_manager_smp_functions( set_size, cpu_set );
    92 
    93   if ( rtems_get_current_processor() == 0)
    94     _Thread_Enable_dispatch();
    95 }
    96 
    97 static void test_func_test( size_t set_size, cpu_set_t *cpu_set,
    98     SMP_barrier_State *bs )
     105static void test_broadcast_action(
     106  size_t set_size,
     107  const cpu_set_t *cpu_set,
     108  SMP_barrier_State *bs
     109)
    99110{
    100111  ctx.count[rtems_get_current_processor()] = 0;
    101112  _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() );
    102113
    103   _SMP_Multicast_action( set_size, cpu_set, test_cache_message, &ctx );
     114  _SMP_Multicast_action( set_size, cpu_set, test_action, &ctx );
    104115
    105116  _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() );
     
    109120}
    110121
    111 static void test_func_isrdisabled_test( size_t set_size, cpu_set_t *cpu_set,
    112     SMP_barrier_State *bs )
    113 {
    114   ISR_Level isr_level;
    115 
    116   ctx.count[rtems_get_current_processor()] = 0;
    117   _ISR_Disable_without_giant( isr_level );
    118 
    119   _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() );
    120 
    121   _SMP_Multicast_action( set_size, cpu_set, test_cache_message, &ctx );
    122 
    123   _ISR_Enable_without_giant( isr_level );
    124 
    125   _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() );
    126 
    127   rtems_test_assert( ctx.count[rtems_get_current_processor()] ==
    128       rtems_get_processor_count() );
    129 }
    130 
    131 static void test_func_giant_taken_test( size_t set_size, cpu_set_t *cpu_set,
    132     SMP_barrier_State *bs )
    133 {
    134   ctx.count[rtems_get_current_processor()] = 0;
    135 
    136   if ( rtems_get_current_processor() == 0)
    137     _Thread_Disable_dispatch();
    138 
    139   _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() );
    140 
    141   _SMP_Multicast_action( set_size, cpu_set, test_cache_message, &ctx );
    142 
    143   _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() );
    144 
    145   rtems_test_assert( ctx.count[rtems_get_current_processor()] ==
    146       rtems_get_processor_count() );
    147 
    148   if ( rtems_get_current_processor() == 0)
    149     _Thread_Enable_dispatch();
     122static test_case test_cases[] = {
     123  test_cache_flush_multiple_data_lines,
     124  test_cache_invalidate_multiple_data_lines,
     125  test_cache_flush_entire_data,
     126  test_cache_invalidate_entire_instruction,
     127  test_cache_invalidate_multiple_instruction_lines,
     128  test_broadcast_action
     129};
     130
     131static void call_test(
     132  size_t set_size,
     133  const cpu_set_t *cpu_set,
     134  SMP_barrier_State *bs,
     135  size_t i
     136)
     137{
     138  _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() );
     139  ( *test_cases[ i ] )( set_size, cpu_set, bs );
     140  _SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() );
     141}
     142
     143static void call_tests( size_t set_size,
     144    const cpu_set_t *cpu_set, SMP_barrier_State *bs  )
     145{
     146  size_t i;
     147
     148  for (i = 0; i < RTEMS_ARRAY_SIZE( test_cases ); ++i) {
     149    call_test( set_size, cpu_set, bs, i );
     150  }
     151}
     152
     153static void call_tests_isr_disabled( size_t set_size,
     154    const cpu_set_t *cpu_set, SMP_barrier_State *bs  )
     155{
     156  size_t i;
     157
     158  for (i = 0; i < RTEMS_ARRAY_SIZE( test_cases ); ++i) {
     159    ISR_Level isr_level;
     160
     161    _ISR_Disable_without_giant( isr_level );
     162
     163    call_test( set_size, cpu_set, bs, i );
     164
     165    _ISR_Enable_without_giant( isr_level );
     166  }
     167}
     168
     169static void call_tests_with_giant_acquired( size_t set_size,
     170    const cpu_set_t *cpu_set, SMP_barrier_State *bs )
     171{
     172  size_t i;
     173
     174  for (i = 0; i < RTEMS_ARRAY_SIZE( test_cases ); ++i) {
     175    if ( rtems_get_current_processor() == 0)
     176      _Thread_Disable_dispatch();
     177
     178    call_test( set_size, cpu_set, bs, i );
     179
     180    if ( rtems_get_current_processor() == 0)
     181      _Thread_Enable_dispatch();
     182  }
    150183}
    151184
     
    166199  CPU_FILL_S( set_size, cpu_set );
    167200
    168   /* Call SMP cache manager functions */
    169   cmlog( "Calling standard SMP cache functions. " );
    170   _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
    171   standard_funcs_test( set_size, cpu_set );
    172   _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
     201  /* Call test cases */
     202  cmlog( "Calling test cases. " );
     203  call_tests( set_size, cpu_set, &bs );
    173204  cmlog( "Done!\n");
    174205
    175   /* Call SMP cache manager functions with ISR disabled */
    176   cmlog( "Calling standard SMP cache functions with ISR disabled. " );
    177   _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
    178   standard_funcs_isrdisabled_test( set_size, cpu_set, &bs );
    179   _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
     206  /* Call test cases with ISR disabled */
     207  cmlog( "Calling test cases with ISR disabled. " );
     208  call_tests_isr_disabled( set_size, cpu_set, &bs );
    180209  cmlog( "Done!\n" );
    181210
    182   /* Call SMP cache manager functions with core 0 holding the giant lock */
    183   cmlog( "Calling standard SMP cache functions with CPU0 holding "
     211  /* Call test cases with core 0 holding the giant lock */
     212  cmlog( "Calling test cases with CPU0 holding "
    184213      "the giant lock. " );
    185   _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
    186   standard_funcs_giant_taken_test( set_size, cpu_set, &bs );
    187   _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
     214  call_tests_with_giant_acquired( set_size, cpu_set, &bs );
    188215  cmlog( "Done!\n");
    189 
    190   /* Call a test function using SMP cache manager and verify that all
    191    * cores invoke the function */
    192   cmlog( "Calling a test function using the SMP cache manager to "
    193       "verify that all CPUs receive the SMP message. " );
    194   _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
    195   test_func_test( set_size, cpu_set, &bs );
    196   _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
    197   cmlog( "Done!\n");
    198 
    199   /* Call a test function using SMP cache manager and verify that all
    200    * cores invoke the function. ISR disabled. */
    201   cmlog( "Calling a test function using the SMP cache manager to "
    202       "verify that all CPUs receive the SMP message. With ISR disabled. " );
    203   _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
    204   test_func_isrdisabled_test( set_size, cpu_set, &bs );
    205   _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
    206   cmlog( "Done!\n" );
    207 
    208   /* Call a test function using SMP cache manager and verify that all
    209    * cores invoke the function. Core 0 holding giant lock. */
    210   cmlog( "Calling a test function using the SMP cache manager to "
    211       "verify that all CPUs receive the SMP message. With CPU0 "
    212       "holding the giant lock. " );
    213   _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
    214   test_func_giant_taken_test( set_size, cpu_set, &bs );
    215   _SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
    216   cmlog( "Done!\n" );
    217216
    218217  /* Done. Free up memory. */
  • testsuites/smptests/smpcache01/smpcache01.scn

    ra0001d6 rb1b5ddf0  
    11*** BEGIN OF TEST SMPCACHE 1 ***
    2 Calling standard SMP cache functions. Done!
    3 Calling standard SMP cache functions with ISR disabled. Done!
    4 Calling standard SMP cache functions with CPU0 holding the giant lock. Done!
    5 Calling a test function using the SMP cache manager to verify that all CPUs receive the SMP message. Done!
    6 Calling a test function using the SMP cache manager to verify that all CPUs receive the SMP message. With ISR disabled. Done!
    7 Calling a test function using the SMP cache manager to verify that all CPUs receive the SMP message. With CPU0 holding the giant lock. Done!
     2Calling test cases. Done!
     3Calling test cases with ISR disabled. Done!
     4Calling test cases with CPU0 holding the giant lock. Done!
    85*** END OF TEST SMPCACHE 1 ***
Note: See TracChangeset for help on using the changeset viewer.