Changeset b1ac3a5 in rtems
- Timestamp:
-
03/01/19 18:21:52
(5 years ago)
- Author:
- Jonathan Brandmeyer <jbrandmeyer@…>
- Branches:
- 5, master
- Children:
- 2e8a66d
- Parents:
- 3b68442
- git-author:
- Jonathan Brandmeyer <jbrandmeyer@…> (03/01/19 18:21:52)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (03/08/19 06:39:42)
- Message:
-
cpukit/arm: Correct register definition
The register definition for the CP15 PMCR (performance monitor control
register) has the bits for X (export enable) and D (clock divider
enable) backwards. Correct them according to ARMv7-A/R Architecture
Reference Manual, Rev C, Section B4.1.117.
Consequences: On an implementation that starts off with D set at reset,
the clock divider will not be disabled by using RTEMS' definition of the
D bit.
Tested by using the counter on Xilinx Zynq 7020 to measure some atomic
accesses and cache flushing operations.
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(No files)
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