Changeset b047186 in rtems


Ignore:
Timestamp:
Sep 14, 2007, 3:43:37 PM (12 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Children:
e49b92e0
Parents:
622e09b
Message:

2007-09-14 Kate Feng <feng1@…>

  • Makefile.am, README, README.booting, README.irq, preinstall.am, GT64260/MVME5500I2C.c, include/bsp.h, irq/irq.c, irq/irq.h, irq/irq_init.c, pci/pci.c, pci/pci_interface.c, pci/pcifinddevice.c, start/preload.S, startup/bspclean.c, startup/bspstart.c, startup/pgtbl_activate.c, startup/reboot.c: Merge my improvements in this BSP including a new network driver for the 1GHz NIC.
  • network/if_100MHz/GT64260eth.c, network/if_100MHz/GT64260eth.h, network/if_100MHz/GT64260ethreg.h, network/if_100MHz/Makefile.am, network/if_1GHz/Makefile.am, network/if_1GHz/POSSIBLEBUG, network/if_1GHz/if_wm.c, network/if_1GHz/if_wmreg.h, network/if_1GHz/pci_map.c, network/if_1GHz/pcireg.h: New files.
Location:
c/src/lib/libbsp/powerpc/mvme5500
Files:
10 added
19 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/mvme5500/ChangeLog

    r622e09b rb047186  
     12007-09-14      Kate Feng <feng1@bnl.gov>
     2
     3        * Makefile.am, README, README.booting, README.irq,
     4        preinstall.am, GT64260/MVME5500I2C.c, include/bsp.h, irq/irq.c,
     5        irq/irq.h, irq/irq_init.c, pci/pci.c, pci/pci_interface.c,
     6        pci/pcifinddevice.c, start/preload.S, startup/bspclean.c,
     7        startup/bspstart.c, startup/pgtbl_activate.c, startup/reboot.c:
     8        Merge my improvements in this BSP including a new network
     9        driver for the 1GHz NIC.
     10        * network/if_100MHz/GT64260eth.c, network/if_100MHz/GT64260eth.h,
     11        network/if_100MHz/GT64260ethreg.h, network/if_100MHz/Makefile.am,
     12        network/if_1GHz/Makefile.am, network/if_1GHz/POSSIBLEBUG,
     13        network/if_1GHz/if_wm.c, network/if_1GHz/if_wmreg.h,
     14        network/if_1GHz/pci_map.c, network/if_1GHz/pcireg.h: New files.
     15
    1162007-04-06      Ralf Corsépius <ralf.corsepius@rtems.org>
    217
  • c/src/lib/libbsp/powerpc/mvme5500/GT64260/MVME5500I2C.c

    r622e09b rb047186  
    1313
    1414#include <rtems/bspIo.h>            /* printk */
    15 #include <rtems/stdint.h>
    1615#include "bsp/GT64260TWSI.h"
    1716
    1817/* #define I2C_DEBUG*/
     18typedef unsigned int u32;
     19typedef unsigned char unchar;
    1920
    20 unsigned char I2cAddrPack(unsigned char busAddr,uint32_t offset)
     21unchar I2cAddrPack(unchar busAddr,u32 offset)
    2122{
    2223  return(busAddr | ((offset & 0x700) >> 7));
    2324}
    24 unsigned char I2cDevByteAddr(uint32_t devA2A1A0, unsigned char byteNum)
     25unchar I2cDevByteAddr(u32 devA2A1A0, unchar byteNum)
    2526{
    2627  return(( devA2A1A0 >>(byteNum*8)) & 0xff);
     
    2930* I2Cread_eeprom - read EEPROM VPD from the I2C
    3031*/
    31 int I2Cread_eeprom(unsigned char I2cBusAddr,uint32_t devA2A1A0,uint32_t AddrBytes,unsigned char *pBuff,uint32_t numBytes)
     32int I2Cread_eeprom(unchar I2cBusAddr,u32 devA2A1A0,u32 AddrBytes,unchar *pBuff,u32 numBytes)
    3233{
    3334  int status=0, lastByte=0;
  • c/src/lib/libbsp/powerpc/mvme5500/Makefile.am

    r622e09b rb047186  
    77include $(top_srcdir)/../../../../automake/compile.am
    88include $(top_srcdir)/../../bsp.am
     9
     10#prevent the compiler from generating FP instructions
     11AM_CFLAGS      += -msoft-float
    912
    1013dist_project_lib_DATA = bsp_specs
     
    3033startup_rel_SOURCES = startup/bspstart.c \
    3134    ../../powerpc/shared/startup/pgtbl_setup.c startup/pgtbl_activate.c \
     35    ../../powerpc/shared/startup/pretaskinghook.c \
    3236    ../../powerpc/shared/startup/sbrk.c ../../shared/bootcard.c \
    3337    startup/bspclean.c ../../shared/bsplibc.c ../../shared/bsppost.c \
     
    4347
    4448###
    45 include_bsp_HEADERS = ../../powerpc/shared/console/uart.h       \
    46         ../../shared/vmeUniverse/vme_am_defs.h
     49include_bsp_HEADERS = ../../powerpc/shared/console/uart.h
     50include_bsp_HEADERS += ../../powerpc/shared/console/consoleIo.h
    4751
    4852noinst_PROGRAMS += console.rel
     
    6569
    6670noinst_PROGRAMS += irq.rel
    67 irq_rel_SOURCES = irq/irq_init.c irq/GT64260Int.c irq/irq.c \
     71irq_rel_SOURCES = irq/irq_init.c irq/irq.c \
    6872    ../../powerpc/shared/irq/irq_asm.S
    6973irq_rel_CPPFLAGS = $(AM_CPPFLAGS)
     
    98102##
    99103if HAS_NETWORKING
    100 include_bsp_HEADERS += network/GT64260eth.h network/GT64260ethreg.h
     104include_bsp_HEADERS += network/if_100MHz/GT64260eth.h network/if_100MHz/GT64260ethreg.h \
     105    network/if_1GHz/if_wmreg.h network/if_1GHz/pcireg.h
    101106
    102107network_CPPFLAGS = -D_KERNEL
    103108noinst_PROGRAMS += network.rel
    104 network_rel_SOURCES = network/GT64260eth.c
     109network_rel_SOURCES = network/if_100MHz/GT64260eth.c \
     110    network/if_1GHz/if_wm.c network/if_1GHz/pci_map.c
    105111network_rel_CPPFLAGS = $(AM_CPPFLAGS) $(network_CPPFLAGS)
    106112network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    107113endif
    108 ##
    109 include_bsp_HEADERS += ../../shared/vmeUniverse/VME.h vme/VMEConfig.h
    110 include_bsp_HEADERS += ../../shared/vmeUniverse/vmeUniverse.h \
     114##vme
     115include_bsp_HEADERS += ../../shared/vmeUniverse/VME.h vme/VMEConfig.h \
     116        ../../shared/vmeUniverse/vmeUniverse.h \
    111117        ../../shared/vmeUniverse/vmeUniverseDMA.h\
    112118        ../../shared/vmeUniverse/bspVmeDmaList.h\
    113         ../../shared/vmeUniverse/VMEDMA.h
     119        ../../shared/vmeUniverse/VMEDMA.h \
     120        ../../shared/vmeUniverse/vme_am_defs.h
    114121
    115122noinst_PROGRAMS += vme.rel
    116 vme_rel_SOURCES = ../../shared/vmeUniverse/vmeUniverse.c
    117 vme_rel_SOURCES+= ../../shared/vmeUniverse/bspVmeDmaList.c
    118 vme_rel_SOURCES+= ../shared/vme/vmeconfig.c
    119 vme_rel_SOURCES+= ../shared/vme/vme_universe.c
    120 vme_rel_SOURCES+= ../shared/vme/vme_universe_dma.c
     123vme_rel_SOURCES = ../../shared/vmeUniverse/vmeUniverse.c\
     124        ../shared/vme/vmeconfig.c ../../shared/vmeUniverse/bspVmeDmaList.c\
     125        ../shared/vme/vme_universe.c ../shared/vme/vme_universe_dma.c
    121126
    122127vme_rel_CPPFLAGS = $(AM_CPPFLAGS)
  • c/src/lib/libbsp/powerpc/mvme5500/README

    r622e09b rb047186  
    11#
    2 #  $Id$
     2#  $Id: README,v 1.3.1  Shuchen Kate Feng, NSLS, BNL (08/27/07)
    33#
     4
     5Please reference README.booting for the boot/load process.
     6
     7For the priority setting of the Interrupt Requests (IRQs), please
     8reference README.irq
     9
     10The BSP is built and tested on the 4.7.1 and 4.7.99.2 CVS RTEMS release.
     11
     12I believe in valuable real-time programming, where technical neatness,
     13performance and truth are.  Any suggestion, bug reports, or even bug
     14fixes (great!) are welcome so that I still believe what I believe.
     15
     16
     17ACKNOWLEDGEMENTS
     18----------------
     19Acknowledgements:
     20
     21Valuable information was obtained from the following:
     221) Marvell NDA document for the discovery system controller.
     23Other related documents are listed at :
     24http://www.aps.anl.gov/epics/meetings/2006-06/RTEMS_Primer_SIG/RTEMS_BSP_MVME5500.pdf
     252) netBSD: For the two NICS and some headers :
     26           Allegro Networks, Inc., Wasabi Systems, Inc. 
     273) RTEMS: For the SVGM5 BSP
     28          Stanford Linear Accelerator Center, Till Straumann
     29
     30 This BSP also builds on top of the work of others who have contributed
     31 to similar RTEMS powerpc shared and motorola_powerpc BSPs, most notably
     32 Eric Valette, Till Straumann, Eric Norum and others.
     33
     34LICENSE
     35-------
     36See ./LICENSE file.
    437
    538BSP NAME:           mvme5500
     
    1245DEBUG MONITOR:      MOTLoad
    1346SYSTEM CONTROLLER:  GT64260B
    14 
    15 OTHER README FILES: README.booting,README.rtems-4.6.0-patch,README.VME,
    16                     README.irq
    1747
    1848PERIPHERALS
  • c/src/lib/libbsp/powerpc/mvme5500/README.booting

    r622e09b rb047186  
    1 README.booting: written by S. Kate Feng <feng1@bnl.gov>, 2004/10/11
     1README.booting: written by S. Kate Feng <feng1@bnl.gov>, Aug. 28, 2007
    22
    33The bootloader is adapted from Till Straumann's Generic Mini-loader,
    4 which he wrote originally for the SVGM powerpc board. Part of the
    5 BSP was derived from the "RTEMS-PowerPC BSPs" and the NetBSD projects.
    6 As of today, the BSP is built and tested on the RTEMS-4.6.0
    7 release with small patches I added (see README.rtems-4.6.0-patch
    8 and rtems-4.6.0-patch/ directory).
    9 
     4which he wrote originally for the SVGM powerpc board.
     5The BSP is built and tested on the 4.7 CVS RTEMS release.
    106
    117Booting requirement :
    128-------------------------
    139
    14 1) One needs to setup BOOTP/DHCP and TFTP servers and /etc/bootptab
    15    properly to boot the system.  (Note : EPICS needs a NTP server).
     101) One needs to setup BOOTP/DHCP and TFTP servers and /etc/bootptab(BOOTP)
     11   or /etc/dhcpd.conf (DHCP) properly to boot the system.
     12   (Note : EPICS needs a NTP server).
    1613 
    17142) Please copy the prebuilt RTEMS binary (e.g. misc/rtems5500-cexp.bin)
     
    3633        sxx.xx.xx.xx is the server IP address)
    3734
    38 4) Other reference web sites:
     354) Other reference web sites for mvme5500 BSP:
    3936http://lansce.lanl.gov/EPICS/presentations/KateFeng%20RTEMS-mvme55001.ppt
     37http://www.nsls.bnl.gov/facility/expsys/software/EPICS/
     38http://www.nsls.bnl.gov/facility/expsys/software/EPICS/FAQ.txt
    4039
    41405) When generating code (especially C++) for this system, one should
     
    5453http://www.aps.anl.gov/epics/base/RTEMS/tutorial/
    5554in additional to the RTEMS document.
    56 
    57 
    58 TODO lists:
    59 1) 1 GHZ ethernet ( work in progress, to be released soon)
    60 2) To measure the interrupt latency and context switching.
    61 3) To implement the watchdog timer.
    62 
  • c/src/lib/libbsp/powerpc/mvme5500/README.irq

    r622e09b rb047186  
    1 README.irq : Shuchen Kate Feng  <feng1@bnl.gov>, 10/10/04
     1README.irq : Shuchen Kate Feng  <feng1@bnl.gov>, Sept. 2, 2007
     2
     3As per implementation in shared PPC code,
     4the BSPirqPrioTable[96] listed in irq_init.c is where the
     5software developers can change the levels of priority
     6for all the interrupts based on the need of their
     7applications.  The IRQs can be eanbled dynamically via the
     8BSP_enable_pic_irq(), or disbaled dynamically via the
     9BSP_disable_pic_irq().
    210
    311
    4 The BSPirqPrioTable[] listed in irq_init.c is where the
    5 software developers can change the levels of priority
    6 for main interrupts based on the need of their
    7 applications.
     12Support for run-time priority setup could be
     13added easily, but there is no action taken yet due to concerns
     14over computer security at VME CPU level.
    815
    916
    10 Presently, a dynamic IRQ table (e.g. mainIrqTbl[64]), which is
    11 arranged dynamically based on the priority levels of enabled
    12 main interrupts, is used in C_dispatch_irq_handler() to
    13 incorporate the handling of the software priority levels.
    14 
    15 
    16 The valid entries listed in mainIrqTbl[64] by the BSP are:
    17 
    18 1. Main interrupt 59   (GPP31_24 : no enabled IRQ yet,
    19                         to enable 'watchdog timer' if needed)
    20 2. Main interrupt 57   (GPP15_8  : VME interrupt enabled,
    21                         to enable 'PMC1' if needed)
    22 3. Main interrupt 58   (GPP23_16 : no enabled IRQ yet,
    23                         to enable '1 GHZ ethernet' or 'PMC2'
    24                         if needed)
    25 4. Main interrupt 32   (10/100 MHZ ethernet)
    26 5. Main interrupt 56   (GPP7_0 : presently only COM1/COM2 enabled)
    27 
    28 
    29 The main IRQs can be added to the mainIrqTbl[] dynamically
    30 via the BSP_enable_main_irq(), or removed from the mainIrqTbl[]
    31 dynamically via the BSP_disable_main_irq().
    32 
    33 
    34 Regarding other GPP interrupts not listed in the GPP7_0IrqTbl[8],
    35 GPP15_8IrqTbl[8], GPP23_16IrqTbl[8], or GPP31_24IrqTbl[8], they
    36 could be enabled by being added to the correspondent of
    37 the four aforementioned tables listed in the irq_init.c.
    38 
    39 
    40 Caveat: Presently, the eight GPP IRQs for each BSP_MAIN_GPPx_y_IRQ group
    41 are set at the same main priority in the BSPirqPrioTable[], while the
    42 sub-priority levels for the eight GPP in each group  are sorted
    43 statically by developers in the GPPx_yIrqTbl[8] from the highest
    44 priority to the lowest one.
    45 
    46 
    47 Note :
    48 1. GPP7-0   (Main interrupt high cause, bit 24)
    49 2. GPP15-8  (Main interrupt high cause, bit 25)
    50 3. GPP23-16 (Main interrupt high cause, bit 26)
    51 4. GPP31-24 (Main interrupt high cause, bit 27)
    52 
     17The software developers are forbidden to setup picIsrTable[],
     18as it is a powerful engine for the BSP to find the pending
     19highest priority IRQ at run time. It ensures the fastest/faster
     20interrupt service to the highest/higher priority IRQ, if pending.
  • c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h

    r622e09b rb047186  
    88 *  http://www.rtems.com/license/LICENSE.
    99 *
    10  *  S. Kate Feng 12/03 : Modified it to support the MVME5500 board.
     10 *  S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP.
    1111 *
    1212 */
     
    5454
    5555
    56 #if 0
    57 /* T.S, 2007/1: in order to let the universe acknowledge the interrupt
    58  * (this allows for VME software priorities) corresponding support
    59  * **MUST** be present in the interrupt controller driver
    60  * Unless that's implemented DO NOT define BSP_PIC_DO_EOI.
     56/* The glues to Till's vmeUniverse, although the name does not
     57 * actually reflect the relevant architect of the MVME5500.
     58 * Till TODO ? :  BSP_PCI_DO_EOI instead ?
     59 * BSP_EXT_IRQ0 instead of BSP_PCI_IRQ0 ?
     60 *
    6161 */
    6262#define BSP_PIC_DO_EOI  inl(0xc34)  /* PCI IACK */
    63 #endif
    6463#define BSP_PCI_IRQ0 BSP_GPP_IRQ_LOWEST_OFFSET
    6564
     
    112111extern unsigned long _BSP_clear_hostbridge_errors();
    113112
     113extern unsigned int BSP_heap_start;
     114
     115#if 1
    114116#define RTEMS_BSP_NETWORK_DRIVER_NAME   "gt1"
    115117#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_GT64260eth_driver_attach
     118#else
     119#define RTEMS_BSP_NETWORK_DRIVER_NAME   "wmG1"
     120#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_i82544EI_driver_attach
     121#endif
    116122
    117123extern int
    118124RTEMS_BSP_NETWORK_DRIVER_ATTACH(/* struct rtems_bsdnet_ifconfig * */);
    119125
     126#define gccMemBar() RTEMS_COMPILER_MEMORY_BARRIER()
     127
     128static inline void memBar()
     129{
     130    asm volatile("sync":::"memory");
     131}
     132static inline void ioBar()
     133{
     134    asm volatile("eieio":::"memory");
     135}
    120136
    121137#endif
  • c/src/lib/libbsp/powerpc/mvme5500/irq/irq.c

    r622e09b rb047186  
    77 *  The license and distribution terms for this file may be
    88 *  found in the file LICENSE in this distribution or at
    9  *  http://www.rtems.com/license/LICENSE.
    10  *
    11  *  Special acknowledgement to Till Straumann <strauman@slac.stanford.edu>
    12  *  for providing inputs to the IRQ handling and optimization.
    13  *
    14  *  Modified and added support for the MVME5500 board
    15  *  Copyright 2003, 2004, Shuchen Kate Feng <feng1@bnl.gov>,
     9 *  http://www.OARcorp.com/rtems/license.html.
     10 *
     11 *  Acknowledgement May 2004 : to Till Straumann <strauman@slac.stanford.edu>
     12 *  for some inputs.
     13 *
     14 *  Copyright 2003, 2004, 2005, 2007  Shuchen Kate Feng <feng1@bnl.gov>,
    1615 *                  NSLS,Brookhaven National Laboratory
     16 *  1) Modified and added support for the MVME5500 board.
     17 *  2) The implementation of picIsrTable[] is an original work by the
     18 *     author to optimize the software IRQ priority scheduling because
     19 *     Discovery controller does not provide H/W IRQ priority schedule.
     20 *     It ensures the fastest/faster interrupt service to the
     21 *     highest/higher priority IRQ, if pendig.
     22 *  3) _CPU_MSR_SET() needs RTEMS_COMPILER_MEMORY_BARRIER()
    1723 *
    1824 */
     
    2430#include <rtems/score/apiext.h>
    2531#include <libcpu/raw_exception.h>
     32#include <rtems/rtems/intr.h>
    2633#include <libcpu/io.h>
     34#include <libcpu/byteorder.h>
    2735#include <bsp/vectors.h>
    2836
     
    3240#define HI_INT_CAUSE 0x40000000
    3341
    34 /*#define DEBUG*/
    35 
    36 int gpp_int_error =0;
     42#define MAX_IRQ_LOOP 30
     43
     44#define EDGE_TRIGGER
     45
     46#define _MSR_GET( _mask) \
     47  do { \
     48     RTEMS_COMPILER_MEMORY_BARRIER(); \
     49     _CPU_MSR_GET( _mask); \
     50     RTEMS_COMPILER_MEMORY_BARRIER(); \
     51  } while (0);
     52
     53#define _MSR_SET( _mask) \
     54  do { \
     55     RTEMS_COMPILER_MEMORY_BARRIER(); \
     56     _CPU_MSR_SET( _mask); \
     57     RTEMS_COMPILER_MEMORY_BARRIER(); \
     58  } while (0);
     59
     60/* #define DEBUG_IRQ*/
    3761
    3862/*
    3963 * pointer to the mask representing the additionnal irq vectors
    4064 * that must be disabled when a particular entry is activated.
    41  * They will be dynamically computed from teh prioruty table given
     65 * They will be dynamically computed from the table given
    4266 * in BSP_rtems_irq_mngt_set();
    4367 * CAUTION : this table is accessed directly by interrupt routine
    4468 *           prologue.
    4569 */
    46 static unsigned int irq_prio_maskLO_tbl[BSP_MAIN_IRQ_NUMBER];
    47 static unsigned int irq_prio_maskHI_tbl[BSP_MAIN_IRQ_NUMBER];
     70static unsigned int BSP_irq_prio_mask_tbl[3][BSP_PIC_IRQ_NUMBER];
    4871
    4972/*
     
    5982static rtems_irq_connect_data*          rtems_hdl_tbl;
    6083
    61 static unsigned int irqCAUSE[20], irqLOW[20], irqHIGH[20];
    62 static int irqIndex=0;
    63 
    64 /*
    65  * Check if IRQ is a MAIN CPU internal IRQ
    66  */
    67 static inline int is_main_irq(const rtems_irq_number irqLine)
    68 {
    69   return (((int) irqLine <= BSP_MICH_IRQ_MAX_OFFSET) &
     84static volatile unsigned  *BSP_irqMask_reg[3];
     85static volatile unsigned  *BSP_irqCause_reg[3];
     86static volatile unsigned  BSP_irqMask_cache[3]={0,0,0};
     87
     88
     89static int picIsrTblPtr=0;
     90static unsigned int GPPIrqInTbl=0;
     91static unsigned long long MainIrqInTbl=0;
     92
     93/*
     94 * The software developers are forbidden to setup picIsrTable[],
     95 * as it is a powerful engine for the BSP to find the pending
     96 * highest priority IRQ at run time.  It ensures the fastest/faster
     97 * interrupt service to the highest/higher priority IRQ, if pendig.
     98 *
     99 * The picIsrTable[96] is updated dynamically at run time
     100 * based on the priority levels set at BSPirqPrioTable[96],
     101 * while the BSP_enable_pic_irq(), and BSP_disable_pic_irq()
     102 * commands are invoked.
     103 *
     104 * The picIsrTable[96] lists the enabled CPU main and GPP external interrupt
     105 * numbers [0 (lowest)- 95 (highest)] starting from the highest priority
     106 * one to the lowest priority one. The highest priority interrupt is
     107 * located at picIsrTable[0], and the lowest priority interrupt is located
     108 * at picIsrTable[picIsrTblPtr-1].
     109 *
     110 *
     111 */
     112/* BitNums for Main Interrupt Lo/High Cause and GPP, -1 means invalid bit */
     113static unsigned int picIsrTable[BSP_PIC_IRQ_NUMBER]={ 
     114     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     115     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     116     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     117     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     118     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     119     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     120     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     121     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     122     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     123     -1, -1, -1, -1, -1, -1 };
     124
     125
     126/*
     127 * Check if IRQ is a MAIN CPU internal IRQ or GPP external IRQ
     128 */
     129static inline int is_pic_irq(const rtems_irq_number irqLine)
     130{
     131  return (((int) irqLine <= BSP_GPP_IRQ_MAX_OFFSET) &
    70132          ((int) irqLine >= BSP_MICL_IRQ_LOWEST_OFFSET)
    71          );
    72 }
    73 
    74 /*
    75  * Check if IRQ is a GPP IRQ
    76  */
    77 static inline int is_gpp_irq(const rtems_irq_number irqLine)
    78 {
    79   return (((int) irqLine <= BSP_GPP_IRQ_MAX_OFFSET) &
    80           ((int) irqLine >= BSP_GPP_IRQ_LOWEST_OFFSET)
    81133         );
    82134}
     
    92144}
    93145
    94 #define GT_GPP_Int1_Cause GT_GPP_Interrupt_Cause+1
    95 #define GT_GPP_Int2_Cause GT_GPP_Interrupt_Cause+2
    96 #define GT_GPP_Int3_Cause GT_GPP_Interrupt_Cause+3
    97 
    98 void GT_GPP_IntHandler0()
    99 {
    100 
    101   unsigned  gppCause, irqNum, bitNum;
    102   int i, found=0;
    103 
    104   gppCause = inb(GT_GPP_Interrupt_Cause) & GT_GPPirq_cache;
    105 
    106   for (i=0; GPP7_0IrqTbl[i]!=-1;i++){
    107     bitNum =GPP7_0IrqTbl[i];
    108     if (gppCause & (1<<bitNum)) {
    109         /* Clear the GPP interrupt cause bit */
    110       outb( ~(1<<bitNum), GT_GPP_Interrupt_Cause);/* Till Straumann */
    111         found = 1;
    112         irqNum = bitNum+BSP_GPP_IRQ_LOWEST_OFFSET;
    113         /* call the necessary interrupt handlers */
    114         if (rtems_hdl_tbl[irqNum].hdl != default_rtems_entry.hdl)
    115            rtems_hdl_tbl[irqNum].hdl(rtems_hdl_tbl[irqNum].handle);
    116         else
    117            gpp_int_error= bitNum; /*GPP interrupt bitNum not connected */
    118     }
    119   }
    120   if ( !found) gpp_int_error = 33; /* spurious GPP interrupt  */
    121 }
    122 
    123 void GT_GPP_IntHandler1()
    124 {
    125   unsigned  gppCause, irqNum, bitNum;
    126   int i, found=0;
    127 
    128   gppCause = inb(GT_GPP_Int1_Cause) & (GT_GPPirq_cache>>8);
    129 
    130   for (i=0; GPP15_8IrqTbl[i]!=-1;i++){
    131     bitNum =GPP15_8IrqTbl[i];
    132     if (gppCause & (1<<bitNum)) {
    133         /* Clear the GPP interrupt cause bit */
    134         outb( ~(1<<bitNum), GT_GPP_Int1_Cause); /* Till Straumann */
    135         found = 1;
    136         irqNum = bitNum+BSP_GPP8_IRQ_OFFSET;
    137         /* call the necessary interrupt handlers */
    138         if (rtems_hdl_tbl[irqNum].hdl != default_rtems_entry.hdl)
    139            rtems_hdl_tbl[irqNum].hdl(rtems_hdl_tbl[irqNum].handle);
    140         else
    141            gpp_int_error= bitNum+8; /*GPP interrupt bitNum not connected */
    142     }
    143   }
    144   if ( !found) gpp_int_error = 33; /* spurious GPP interrupt  */
    145 }
    146 void GT_GPP_IntHandler2()
    147 {
    148   unsigned  gppCause, irqNum, bitNum;
    149   int i, found=0;
    150 
    151   gppCause = inb(GT_GPP_Int2_Cause) & (GT_GPPirq_cache>>16);
    152 
    153   for (i=0; GPP23_16IrqTbl[i]!=-1;i++){
    154     bitNum =GPP23_16IrqTbl[i];
    155     if (gppCause & (1<<bitNum)) {
    156         /* Clear the GPP interrupt cause bit */
    157         outb( ~(1<<bitNum), GT_GPP_Int2_Cause);
    158         found = 1;
    159         irqNum = bitNum+BSP_GPP16_IRQ_OFFSET;
    160         /* call the necessary interrupt handlers */
    161         if (rtems_hdl_tbl[irqNum].hdl != default_rtems_entry.hdl)
    162             rtems_hdl_tbl[irqNum].hdl(rtems_hdl_tbl[irqNum].handle);
    163         else
    164            gpp_int_error= bitNum+16; /*GPP interrupt bitNum not connected */
    165     }
    166   }
    167   if ( !found) gpp_int_error = 33; /* spurious GPP interrupt  */
    168 }
    169 
    170 void GT_GPP_IntHandler3()
    171 {
    172   unsigned  gppCause, irqNum, bitNum;
    173   int i, found=0;
    174 
    175   gppCause = inb(GT_GPP_Int3_Cause) & (GT_GPPirq_cache>>24);
    176 
    177   for (i=0; GPP31_24IrqTbl[i]!=-1;i++){
    178     bitNum=GPP31_24IrqTbl[i];
    179     if (gppCause & (1<<bitNum)) {
    180         /* Clear the GPP interrupt cause bit */
    181         outb(~(1<<bitNum), GT_GPP_Int3_Cause);
    182         found = 1;
    183         irqNum = bitNum+BSP_GPP24_IRQ_OFFSET;
    184         /* call the necessary interrupt handlers */
    185         if (rtems_hdl_tbl[irqNum].hdl != default_rtems_entry.hdl)
    186             rtems_hdl_tbl[irqNum].hdl(rtems_hdl_tbl[irqNum].handle);
    187         else
    188            gpp_int_error= bitNum+24; /*GPP interrupt bitNum not connected */
    189     }
    190   }
    191   if ( !found) gpp_int_error = 33; /* spurious GPP interrupt  */
     146static inline unsigned int divIrq32(unsigned irq)
     147{
     148  return(irq/32);
     149}
     150
     151static inline unsigned int modIrq32(unsigned irq)
     152{
     153   return(irq%32);
    192154}
    193155
     
    201163 * and accessible.
    202164 */
    203 static void compute_GT64260int_masks_from_prio ()
    204 {
    205   int i,j;
     165static void compute_pic_masks_from_prio()
     166{
     167  int i,j, k;
    206168  unsigned long long irq_prio_mask=0;
    207169
     
    209171   * Always mask at least current interrupt to prevent re-entrance
    210172   */
    211   for (i=0; i <BSP_MAIN_IRQ_NUMBER; i++) {
    212     irq_prio_mask = (unsigned long long) (1LLU << i);
     173  for (i=0; i <BSP_PIC_IRQ_NUMBER; i++) {
     174    switch(i) {
     175      case BSP_MAIN_GPP7_0_IRQ:
     176      case BSP_MAIN_GPP15_8_IRQ:
     177      case BSP_MAIN_GPP23_16_IRQ:
     178      case BSP_MAIN_GPP31_24_IRQ:
     179        for (k=0; k< 3; k++)
     180            BSP_irq_prio_mask_tbl[k][i]=0;
     181
     182        irq_prio_mask =0;
     183        break;
     184      default :
     185        irq_prio_mask = (unsigned long long) (1LLU << i);
     186        break;
     187    }
     188   
     189    if (irq_prio_mask) {
    213190    for (j = 0; j <BSP_MAIN_IRQ_NUMBER; j++) {
    214       /*
    215        * Mask interrupts at GT64260int level that have a lower priority
    216        * or <Till Straumann> a equal priority.
    217        */
    218       if (internal_config->irqPrioTbl [i] >= internal_config->irqPrioTbl [j]) {
    219          irq_prio_mask |= (unsigned long long)(1LLU << j);
     191        /*
     192         * Mask interrupts at PIC level that have a lower priority
     193         * or <Till Straumann> a equal priority.
     194         */
     195        if (internal_config->irqPrioTbl [i] >= internal_config->irqPrioTbl [j])
     196           irq_prio_mask |= (unsigned long long)(1LLU << j);
     197    }
     198   
     199
     200    BSP_irq_prio_mask_tbl[0][i] = irq_prio_mask & 0xffffffff;
     201    BSP_irq_prio_mask_tbl[1][i] = (irq_prio_mask>>32) & 0xffffffff;
     202#ifdef DEBUG
     203    printk("irq_mask_prio_tbl[%d]:0x%8x%8x\n",i,BSP_irq_prio_mask_tbl[1][i],
     204           BSP_irq_prio_mask_tbl[0][i]);
     205#endif
     206
     207    BSP_irq_prio_mask_tbl[2][i] = 1<<i;
     208    /* Compute for the GPP priority interrupt mask */
     209    for (j=BSP_GPP_IRQ_LOWEST_OFFSET; j <BSP_PROCESSOR_IRQ_LOWEST_OFFSET; j++) {     
     210      if (internal_config->irqPrioTbl [i] >= internal_config->irqPrioTbl [j])
     211           BSP_irq_prio_mask_tbl[2][i] |= 1 << (j-BSP_GPP_IRQ_LOWEST_OFFSET);
     212    }
     213    }
     214  }
     215}
     216
     217
     218static void UpdateMainIrqTbl(int irqNum)
     219{
     220  int i=0, j, shifted=0;
     221
     222  switch (irqNum) {
     223    case BSP_MAIN_GPP7_0_IRQ:
     224    case BSP_MAIN_GPP15_8_IRQ:
     225    case BSP_MAIN_GPP23_16_IRQ:
     226    case BSP_MAIN_GPP31_24_IRQ: 
     227      return;  /* Do nothing, let GPP take care of it */
     228      break;
     229  }
     230#ifdef SHOW_MORE_INIT_SETTINGS
     231  unsigned long val2, val1;
     232#endif
     233
     234  /* If entry not in table*/
     235  if ( ((irqNum<BSP_GPP_IRQ_LOWEST_OFFSET) &&
     236        (!((unsigned long long)(1LLU << irqNum) & MainIrqInTbl))) ||
     237       ((irqNum>BSP_MICH_IRQ_MAX_OFFSET) &&
     238        (!(( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl))))
     239  {
     240      while ( picIsrTable[i]!=-1) {
     241        if (internal_config->irqPrioTbl[irqNum]>internal_config->irqPrioTbl[picIsrTable[i]]) {
     242          /* all other lower priority entries shifted right */
     243          for (j=picIsrTblPtr;j>i; j--)
     244              picIsrTable[j]=picIsrTable[j-1];
     245          picIsrTable[i]=irqNum;
     246          shifted=1;
     247          break;
     248       }
     249       i++;
     250     }
     251     if (!shifted) picIsrTable[picIsrTblPtr]=irqNum;
     252     if (irqNum >BSP_MICH_IRQ_MAX_OFFSET)
     253        GPPIrqInTbl |= (1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET));
     254     else     
     255        MainIrqInTbl |= (unsigned long long)(1LLU << irqNum);
     256     picIsrTblPtr++;
     257  }
     258#ifdef SHOW_MORE_INIT_SETTINGS
     259  val2 = (MainIrqInTbl>>32) & 0xffffffff;
     260  val1 = MainIrqInTbl&0xffffffff;
     261  printk("irqNum %d, MainIrqInTbl 0x%x%x\n", irqNum, val2, val1);
     262  BSP_printPicIsrTbl();
     263#endif
     264
     265}
     266
     267
     268static void CleanMainIrqTbl(int irqNum)
     269{
     270  int i, j;
     271
     272  switch (irqNum) {
     273    case BSP_MAIN_GPP7_0_IRQ:
     274    case BSP_MAIN_GPP15_8_IRQ:
     275    case BSP_MAIN_GPP23_16_IRQ:
     276    case BSP_MAIN_GPP31_24_IRQ:
     277      return;  /* Do nothing, let GPP take care of it */
     278      break; 
     279  }
     280  if ( ((irqNum<BSP_GPP_IRQ_LOWEST_OFFSET) &&
     281        ((unsigned long long)(1LLU << irqNum) & MainIrqInTbl)) ||
     282       ((irqNum>BSP_MICH_IRQ_MAX_OFFSET) &&
     283        (( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl)))
     284  { /* If entry in table*/
     285     for (i=0; i<64; i++) {
     286       if (picIsrTable[i]==irqNum) {/*remove it from the entry */
     287          /* all other lower priority entries shifted left */
     288          for (j=i;j<picIsrTblPtr; j++)
     289              picIsrTable[j]=picIsrTable[j+1];
     290          if (irqNum >BSP_MICH_IRQ_MAX_OFFSET)
     291            GPPIrqInTbl &= ~(1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET));
     292          else     
     293            MainIrqInTbl &= ~(1LLU << irqNum);
     294          picIsrTblPtr--;
     295          break;
     296       }
     297     }
     298  }
     299}
     300
     301void BSP_enable_pic_irq(const rtems_irq_number irqNum)
     302{
     303  unsigned bitNum, regNum;
     304  unsigned int level;
     305
     306  bitNum = modIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
     307  regNum = divIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
     308
     309  rtems_interrupt_disable(level);
     310
     311  UpdateMainIrqTbl((int) irqNum);
     312  BSP_irqMask_cache[regNum] |= (1 << bitNum);
     313
     314  out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);
     315  while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]);
     316
     317  rtems_interrupt_enable(level);
     318}
     319
     320void BSP_disable_pic_irq(const rtems_irq_number irqNum)
     321{
     322  unsigned bitNum, regNum;
     323  unsigned int level;
     324
     325  bitNum = modIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
     326  regNum = divIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
     327
     328  rtems_interrupt_disable(level);
     329
     330  CleanMainIrqTbl((int) irqNum);
     331  BSP_irqMask_cache[regNum] &=  ~(1 << bitNum);
     332
     333  out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);
     334  while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]);
     335
     336  rtems_interrupt_enable(level);
     337}
     338
     339int BSP_setup_the_pic()  /* adapt the same name as shared/irq */
     340{
     341    int i;
     342
     343    /* Get ready for discovery BSP */
     344    BSP_irqMask_reg[0]= (volatile unsigned int *) (GT64260_REG_BASE + GT_CPU_INT_MASK_LO);
     345    BSP_irqMask_reg[1]= (volatile unsigned int *) (GT64260_REG_BASE + GT_CPU_INT_MASK_HI);
     346    BSP_irqMask_reg[2]= (volatile unsigned int *) (GT64260_REG_BASE + GT_GPP_Interrupt_Mask);
     347
     348    BSP_irqCause_reg[0]= (volatile unsigned int *) (GT64260_REG_BASE + GT_MAIN_INT_CAUSE_LO);
     349    BSP_irqCause_reg[1]= (volatile unsigned int *) (GT64260_REG_BASE + GT_MAIN_INT_CAUSE_HI);
     350    BSP_irqCause_reg[2]= (volatile unsigned int *) (GT64260_REG_BASE + GT_GPP_Interrupt_Cause);
     351
     352#ifdef EDGE_TRIGGER
     353
     354    /* Page 401, Table 598:
     355     * Comm Unit Arbiter Control register :
     356     * bit 10:GPP interrupts as level sensitive(1) or edge sensitive(0).
     357     * We set the GPP interrupts to be edge sensitive.
     358     * MOTload default is set as level sensitive(1).
     359     */
     360    outl((inl(GT_CommUnitArb_Ctrl)& (~(1<<10))), GT_CommUnitArb_Ctrl);
     361#else
     362    outl((inl(GT_CommUnitArb_Ctrl)| (1<<10)), GT_CommUnitArb_Ctrl);
     363#endif
     364
     365#if 0
     366    printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n",
     367           in_le32(BSP_irqMask_reg[0]),
     368           in_le32(BSP_irqCause_reg[0]));
     369    printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n",
     370           in_le32(BSP_irqMask_reg[1]),
     371           in_le32(BSP_irqCause_reg[1]));
     372    printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n",
     373           in_le32(BSP_irqMask_reg[2]),
     374           in_le32(BSP_irqCause_reg[2]));
     375#endif
     376
     377    /* Initialize the interrupt related GT64260 registers */
     378    for (i=0; i<3; i++) {
     379      out_le32(BSP_irqCause_reg[i], 0);
     380      out_le32(BSP_irqMask_reg[i], 0);
     381    }         
     382    in_le32(BSP_irqMask_reg[2]);
     383    compute_pic_masks_from_prio();
     384
     385#if 0
     386    printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n",
     387           in_le32(BSP_irqMask_reg[0]),
     388           in_le32(BSP_irqCause_reg[0]));
     389    printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n",
     390           in_le32(BSP_irqMask_reg[1]),
     391           in_le32(BSP_irqCause_reg[1]));
     392    printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n",
     393           in_le32(BSP_irqMask_reg[2]),
     394           in_le32(BSP_irqCause_reg[2]));
     395#endif
     396
     397    /*
     398     *
     399     */
     400    for (i=BSP_MICL_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET ; i++) {
     401      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
     402        BSP_enable_pic_irq(i);
     403        rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
    220404      }
    221     }
    222 
    223     irq_prio_maskLO_tbl[i] = irq_prio_mask & 0xffffffff;
    224     irq_prio_maskHI_tbl[i] = (irq_prio_mask>>32) & 0xffffffff;
    225 #ifdef DEBUG
    226     printk("irq_mask_prio_tbl[%d]:0x%8x%8x\n",i,irq_prio_maskHI_tbl[i],
    227            irq_prio_maskLO_tbl[i]);
    228 #endif 
    229   }
     405      else {
     406        rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
     407        BSP_disable_pic_irq(i);
     408      }
     409    }
     410
     411    return(1);
    230412}
    231413
     
    261443     * to get the previous handler before accepting to disconnect.
    262444     */
    263     _CPU_ISR_Disable(level);
     445    rtems_interrupt_disable(level);
    264446    if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
    265       _CPU_ISR_Enable(level);
     447      rtems_interrupt_enable(level);
    266448      printk("IRQ vector %d already connected\n",irq->name);
    267449      return 0;
     
    272454     */
    273455    rtems_hdl_tbl[irq->name] = *irq;
    274 
    275     if (is_main_irq(irq->name)) {
     456#ifdef BSP_SHARED_HANDLER_SUPPORT
     457    rtems_hdl_tbl[irq->name].next_handler = (void *)-1;
     458#endif
     459
     460    if (is_pic_irq(irq->name)) {
    276461      /*
    277        * Enable (internal ) Main Interrupt Cause Low and High
     462       * Enable PIC  irq : Main Interrupt Cause Low and High & GPP external
    278463       */
    279464#ifdef DEBUG_IRQ
    280       printk("main irq %d\n",irq->name);
    281 #endif
    282       BSP_enable_main_irq(irq->name);
    283     }
     465      printk("PIC irq %d\n",irq->name);
     466#endif
     467      BSP_enable_pic_irq(irq->name);
     468    }
     469    else {
     470      if (is_processor_irq(irq->name)) {
     471         /*
     472          * Enable exception at processor level
     473          */
     474
     475       }
     476    }
     477    /*
     478     * Enable interrupt on device
     479     */
     480    irq->on(irq);
    284481   
    285     if (is_gpp_irq(irq->name)) {
    286       /*
    287        * Enable (external) GPP[x] interrupt
    288        */
    289       BSP_enable_gpp_irq((int) irq->name);
    290     }
    291 
    292     if (is_processor_irq(irq->name)) {
    293       /*
    294        * Enable exception at processor level
    295        */
    296     }
    297     /*
    298      * Enable interrupt on device
    299      
    300     irq->on(irq);*/
    301    
    302     _CPU_ISR_Enable(level);
     482    rtems_interrupt_enable(level);
    303483
    304484    return 1;
     
    332512      return 0;
    333513    }
    334     _CPU_ISR_Disable(level);
    335 
    336     if (is_main_irq(irq->name)) {
    337       /*
    338        * disable CPU main interrupt
    339        */
    340       BSP_disable_main_irq(irq->name);
    341     }
    342     if (is_gpp_irq(irq->name)) {
    343       /*
    344        * disable external interrupt
    345        */
    346       BSP_disable_gpp_irq(irq->name);
    347     }
    348     if (is_processor_irq(irq->name)) {
    349       /*
    350        * disable exception at processor level
    351        */
     514    rtems_interrupt_disable(level);
     515
     516    /*
     517     * disable PIC interrupt
     518     */
     519    if (is_pic_irq(irq->name))
     520      BSP_disable_pic_irq(irq->name);
     521    else {
     522      if (is_processor_irq(irq->name)) {
     523         /*
     524          * disable exception at processor level
     525          */
     526       }
    352527    }   
    353528
     
    362537    rtems_hdl_tbl[irq->name] = default_rtems_entry;
    363538
    364     _CPU_ISR_Enable(level);
     539
     540    rtems_interrupt_enable(level);
    365541
    366542    return 1;
     
    373549int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
    374550{
     551    unsigned int level;
    375552    int i;
    376     unsigned int level;
     553
    377554   /*
    378555    * Store various code accelerators
     
    382559    rtems_hdl_tbl               = config->irqHdlTbl;
    383560
    384     _CPU_ISR_Disable(level);
    385     compute_GT64260int_masks_from_prio();
    386 
    387     /*
    388      * set up internal tables used by rtems interrupt prologue
    389      */
    390     /*
    391      * start with MAIN CPU IRQ
    392      */
    393     for (i=BSP_MICL_IRQ_LOWEST_OFFSET; i < BSP_GPP_IRQ_LOWEST_OFFSET ; i++) {
    394       if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
    395         BSP_enable_main_irq(i);
    396         rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
    397       }
    398       else {
    399         rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
    400         BSP_disable_main_irq(i);
    401       }
    402     }
    403     /*
    404      * continue with  external IRQ
    405      */
    406     for (i=BSP_GPP_IRQ_LOWEST_OFFSET; i<BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i++) {
    407       if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
    408         BSP_enable_gpp_irq(i);
    409         rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
    410       }
    411       else {
    412         rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
    413         BSP_disable_gpp_irq(i);
    414       }
    415     }
    416 
    417     /*
    418      * finish with Processor exceptions handled like IRQ
    419      */
    420     for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_MAX_OFFSET+1; i++) {
    421       if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
    422         rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
    423       }
    424       else {
    425         rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
    426       }
    427     }
    428     _CPU_ISR_Enable(level);
     561    rtems_interrupt_disable(level);
     562
     563    if ( !BSP_setup_the_pic() ) {
     564       printk("PIC setup failed; leaving IRQs OFF\n");
     565       return 0;
     566    }
     567
     568    for (i= BSP_MAIN_GPP7_0_IRQ; i <= BSP_MAIN_GPP31_24_IRQ; i++)
     569      BSP_enable_pic_irq(i);
     570
     571    rtems_interrupt_enable(level);
    429572    return 1;
    430573}
     
    436579}   
    437580
    438 int _BSP_vme_bridge_irq = -1;
    439 
    440581/*
    441582 * High level IRQ handler called from shared_raw_irq_code_entry
    442583 */
     584
    443585void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
    444586{
    445   register unsigned msr;
    446   register unsigned new_msr;
    447   unsigned mainCause[2];
    448   register unsigned selectCause;
    449   register unsigned oldMask[2]={0,0};
    450   unsigned i, regNum, irq, bitNum, startIrqNum=0;
     587  register unsigned msr, new_msr;
     588  unsigned long irqCause[3]={0, 0,0};
     589  register unsigned long selectCause;
     590  unsigned oldMask[3]={0,0,0};
     591  register unsigned i=0, j, irq=0, bitmask=0, group=0;
    451592
    452593  if (excNum == ASM_DEC_VECTOR) {
    453     _CPU_MSR_GET(msr);
     594    _MSR_GET(msr);
    454595    new_msr = msr | MSR_EE;
    455     _CPU_MSR_SET(new_msr);
     596    _MSR_SET(new_msr);
    456597   
    457598    rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle);
    458599
    459     _CPU_MSR_SET(msr);
     600    _MSR_SET(msr);
    460601    return;
    461602   
    462603  }
    463   selectCause = inl( GT_CPU_SEL_CAUSE);
    464   if (selectCause & HI_INT_CAUSE ) {
    465     mainCause[1]= selectCause & inl(GT_CPU_INT_MASK_HI);
    466     startIrqNum=32;
     604
     605  for (j=0; j<3; j++ ) oldMask[j] = BSP_irqMask_cache[j];
     606
     607  if ((selectCause= in_le32((volatile unsigned *)0xf1000c70)) & HI_INT_CAUSE ){
     608    irqCause[1] = (selectCause & BSP_irqMask_cache[1]);
     609    irqCause[2] = in_le32(BSP_irqCause_reg[2]) & BSP_irqMask_cache[2];
    467610  }
    468611  else {
    469     mainCause[0] =inl(GT_MAIN_INT_CAUSE_LO)&inl(GT_CPU_INT_MASK_LO);
    470     mainCause[1] =inl(GT_MAIN_INT_CAUSE_HI)&inl(GT_CPU_INT_MASK_HI);
    471   }
    472 
    473 #if 0
    474   /* very bad practice to put printk here, use only if for debug */
    475   printk("main 0 %x, main 1 %x \n", mainCause[0],mainCause[1]);
    476 #endif
    477   oldMask[0]= GT_MAINirqLO_cache;
    478   oldMask[1]= GT_MAINirqHI_cache;
    479 
    480   for (i=0;mainIrqTbl[i]!=-1;i++) {
    481     irq=mainIrqTbl[i];
    482     if ( irq < startIrqNum ) continue;
    483     regNum = irq/32;
    484     bitNum = irq % 32;
    485     if ( mainCause[regNum] & (1<<bitNum)) {
    486       GT_MAINirqLO_cache=oldMask[0]&(~irq_prio_maskLO_tbl[irq]);
    487       outl(GT_MAINirqLO_cache, GT_CPU_INT_MASK_LO);
    488       __asm __volatile("sync");
    489       GT_MAINirqHI_cache=oldMask[1]&(~irq_prio_maskHI_tbl[irq]);
    490       outl(GT_MAINirqHI_cache, GT_CPU_INT_MASK_HI);
    491       __asm __volatile("sync");
    492 
    493       /* <skf> It seems that reading back is necessary to ensure the
    494        * interrupt mask updated. Otherwise, spurious interrupt will
    495        * happen.  However, I do not want to use "while loop" to risk
    496        * the CPU stuck.  I wound rather keep track of the interrupt
    497        * mask if not updated.
    498        */
    499       if (((irqLOW[irqIndex]= inl(GT_CPU_INT_MASK_LO))!=GT_MAINirqLO_cache)||
    500           ((irqHIGH[irqIndex]= inl(GT_CPU_INT_MASK_HI))!=GT_MAINirqHI_cache)){
    501          irqIndex++;
    502          irqIndex %=20;
    503          irqCAUSE[irqIndex] = irq;
    504       }
    505       _CPU_MSR_GET(msr);
     612    irqCause[0] = (selectCause & BSP_irqMask_cache[0]);
     613    if ((irqCause[1] =(in_le32((volatile unsigned *)0xf1000c68)&BSP_irqMask_cache[1])))
     614       irqCause[2] = in_le32(BSP_irqCause_reg[2]) & BSP_irqMask_cache[2];
     615  }
     616 
     617  while ((irq = picIsrTable[i++])!=-1)
     618  {
     619    if (irqCause[group=(irq/32)] && (irqCause[group]&(bitmask=(1<<(irq % 32))))) {
     620      for (j=0; j<3; j++)
     621        BSP_irqMask_cache[j] &= (~ BSP_irq_prio_mask_tbl[j][irq]);
     622
     623      RTEMS_COMPILER_MEMORY_BARRIER();
     624      out_le32((volatile unsigned *)0xf1000c1c, BSP_irqMask_cache[0]);
     625      out_le32((volatile unsigned *)0xf1000c6c, BSP_irqMask_cache[1]);
     626      out_le32((volatile unsigned *)0xf100f10c, BSP_irqMask_cache[2]);
     627      in_le32((volatile unsigned *)0xf100f10c);
     628
     629#ifdef EDGE_TRIGGER
     630      if (irq > BSP_MICH_IRQ_MAX_OFFSET)
     631         out_le32(BSP_irqCause_reg[2], ~bitmask);/* Till Straumann: Ack the edge triggered GPP IRQ */
     632#endif
     633
     634      _MSR_GET(msr);
    506635      new_msr = msr | MSR_EE;
    507       _CPU_MSR_SET(new_msr);
     636      _MSR_SET(new_msr);
    508637      rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
    509       _CPU_MSR_SET(msr);
     638      _MSR_SET(msr);
     639     
     640      for (j=0; j<3; j++ ) BSP_irqMask_cache[j] = oldMask[j];
    510641      break;
    511642    }
    512643  }
    513   GT_MAINirqLO_cache=oldMask[0];
    514   outl(GT_MAINirqLO_cache, GT_CPU_INT_MASK_LO);
    515   GT_MAINirqHI_cache=oldMask[1];
    516   outl(GT_MAINirqHI_cache, GT_CPU_INT_MASK_HI);
     644
     645  out_le32((volatile unsigned *)0xf1000c1c, oldMask[0]);
     646  out_le32((volatile unsigned *)0xf1000c6c, oldMask[1]);
     647  out_le32((volatile unsigned *)0xf100f10c, oldMask[2]);
     648  in_le32((volatile unsigned *)0xf100f10c);
    517649}
    518650
     
    536668}
    537669
    538 void BSP_printIRQMask()
     670/* Only print part of the entries for now */
     671void BSP_printPicIsrTbl()
    539672{
    540673  int i;
    541674
    542   for (i=0; i< 20; i++)
    543     printk("IRQ%d : 0x%x %x \n", irqCAUSE[i], irqHIGH[i],irqLOW[i]);
    544 }
     675  printk("picIsrTable[12]={");
     676  for (i=0; i<12; i++)
     677    printk("%d,", picIsrTable[i]);
     678  printk("}\n");
     679
     680  printk("GPPIrqInTbl: 0x%x :\n", GPPIrqInTbl);
     681}
  • c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h

    r622e09b rb047186  
    1616 *  http://www.rtems.com/license/LICENSE.
    1717 *
    18  * Copyright 2004, Brookhaven National Laboratory and
     18 * Copyright 2004, 2005 Brookhaven National Laboratory and
    1919 *                 Shuchen Kate Feng <feng1@bnl.gov>
    2020 *
     
    2222 *    - Discovery GT64260 interrupt controller instead of 8259.
    2323 *    - Added support for software IRQ priority levels.
     24 *    - modified to optimize the IRQ latency and handling
    2425 *
    2526 *  $Id$
     
    2930#define LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H
    3031
     32/*#define BSP_SHARED_HANDLER_SUPPORT      1*/
    3133#include <rtems/irq.h>
    3234
     
    3537#ifndef ASM
    3638
    37 #define DynamicIrqTbl 1
     39#define OneTierIrqPrioTbl 1
    3840
    3941/*
     
    8486   */
    8587#define BSP_IRQ_NUMBER                  (BSP_MISC_IRQ_MAX_OFFSET + 1)
    86 #define BSP_MAIN_IRQ_NUMBER            (64)
     88#define BSP_MAIN_IRQ_NUMBER             (64)
     89#define BSP_PIC_IRQ_NUMBER              (96)
    8790#define BSP_LOWEST_OFFSET               (BSP_MICL_IRQ_LOWEST_OFFSET)
    8891#define BSP_MAX_OFFSET                  (BSP_MISC_IRQ_MAX_OFFSET)
     
    110113
    111114  /* on the MVME5500, these are the GT64260B external GPP0 interrupt */
     115#define BSP_PCI_IRQ_LOWEST_OFFSET       (BSP_GPP_IRQ_LOWEST_OFFSET)
    112116#define BSP_UART_COM2_IRQ               (BSP_GPP_IRQ_LOWEST_OFFSET)
    113117#define BSP_UART_COM1_IRQ               (BSP_GPP_IRQ_LOWEST_OFFSET)
     
    130134#define BSP_DECREMENTER         (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
    131135
    132 typedef unsigned int rtems_GTirq_masks;
    133 
    134 extern rtems_GTirq_masks GT_GPPirq_cache;
    135 extern rtems_GTirq_masks GT_MAINirqLO_cache, GT_MAINirqHI_cache;
    136 
    137 void BSP_enable_main_irq(unsigned irqNum);
    138 void BSP_disable_main_irq(unsigned irqNum);
    139 void BSP_enable_gpp_irq(unsigned irqNum);
    140 void BSP_disable_gpp_irq(unsigned irqNum);
    141  
    142136extern void BSP_rtems_irq_mng_init(unsigned cpuId);
    143 extern int gpp_int_error;
    144 #if  DynamicIrqTbl
    145 extern int MainIrqTblPtr;
    146 extern unsigned long long MainIrqInTbl;
    147 extern unsigned char GPPinMainIrqTbl[4];
    148 #endif
    149 extern unsigned int mainIrqTbl[64];
    150 extern unsigned int GPP7_0IrqTbl[8];
    151 extern unsigned int GPP15_8IrqTbl[8];
    152 extern unsigned int GPP23_16IrqTbl[8];
    153 extern unsigned int GPP31_24IrqTbl[8];
    154137
    155138#endif
    156 
    157139#endif
  • c/src/lib/libbsp/powerpc/mvme5500/irq/irq_init.c

    r622e09b rb047186  
    66 * CopyRight (C) 1999 valette@crf.canon.fr
    77 *
    8  * Special acknowledgement to Till Straumann <strauman@slac.stanford.edu>
    9  * for providing inputs to the IRQ optimization.
    10  *
    118 * Modified and added support for the MVME5500.
    12  * Copyright 2003, 2004, Brookhaven National Laboratory and
     9 * Copyright 2003, 2004, 2005, Brookhaven National Laboratory and
    1310 *                 Shuchen Kate Feng <feng1@bnl.gov>
    1411 *
    1512 * The license and distribution terms for this file may be
    1613 * found in the file LICENSE in this distribution or at
    17  * http://www.rtems.com/license/LICENSE.
     14 * http://www.rtems.com/license/LICENSE
    1815 *
    1916 */
     
    2320#include <bsp.h>
    2421#include <libcpu/raw_exception.h>  /* ASM_EXT_VECTOR, ASM_DEC_VECTOR ... */
     22/*#define  TRACE_IRQ_INIT*/
    2523
    2624extern unsigned int external_exception_vector_prolog_code_size[];
     
    2826extern unsigned int decrementer_exception_vector_prolog_code_size[];
    2927extern void decrementer_exception_vector_prolog_code();
    30 extern void GT_GPP_IntHandler0(), GT_GPP_IntHandler1();
    31 extern void GT_GPP_IntHandler2(), GT_GPP_IntHandler3();
    32 extern void BSP_GT64260INT_init();
    3328
    3429/*
     
    4843static rtems_irq_global_settings        initial_config;
    4944static rtems_irq_connect_data           defaultIrq = {
    50   /* vectorIdex,         hdl            , handle        , on            , off           , isOn */
    51   0,                     nop_func       , NULL          , nop_func      , nop_func      , not_connected
     45  /* vectorIdex,         hdl      , handle      , on            , off           , isOn */
     46  0,                     nop_func  , NULL       , nop_func      , nop_func      , not_connected
    5247};
    5348
    54 rtems_irq_prio BSPirqPrioTable[BSP_MAIN_IRQ_NUMBER]={
     49rtems_irq_prio BSPirqPrioTable[BSP_PIC_IRQ_NUMBER]={
    5550  /*
    5651   * This table is where the developers can change the levels of priority
    5752   * based on the need of their applications.
    5853   *
    59    * actual priorities for CPU MAIN interrupts 0-63:
     54   * actual priorities for CPU MAIN and GPP interrupts (0-95)
     55   *
    6056   *    0   means that only current interrupt is masked (lowest priority)
    61    *    255 means all other interrupts are masked
     57   *    255 is only used by bits 24, 25, 26 and 27 of the CPU high
     58   *        interrupt Mask: (e.g. GPP7_0, GPP15_8, GPP23_16, GPP31_24).
     59   *        The IRQs of those four bits are always enabled. When it's used,
     60   *        the IRQ number is never listed in the dynamic picIsrTable[96].
     61   *
     62   *        The priorities of GPP interrupts were decided by their own
     63   *        value set at  BSPirqPrioTable.
     64   *           
    6265   */
    6366  /* CPU Main cause low interrupt */
    6467  /* 0-15 */
    65   0, 0, 0, 0, 0, 0, 0, 0, 4/*Timer*/, 0, 0, 0, 0, 0, 0, 0,
     68  0, 0, 0, 0, 0, 0, 0, 0, 64/*Timer*/, 0, 0, 0, 0, 0, 0, 0,
    6669   /* 16-31 */
    6770  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    6871  /* CPU Main cause high interrupt */
    6972  /* 32-47 */
    70   1/*10/100MHZ*/, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
     73  2/*10/100MHz*/, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    7174  /* 48-63 */
    72   0, 0, 0, 0, 0, 0, 0, 0, 0/*serial*/, 3/*VME*/, 2/*1GHZ*/, 5/*WD*/, 0, 0, 0, 0
     75  0, 0, 0, 0, 0, 0, 0, 0,
     76  255 /*GPP0-7*/, 255/*GPP8-15*/, 255/*GPP16-23*/, 255/*GPP24-31*/, 0, 0, 0, 0,
     77  /* GPP interrupts */
     78  /* GPP0-7 */
     79  1/*serial*/,0, 0, 0, 0, 0, 0, 0,
     80  /* GPP8-15 */
     81  47/*PMC1A*/,46/*PMC1B*/,45/*PMC1C*/,44/*PMC1D*/,30/*VME0*/, 29/*VME1*/,3,1,
     82  /* GPP16-23 */
     83  37/*PMC2A*/,36/*PMC2B*/,35/*PMC2C*/,34/*PMC2D*/,23/*1GHz*/, 0,0,0, 
     84  /* GPP24-31 */
     85  7/*watchdog*/, 0,0,0,0,0,0,0
    7386};
    74 
    75 /* The mainIrqTbl[64] lists the enabled CPU main interrupt
    76  * numbers [0-63] starting from the highest priority one
    77  * to the lowest priority one.
    78  *
    79  * The highest priority interrupt is located at mainIrqTbl[0], and
    80  * the lowest priority interrupt is located at
    81  * mainIrqTbl[MainIrqTblPtr-1].
    82  */
    83 
    84 #if DynamicIrqTbl
    85 /* The mainIrqTbl[64] is updated dynamically based on the priority
    86  * levels set at BSPirqPrioTable[64], as the BSP_enable_main_irq() and
    87  * BSP_disable_main_irq() commands are invoked.
    88  *
    89  * Caveat: The eight GPP IRQs for each BSP_MAIN_GPPx_y_IRQ group are set
    90  * at the same main priority in the BSPirqPrioTable, while the
    91  * sub-priority levels for the eight GPP in each group  are sorted
    92  * statically by developers in the GPPx_yIrqTbl[8] from the highest
    93  * priority to the lowest one.
    94  */
    95 int MainIrqTblPtr=0;
    96 unsigned long long MainIrqInTbl=0;
    97 unsigned char GPPinMainIrqTbl[4]={0,0,0,0};
    98 /* BitNums for Main Interrupt Lo/High Cause, -1 means invalid bit */
    99 unsigned int mainIrqTbl[BSP_MAIN_IRQ_NUMBER]={ 
    100                                -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    101                                -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    102                                -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    103                                -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    104                                -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    105                                -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    106                                -1, -1, -1, -1};
    107 #else
    108 /* Pre-sorted for IRQ optimization, and prioritization
    109  * The interrupts sorted are :
    110 
    111  1. Watchdog timer      (GPP #25)
    112  2. Timers 0-1          (Main interrupt low cause, bit 8)
    113  3. VME interrupt       (GPP #12)
    114  4. 1 GHZ ethernet      (GPP #20)
    115  5. 10/100 MHZ ethernet (Main interrupt high cause, bit 0)
    116  6. COM1/COM2           (GPP #0)
    117 
    118 */
    119 /* BitNums for Main Interrupt Lo/High Cause, -1 means invalid bit */
    120 unsigned int mainIrqTbl[64]={ BSP_MAIN_GPP31_24_IRQ, /* 59:watchdog timer */
    121                                BSP_MAIN_TIMER0_1_IRQ, /* 8:Timers 0-1 */
    122                                BSP_MAIN_GPP15_8_IRQ,  /* 57:VME interrupt */
    123                                BSP_MAIN_GPP23_16_IRQ, /* 58: 1 GHZ ethernet */
    124                                BSP_MAIN_ETH0_IRQ,  /* 32:10/100 MHZ ethernet */
    125                                BSP_MAIN_GPP7_0_IRQ, /* 56:COM1/COM2 */
    126                                -1, -1, -1, -1,
    127                                -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    128                                -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    129                                -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    130                                -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    131                                -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    132                                -1, -1, -1, -1};
    133 #endif
    134 
    135 unsigned int GPP7_0IrqTbl[8]={0, /* COM1/COM2 */
    136                                -1, -1, -1, -1, -1, -1, -1};
    137 unsigned int GPP15_8IrqTbl[8]={ 4, 5, 6, 7,  /* VME interrupt 0-3 */
    138                                 0, 1, 2, 3   /* PMC1 INT A, B, C, D */};
    139 unsigned int GPP23_16IrqTbl[8]={4, /* 82544 1GHZ ethernet (20-16=4)*/
    140                                 0, 1, 2, 3, /* PMC2 INT A, B, C, D */
    141                                 -1, -1, -1};
    142 unsigned int GPP31_24IrqTbl[8]={1, /* watchdog timer (25-24=1) */
    143                                 -1, -1, -1, -1, -1, -1, -1};
    144 
    145 static int
    146 doit(unsigned intNum, rtems_irq_hdl handler, int (*p)(const rtems_irq_connect_data*))
    147 {
    148         rtems_irq_connect_data d={0};
    149         d.name = intNum;
    150         d.isOn = connected;
    151         d.hdl  = handler;
    152         return p(&d);
    153 }
    154 
    155 int BSP_GT64260_install_isr(unsigned intNum,rtems_irq_hdl handler)
    156 {
    157   return doit(intNum, handler, BSP_install_rtems_irq_handler);
    158 }
    15987
    16088/*
     
    175103  printk("Initializing the interrupt controller of the GT64260\n");
    176104#endif       
    177   BSP_GT64260INT_init();
    178105
    179106#ifdef TRACE_IRQ_INIT 
     
    187114   */
    188115  for (i = 0; i < BSP_IRQ_NUMBER; i++) {
    189       rtemsIrq[i]      = defaultIrq;
    190       rtemsIrq[i].name = i;
     116    rtemsIrq[i]      = defaultIrq;   
     117    rtemsIrq[i].name = i;
    191118  }
    192119
     
    210137      BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n");
    211138  }
     139#ifdef TRACE_IRQ_INIT 
     140  printk("Done setup irq mngt configuration\n");
     141#endif     
    212142
    213   /* Connect the GPP int handler to each of the associated main cause bits */
    214   BSP_GT64260_install_isr(BSP_MAIN_GPP7_0_IRQ, GT_GPP_IntHandler0); /* COM1 & COM2, .... */
    215   BSP_GT64260_install_isr(BSP_MAIN_GPP15_8_IRQ, GT_GPP_IntHandler1);
    216   BSP_GT64260_install_isr(BSP_MAIN_GPP23_16_IRQ, GT_GPP_IntHandler2);
    217   BSP_GT64260_install_isr(BSP_MAIN_GPP31_24_IRQ, GT_GPP_IntHandler3);
    218  
    219143  /*
    220144   * We must connect the raw irq handler for the two
  • c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c

    r622e09b rb047186  
    3535#include <string.h>
    3636
    37 /* #define PCI_DEBUG 1 */
    38 /* #define PCI_PRINT 1 */
     37#define PCI_DEBUG 0
     38#define PCI_PRINT 0
    3939
    4040/* allow for overriding these definitions */
     
    252252  unsigned int ulHeader;
    253253  unsigned int pcidata, ulClass, ulDeviceID;
    254 #if PCI_DEBUG
    255   unsigned short sdata;
    256   unsigned int data;
    257 #endif
    258 
    259254
    260255  pci_interface();
  • c/src/lib/libbsp/powerpc/mvme5500/pci/pci_interface.c

    r622e09b rb047186  
    11/* pci_interface.c
    22 *
    3  * Copyright 2004, Brookhaven National Laboratory and
    4  *                Shuchen Kate Feng <feng1@bnl.gov>
     3 * Copyright 2004, 2006, 2007 All rights reserved. (NDA items)
     4 *      Brookhaven National Laboratory and Shuchen Kate Feng <feng1@bnl.gov>
    55 *
    66 * The license and distribution terms for this file may be
    77 * found in the file LICENSE in this distribution.
     8 *
     9 * 8/17/2006 : S. Kate Feng
     10 *             uses in_le32()/out_le32(), instead of inl()/outl() so that
     11 *             it is easier to be ported.
    812 *
    913 */
     
    1620#include <bsp/gtpcireg.h>
    1721
     22#define REG32_READ(reg) in_le32((volatile unsigned int *)(GT64260_REG_BASE+reg))
     23#define REG32_WRITE(data, reg) out_le32((volatile unsigned int *)(GT64260_REG_BASE+reg), data)
     24
    1825#define PCI_DEBUG     0
    1926
     
    2229 *
    2330 * Some PCI devices require Synchronization Barriers or PCI ordering
    24  * for synchronization.  For example, the VME-OMS58 motor controller we
    25  * used at NSLS requires either enhanced CPU Synchronization Barrier
    26  * or PCI-ordering (only one mechanism allowed. See section 11.1.2).
     31 * for synchronization (only one mechanism allowed. See section 11.1.2).
    2732 * To use the former mechanism(default), one needs to call
    2833 * CPU0_PciEnhanceSync() or CPU1_PciEnhanceSync() to perform software
     
    4045 *
    4146 */
    42 #define PCI_ORDERING
     47/*#define PCI_ORDERING*/
     48
     49#define EN_SYN_BAR   /* take MOTLoad default for enhanced SYN Barrier mode */
    4350
    4451/*#define PCI_DEADLOCK*/
    45 
    46 /*  So far, I do not see the need to disable the address pipelining.
    47 #define DIS_ADDR_PIPELINE*/
    4852
    4953#ifdef PCI_ORDERING
     
    8791void pci_interface()
    8892{
    89   unsigned int data;
    90 
    91 #if  (defined(PCI_ORDERING)||defined(DIS_ADDR_PIPELINE))
    92   data = inl(0); /* needed : read to flush */
    93   /* MOTLOad default disables Configuration and I/O Read Sync Barrier
    94    * which is needed for enhanced CPU sync. barrier  */
    95 #ifdef PCI_ORDERING
    96   /* enable Configuration Read Sync Barrier and IO read Sync Barrier*/
    97   data &= ~ConfIOSBDis;
    98 #endif
    99 #ifdef DIS_ADDR_PIPELINE
    100   data &= ~ADDR_PIPELINE;
    101 
    102 #if PCI_DEBUG
    103   printk("data %x\n", data);
    104 #endif
    105 #endif
    106   outl(data, 0);
    107   /* read polling of the register until the new data is being read */
    108   while ( inl(0)!=data);
    109 #endif
    11093
    11194#ifdef PCI_DEADLOCK
    112   outl(0x07fff600, CNT_SYNC_REG);
     95  REG32_WRITE(0x07fff600, CNT_SYNC_REG);
    11396#endif
    11497#ifdef PCI_ORDERING
    115   outl(0xc0060002, DLOCK_ORDER_REG);
    116   outl(0x07fff600, CNT_SYNC_REG);
    117 #else
    118   outl(inl(PCI_CMD_CNTL)|PCI_COMMAND_SB_DIS, PCI_CMD_CNTL);
     98  /* Let's leave this to be MOTLOad deafult : 0x80070000
     99     REG32_WRITE(0xc0070000, DLOCK_ORDER_REG);*/
     100  /* Leave the CNT_SYNC_REG b/c MOTload default had the SyncBarMode set to 1 */
    119101#endif
    120102
    121103  /* asserts SERR upon various detection */
    122   outl(0x3fffff, 0xc28);
     104  REG32_WRITE(0x3fffff, 0xc28);
    123105
    124106  pciAccessInit();
     
    134116     * one PCI access control because the top = 0x1ff
    135117     */
    136     data = inl(GT_SCS0_Low_Decode) & 0xfff;
     118    data = REG32_READ(GT_SCS0_Low_Decode) & 0xfff;
    137119    data |= PCI_ACCCTLBASEL_VALUE;
    138120    data &= ~0x300000;
    139     outl(data, PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80));
     121    REG32_WRITE(data, PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80));
    140122#if PCI_DEBUG
    141     printk("PCI%d_ACCESS_CNTL_BASE0_LOW 0x%x\n",PciLocal,inl(PCI_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)));
     123    printk("PCI%d_ACCESS_CNTL_BASE0_LOW 0x%x\n",PciLocal,REG32_READ(PCI_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)));
    142124#endif
     125
    143126  }
    144127}
     
    153136void CPU0_PciEnhanceSync(unsigned int syncVal)
    154137{
    155   outl(syncVal,CPU0_SYNC_TRIGGER);
    156   while (inl(CPU0_SYNC_VIRTUAL));
     138  REG32_WRITE(syncVal,CPU0_SYNC_TRIGGER);
     139  while (REG32_READ(CPU0_SYNC_VIRTUAL));
    157140}
    158141
    159142void CPU1_PciEnhanceSync(unsigned int syncVal)
    160143{
    161   outl(syncVal,CPU1_SYNC_TRIGGER);
    162   while (inl(CPU1_SYNC_VIRTUAL));
     144  REG32_WRITE(syncVal,CPU1_SYNC_TRIGGER);
     145  while (REG32_READ(CPU1_SYNC_VIRTUAL));
    163146}
    164147
  • c/src/lib/libbsp/powerpc/mvme5500/pci/pcifinddevice.c

    r622e09b rb047186  
    11/* pcifinddevice.c
    22 *
     3 * Copyright 2001,  Till Straumann <strauman@slac.stanford.edu>
    34 *
    45 * find a particular PCI device
    56 * (we assume, the firmware configured the PCI bus[es] for us)
    67 *
    7  */
    8 
    9 /*
    10  * Authorship
    11  * ----------
    12  * This software was created by
    13  *     Till Straumann <strauman@slac.stanford.edu>, 2001,
    14  *         Stanford Linear Accelerator Center, Stanford University.
    158 *
    16  * Acknowledgement of sponsorship
    17  * ------------------------------
    18  * This software was produced by
    19  *     the Stanford Linear Accelerator Center, Stanford University,
    20  *         under Contract DE-AC03-76SFO0515 with the Department of Energy.
    21  *
    22  * Government disclaimer of liability
    23  * ----------------------------------
    24  * Neither the United States nor the United States Department of Energy,
    25  * nor any of their employees, makes any warranty, express or implied, or
    26  * assumes any legal liability or responsibility for the accuracy,
    27  * completeness, or usefulness of any data, apparatus, product, or process
    28  * disclosed, or represents that its use would not infringe privately owned
    29  * rights.
    30  *
    31  * Stanford disclaimer of liability
    32  * --------------------------------
    33  * Stanford University makes no representations or warranties, express or
    34  * implied, nor assumes any liability for the use of this software.
    35  *
    36  * Stanford disclaimer of copyright
    37  * --------------------------------
    38  * Stanford University, owner of the copyright, hereby disclaims its
    39  * copyright and all other rights in this software.  Hence, anyone may
    40  * freely use it for any purpose without restriction. 
    41  *
    42  * Maintenance of notices
    43  * ----------------------
    44  * In the interest of clarity regarding the origin and status of this
    45  * SLAC software, this and all the preceding Stanford University notices
    46  * are to remain affixed to any copy or derivative of this software made
    47  * or distributed by the recipient and are to be affixed to any copy of
    48  * software made or distributed by the recipient that contains a copy or
    49  * derivative of this software.
    50  *
    51  * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
    52  */
    53 /*
    549 * Kate Feng <feng1@bnl.gov>, modified it to support the mvme5500 board.
    5510 *
  • c/src/lib/libbsp/powerpc/mvme5500/preinstall.am

    r622e09b rb047186  
    2020
    2121$(PROJECT_LIB)/$(dirstamp):
    22         @$(MKDIR_P) $(PROJECT_LIB)
     22        @$(mkdir_p) $(PROJECT_LIB)
    2323        @: > $(PROJECT_LIB)/$(dirstamp)
    2424PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
    2525
    2626$(PROJECT_INCLUDE)/$(dirstamp):
    27         @$(MKDIR_P) $(PROJECT_INCLUDE)
     27        @$(mkdir_p) $(PROJECT_INCLUDE)
    2828        @: > $(PROJECT_INCLUDE)/$(dirstamp)
    2929PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
     
    5050
    5151$(PROJECT_INCLUDE)/bsp/$(dirstamp):
    52         @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
     52        @$(mkdir_p) $(PROJECT_INCLUDE)/bsp
    5353        @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    5454PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     
    6262PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart.h
    6363
    64 $(PROJECT_INCLUDE)/bsp/vme_am_defs.h: ../../shared/vmeUniverse/vme_am_defs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    65         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vme_am_defs.h
    66 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vme_am_defs.h
     64$(PROJECT_INCLUDE)/bsp/consoleIo.h: ../../powerpc/shared/console/consoleIo.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     65        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/consoleIo.h
     66PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/consoleIo.h
    6767
    6868$(PROJECT_INCLUDE)/bsp/gtpcireg.h: pci/gtpcireg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     
    107107
    108108if HAS_NETWORKING
    109 $(PROJECT_INCLUDE)/bsp/GT64260eth.h: network/GT64260eth.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     109$(PROJECT_INCLUDE)/bsp/GT64260eth.h: network/if_100MHz/GT64260eth.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    110110        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/GT64260eth.h
    111111PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260eth.h
    112112
    113 $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h: network/GT64260ethreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     113$(PROJECT_INCLUDE)/bsp/GT64260ethreg.h: network/if_100MHz/GT64260ethreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    114114        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h
    115115PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h
     116$(PROJECT_INCLUDE)/bsp/if_wmreg.h: network/if_1GHz/if_wmreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     117        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/if_wmreg.h
     118PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/if_wmreg.h
     119
     120$(PROJECT_INCLUDE)/bsp/pcireg.h: network/if_1GHz/pcireg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     121        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pcireg.h
     122PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pcireg.h
    116123endif
     124
    117125$(PROJECT_INCLUDE)/bsp/VME.h: ../../shared/vmeUniverse/VME.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    118126        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VME.h
     
    126134        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vmeUniverse.h
    127135PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vmeUniverse.h
     136
     137$(PROJECT_INCLUDE)/bsp/vme_am_defs.h: ../../shared/vmeUniverse/vme_am_defs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     138        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vme_am_defs.h
     139PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vme_am_defs.h
    128140
    129141$(PROJECT_INCLUDE)/bsp/vmeUniverseDMA.h: ../../shared/vmeUniverse/vmeUniverseDMA.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
  • c/src/lib/libbsp/powerpc/mvme5500/start/preload.S

    r622e09b rb047186  
    11/*
    2  * Mini-loader for the SVGM and MVME5500 BSP.
     2 * Mini-loader for the SVGM BSP.
    33 *
    44 * $Id$
    55 *
    6  * Copyright (C) 2003, 2004
    76 * Author: Till Straumann, 10/2001 <strauman@slac.stanford.edu>
    87 *
     
    1211 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
    1312 *
    14  *
    15  * The SVGM firmware is unable to load the RTEMS image below
    16  * 0x2000 (I believe their stack is growing below 0x1000) ?
     13 * The SMON firmware is unable to load the RTEMS image below
     14 * 0x2000 (I believe their stack is growing below 0x1000).
    1715 *
    1816 * The code provided by this file is responsible for the performing
     
    2422 *          nor the final BSS segment (rtems clears BSS
    2523 *          before saving the command line).
    26  *  2) Initialize and setup the memory controller to prepare the
    27  *     SDRAM before moving the image to it.
    28  *  3) Move the entire image (including this very file) to
     24 *  2) Move the entire image (including this very file) to
    2925 *     its final location starting at 0x0000.
    3026 *     It is important to note that _NO_STACK_ is available
    3127 *     during this step. Also, there is probably no return to
    32  *     Monitor because relocating RTEMS will destroy vital Monitor
     28 *     SMON because relocating RTEMS will destroy vital SMON
    3329 *     data (such as its stack).
    3430 *  3) Flush the cache to make sure the relocated image is actually
     
    4541 *
    4642 *  Calling convention:
    47  *     R1: Monitor SP
     43 *     R1: SMON SP
    4844 *     R3: command line string start
    4945 *     R4: command line string end + 1
    50  *     R5: where Monitor put the image
     46 *     R5: where SMON put the image
    5147 *         if R5 is 0, the preloader will use its entry point
    5248 *         as the image starting address.
     
    7571 */
    7672#if 0
    77 /* TODO: I dont know where the appropriate CPU model is to be defined
    78  *       when including this to get PPC_CACHE_ALIGNMENT I get an error...
    79  */
    80 #include <rtems/score/ppc.h>
     73#include <rtems/score/powerpc.h>
    8174#else
    8275#ifndef PPC_CACHE_ALIGNMENT
     
    9184 * if DESTINATION_ADDR is not 0
    9285 */
    93 #define KERNELBASE              0x0
    94 #define INITIAL_STACK           0x78                    /* 8-byte aligned */
     86#define KERNELBASE                      0x0
     87#define INITIAL_STACK           0x78                                    /* 8-byte aligned */
    9588#define CACHE_LINE_SIZE         PPC_CACHE_ALIGNMENT     /* autodetect doesn't work, see below */
    9689#define ASSUME_RTEMS_INSTALLS_VECTORS                           /* assume we need not load vectors */
     
    109102        bl      here
    110103here:
    111         /* MOTLoad had MSR_EE turned on.  Disable it.*/
    112         mfmsr   r0
    113         xori    r0, r0, MSR_EE
    114         mtmsr   r0               
     104        xor             r0,r0,r0
     105        mtmsr   r0      /* clear MSR to known state */
    115106        mflr    r5
    116107        addi    r5,r5,-(here-preload)
     
    148139        cmpw    r16, r18
    149140        bge             ishighenough
    150         mr              r16,r18                 /* __rtems_end is higher than
    151                                                  * the image end
    152                                                  * (without bss)
    153                                                  */
     141        mr              r16,r18                 /* __rtems_end is higher than the image end
     142                                                         * (without bss)
     143                                                         */
    154144ishighenough:
    155145        cmpw    r16, r3             /* destination start > current string start ? */
     
    166156
    167157#ifndef CACHE_LINE_SIZE
    168         /* Oh well, Monitor firmware has inhibited the cache, so this
     158        /* Oh well, SMON has inhibited the cache, so this
    169159         * nice routine doesn't work...
    170160         */
     
    188178#endif
    189179       
    190         lis             r3,preload@h
     180    lis         r3,preload@h
    191181        ori             r3,r3,preload@l
    192182        mr              r4,r5                   /* from-addr */
     
    219209     * we are ready to start...
    220210         */
    221         /* R6: start of command line */
    222         /* R7: end of command line +1 */
    223        
     211
    224212        /* setup initial stack for rtems early boot */
    225         lis             r1, INITIAL_STACK
     213        li              r1,INITIAL_STACK
    226214        /* disable the MMU and fire up rtems */
    227215        mfmsr   r0
    228         ori     r0,r0,MSR_IR|MSR_DR|MSR_IP
     216        ori     r0,r0,MSR_IR|MSR_DR|MSR_IP|MSR_ME
    229217        xori    r0,r0,MSR_IR|MSR_DR
    230218        mtsrr1  r0
     
    232220        ori             r0,r0,__rtems_entry_point@l
    233221        mtsrr0  r0
     222        /* R6: start of command line */
     223        /* R7: end of command line +1 */
    234224        rfi
    235225
     
    239229     * the caches for the destination memory
    240230     * region. R16 provides the cache line size.
    241     * DESTROYS: R0, R17, R18, CTR, CR
     231        * DESTROYS: R0, R17, R18, CTR, CR
    242232     */
    243233domove:
     
    259249#endif
    260250#if defined(CACHE_LINE_SIZE) && CACHE_LINE_SIZE > 0
    261         add     r17,r3,r5               /* target end pointer */
     251        add             r17,r3,r5               /* target end pointer */
    262252        subi    r0,r16,1
    263         add     r17,r17,r0
     253        add             r17,r17,r0
    264254        andc    r17,r17,r0              /* cache aligned target end pointer */
    265         mr      r18,r3
     255        mr              r18,r3
    2662562:      cmpw    r18,r17
    267257        dcbst   0,r18                   /* write out data cache line */
    268258        icbi    0,r18                   /* invalidate corresponding i-cache line */
    269         add     r18,r18,r16
    270         blt     2b
    271         sync                           /* make sure data is written back */
    272         isync                          /* invalidate possibly preloaded instructions */
     259        add             r18,r18,r16
     260        blt             2b
     261        sync                                    /* make sure data is written back */
     262        isync                                   /* invalidate possibly preloaded instructions */
    273263#endif
    2742643:
  • c/src/lib/libbsp/powerpc/mvme5500/startup/bspclean.c

    r622e09b rb047186  
    88{
    99#if AUTO_BOOT
     10  /* Till Straumann <strauman@slac.stanford.edu> for SVGM */
    1011  void rtemsReboot();
    1112
    1213  rtemsReboot();
    1314#else
     15  /* Kate Feng <feng1@bnl.gov> for the MVME5500 */
    1416  printk("\nPrinting a stack trace for your convenience :-)\n");
    1517  CPU_print_stack();
  • c/src/lib/libbsp/powerpc/mvme5500/startup/bspstart.c

    r622e09b rb047186  
    1515 *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
    1616 *
    17  *  Modified to support the Synergy VGM & Motorola PowerPC boards.
    18  *  Many thanks to Till Straumann for providing assistance to port the
    19  *  BSP_pgtbl_xxx().
    20  *  (C) by Till Straumann, <strauman@slac.stanford.edu>, 2002, 2004
    21  *
    22  *  Modified to support the MVME5500 board
    23  *  (C) by S. Kate Feng <feng1@bnl.gov>, 2003, 2004
    24  *
     17 *  Modified to support the Synergy VGM & Motorola PowerPC boards
     18 *  (C) by Till Straumann, <strauman@slac.stanford.edu>, 2002, 2004, 2005
     19 *
     20 *  Modified to support the MVME5500 board.
     21 *  Also, the settings of L1, L2, and L3 caches is not necessary here.
     22 *  (C) by Brookhaven National Lab., S. Kate Feng <feng1@bnl.gov>, 2003, 2004, 2005
     23 * 
    2524 *  $Id$
    2625 */
     
    6362#include <rtems/score/wkspace.h>
    6463
    65 uint32_t
    66 _bsp_sbrk_init(uint32_t heap_start, uint32_t *heap_size_p);
    67 
    68 /* provide access to the command line parameters */
    69 char *BSP_commandline_string = 0;
    70 
    7164BSP_output_char_function_type BSP_output_char = BSP_output_char_via_serial;
    7265
    7366extern void _return_to_ppcbug();
    7467extern unsigned long __rtems_end[];
    75 extern void L1_caches_enables();
    7668extern unsigned get_L1CR(), get_L2CR(), get_L3CR();
    77 extern unsigned set_L2CR(unsigned);
    7869extern void bsp_cleanup(void);
    7970extern Triv121PgTbl BSP_pgtbl_setup();
     
    113104 * PCI Bus Frequency
    114105 */
     106/*
     107 * Start of the heap
     108 */
     109unsigned int BSP_heap_start;
     110
    115111unsigned int BSP_bus_frequency;
    116112/*
     
    124120unsigned char ConfVPD_buff[200];
    125121
     122#define CMDLINE_BUF_SIZE        2048
     123
     124static char cmdline_buf[CMDLINE_BUF_SIZE];
     125char *BSP_commandline_string = cmdline_buf;
     126
    126127/*
    127128 * system init stack and soft ir stack size
     
    129130#define INIT_STACK_SIZE 0x1000
    130131#define INTR_STACK_SIZE CONFIGURE_INTERRUPT_STACK_MEMORY
    131 
    132 /* calculate the heap start */
    133 static unsigned long
    134 heapStart(void)
    135 {
    136 unsigned long rval;
    137     rval = ((uint32_t) __rtems_end) +INIT_STACK_SIZE + INTR_STACK_SIZE;
    138     if (rval & (CPU_ALIGNMENT-1))
    139         rval = (rval + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
    140         return rval;
    141 }
    142132
    143133void BSP_panic(char *s)
     
    174164extern void bsp_libc_init( void *, uint32_t, int );
    175165
    176 /*
    177  *  Function:   bsp_pretasking_hook
    178  *  Created:    95/03/10
    179  *
    180  *  Description:
    181  *      BSP pretasking hook.  Called just before drivers are initialized.
    182  *      Used to setup libc and install any BSP extensions.
    183  *
    184  *  NOTES:
    185  *      Must not use libc (to do io) from here, since drivers are
    186  *      not yet initialized.
    187  *
    188  */
    189 
    190 void bsp_pretasking_hook(void)
    191 {
    192     uint32_t        heap_start=heapStart();   
    193     uint32_t        heap_size,heap_sbrk_spared;
    194     extern uint32_t _bsp_sbrk_init(uint32_t, uint32_t*);
    195 
    196     heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size;
    197 
    198     heap_sbrk_spared=_bsp_sbrk_init(heap_start, &heap_size);
    199 
    200 #ifdef SHOW_MORE_INIT_SETTINGS
    201         printk(" HEAP start %x  size %x (%x bytes spared for sbrk)\n", heap_start, heap_size, heap_sbrk_spared);
    202 #endif   
    203 
    204     bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared);
    205 
    206 #ifdef RTEMS_DEBUG
    207     rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
    208 #endif
    209 }
     166extern void bsp_pretasking_hook(void);
    210167
    211168void zero_bss()
     
    258215{
    259216int             i=cmdline_end-cmdline_start;
    260 CmdLine future_heap=(CmdLine)heapStart();
    261 
    262         /* get the string out of the stack area into the future heap region;
    263          * assume there's enough memory...
    264          */
    265         memmove(future_heap->buf,cmdline_start,i);
    266         /* make sure there's an end of string marker */
    267         future_heap->buf[i++]=0;
    268         future_heap->size=i;
    269 }
    270 
    271 
    272 /* Configure and enable the L3CR */
    273 void config_enable_L3CR(unsigned l3cr)
    274 {
    275         unsigned x;
    276 
    277         /* By The Book (numbered steps from section 3.7.3.1 of MPC7450UM) */                           
    278         /*
    279          * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and
    280          *    L3CLKEN.  (also mask off reserved bits in case they were included
    281          *    in L3CR_CONFIG)
    282          */
    283         l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_LOCK_745x|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED);
    284         mtspr(L3CR, l3cr);
    285 
    286         /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */
    287         l3cr |= 0x04000000;
    288         mtspr(L3CR, l3cr);
    289 
    290         /* 3: Set L3CLKEN to 1*/
    291         l3cr |= L3CR_L3CLKEN;
    292         mtspr(L3CR, l3cr);
    293 
    294         /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */
    295         __asm __volatile("dssall;sync");
    296         /* L3 cache is already disabled, no need to clear L3E */
    297         mtspr(L3CR, l3cr|L3CR_L3I);
    298 
    299         do {
    300                x = mfspr(L3CR);
    301         } while (x & L3CR_L3I);
    302        
    303         /* 6: Clear L3CLKEN to 0 */
    304         l3cr &= ~L3CR_L3CLKEN;
    305         mtspr(L3CR, l3cr);
    306 
    307         /* 7: Perform a 'sync' and wait at least 100 CPU cycles */
    308         __asm __volatile("sync");
    309         rtems_bsp_delay_in_bus_cycles(100);
    310 
    311         /* 8: Set L3E and L3CLKEN */
    312         l3cr |= (L3CR_L3E|L3CR_L3CLKEN);
    313         mtspr(L3CR, l3cr);
    314 
    315         /* 9: Perform a 'sync' and wait at least 100 CPU cycles */
    316         __asm __volatile("sync");
    317 
    318         rtems_bsp_delay_in_bus_cycles(100);
     217        if ( i >= CMDLINE_BUF_SIZE )
     218                i = CMDLINE_BUF_SIZE-1;
     219        else if ( i < 0 )
     220                i = 0;
     221        memmove(cmdline_buf, cmdline_start, i);
     222        cmdline_buf[i]=0;
    319223}
    320224
     
    347251  ppc_cpu_revision_t myCpuRevision;
    348252  Triv121PgTbl  pt=0;
     253
     254  /* Till Straumann: 4/2005
     255   * Need to map the system registers early, so we can printk...
     256   * (otherwise we silently die)
     257   */
     258  /*
     259   * Kate Feng : PCI 0 domain memory space, want to leave room for the VME window
     260   */
     261  setdbat(2, PCI0_MEM_BASE, PCI0_MEM_BASE, 0x10000000, IO_PAGE);
     262
     263  /* Till Straumann: 2004
     264   * map the PCI 0, 1 Domain I/O space, GT64260B registers
     265   * and the reserved area so that the size is the power of 2.
     266   *
     267   */
     268  setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x2000000, IO_PAGE);
     269
     270
    349271  /*
    350272   * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
     
    354276  myCpuRevision = get_ppc_cpu_revision();
    355277
    356   /*
    357    * enables L1 Cache. Note that the L1_caches_enables() codes checks for
    358    * relevant CPU type so that the reason why there is no use of myCpu...
    359    *
    360    * MOTLoad default is good. Otherwise, one would have to disable L2, L3
    361    * first before settting L1.  Then L1->L2->L3.
    362    *
    363    L1_caches_enables();*/
    364  
    365278#ifdef SHOW_LCR1_REGISTER
    366279  l1cr = get_L1CR();
     
    391304   * some settings below...
    392305   */
    393   intrStack = ((uint32_t) __rtems_end) +
    394           INIT_STACK_SIZE + INTR_STACK_SIZE - PPC_MINIMUM_STACK_FRAME_SIZE;
     306  BSP_heap_start = ((uint32_t) __rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE;
     307  intrStack = BSP_heap_start - PPC_MINIMUM_STACK_FRAME_SIZE;
    395308
    396309  /* make sure it's properly aligned */
     
    415328   * More PCI1 memory mapping to be done after BSP_pgtbl_activate.
    416329   */
    417   /*
    418    * PCI 0 domain memory space, want to leave room for the VME window
    419    */
    420   setdbat(2, PCI0_MEM_BASE, PCI0_MEM_BASE, 0x10000000, IO_PAGE);
    421 
    422   /* map the PCI 0, 1 Domain I/O space, GT64260B registers
    423    * and the reserved area so that the size is the power of 2.
    424    */
    425   setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x2000000, IO_PAGE);
    426 
    427330  printk("-----------------------------------------\n");
    428331  printk("Welcome to %s on MVME5500-0163\n", _RTEMS_version );
     
    486389  Cpu_table.clicks_per_usec      = BSP_bus_frequency/(BSP_time_base_divisor * 1000);
    487390  Cpu_table.exceptions_in_RAM    = TRUE;
    488   _CPU_Table                     = Cpu_table;/* <skf> for rtems_bsp_delay() */
     391  _CPU_Table                     = Cpu_table;/* S. Kate Feng <feng1@bnl.gov>, for rtems_bsp_delay() */
    489392
    490393  printk("BSP_Configuration.work_space_size = %x\n", BSP_Configuration.work_space_size);
     
    504407   BSP_rtems_irq_mng_init(0);
    505408
    506   /*
    507    * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for
    508    * relevant CPU type (mpc750)...
    509    *
    510    * It also takes care of flushing the cache under certain conditions:
    511    *   current    going to (E==enable, I==invalidate)
    512    *     E           E | I      -> __NOT_FLUSHED_, invalidated, stays E
    513    *     E               I      -> flush & disable, invalidate
    514    *     E           E          -> nothing, stays E
    515    *     0           E | I      -> not flushed, invalidated, enabled
    516    *     0             | I      -> not flushed, invalidated, stays off
    517    *     0           E      -> not flushed, _NO_INVALIDATE, enabled
    518    *
    519    * The first and the last combinations are potentially dangerous!
    520    *
    521    * NOTE: we assume the essential cache parameters (speed, size etc.)
    522    *       have been set correctly by the firmware!
    523    *
    524    */
    525409#ifdef SHOW_LCR2_REGISTER
    526410  l2cr = get_L2CR();
    527411  printk("Initial L2CR value = %x\n", l2cr);
    528412#endif 
    529 #if 0
    530   /* Again, MOTload setup seems to be fine. Otherwise, one would
    531    * have to disable the L3 cahce, then R2 ->R3
    532    */
    533   if ( -1 != (int)l2cr ) {
    534         /* -1 would mean that this machine doesn't support L2 */
    535 
    536         l2cr &= ~( L2CR_LOCK_745x); /* clear 'data only' and 'instruction only' */
    537         l2cr |= L2CR_L3OH0;    /* L3 output hold 0 should be set */
    538         if ( ! (l2cr & L2CR_L2E) ) {
    539             /* we are going to enable the L2 - hence we
    540              * MUST invalidate it first; however, if
    541              * it was enabled already, we MUST NOT
    542              * invalidate it!!
    543              */
    544              l2cr |= L2CR_L2E | L2CR_L2I;
    545              l2cr=set_L2CR(l2cr);
    546         }
    547         l2cr=set_L2CR(l2cr);
    548   }
    549 #endif
    550413
    551414#ifdef SHOW_LCR3_REGISTER
     
    555418#endif 
    556419
    557 #if 0
    558   /* Again, use the MOTLoad default for L3CR again */
    559   if ( -1 != (int)l3cr ) {
    560         /* -1 would mean that this machine doesn't support L3 */
    561         /* BSD : %2 , SDRAM late wirte
    562            l3cr |= L3SIZ_2M|L3CLK_20|L3RT_PIPELINE_LATE; */
    563         /* MOTLOad :0xDF826000-> %5, 4 clocks sample point,3 p-clocks SP */
    564         l3cr |= L3CR_L3PE| L3SIZ_2M|L3CLK_50|L3CKSP_4|L3PSP_3;
    565 
    566         /* TOCHECK MOTload had L2 cache enabled, try to set nothing first */
    567         if ( !(l3cr & L3CR_L3E)) {
    568            l3cr |= L3CR_L3E | L3CR_L3I;
    569            config_enable_L3CR(l3cr);
    570         }
    571   }
    572 #endif
    573420
    574421  /* Activate the page table mappings only after
     
    604451   */
    605452  _BSP_clear_hostbridge_errors(0, 1 /*quiet*/);
    606 
    607   /*
    608    * Initialize VME bridge - needs working PCI
    609    * and IRQ subsystems...
    610    */
    611 #ifdef SHOW_MORE_INIT_SETTINGS
    612   printk("Going to initialize VME bridge\n");
    613 #endif
    614   /* VME initialization is in a separate file so apps which don't use
    615    * VME or want a different configuration may link against a customized
    616    * routine.
    617    */
    618   BSP_vme_config();
    619453
    620454  /* Read Configuration Vital Product Data (VPD) */
  • c/src/lib/libbsp/powerpc/mvme5500/startup/pgtbl_activate.c

    r622e09b rb047186  
    1010 */
    1111
    12 /*
    13  * Authorship
    14  * ----------
    15  * This software was created by
    16  *     Till Straumann <strauman@slac.stanford.edu>, 4/2002,
    17  *         Stanford Linear Accelerator Center, Stanford University.
    18  *
    19  * Acknowledgement of sponsorship
    20  * ------------------------------
    21  * This software was produced by
    22  *     the Stanford Linear Accelerator Center, Stanford University,
    23  *         under Contract DE-AC03-76SFO0515 with the Department of Energy.
    24  *
    25  * Government disclaimer of liability
    26  * ----------------------------------
    27  * Neither the United States nor the United States Department of Energy,
    28  * nor any of their employees, makes any warranty, express or implied, or
    29  * assumes any legal liability or responsibility for the accuracy,
    30  * completeness, or usefulness of any data, apparatus, product, or process
    31  * disclosed, or represents that its use would not infringe privately owned
    32  * rights.
    33  *
    34  * Stanford disclaimer of liability
    35  * --------------------------------
    36  * Stanford University makes no representations or warranties, express or
    37  * implied, nor assumes any liability for the use of this software.
    38  *
    39  * Stanford disclaimer of copyright
    40  * --------------------------------
    41  * Stanford University, owner of the copyright, hereby disclaims its
    42  * copyright and all other rights in this software.  Hence, anyone may
    43  * freely use it for any purpose without restriction. 
    44  *
    45  * Maintenance of notices
    46  * ----------------------
    47  * In the interest of clarity regarding the origin and status of this
    48  * SLAC software, this and all the preceding Stanford University notices
    49  * are to remain affixed to any copy or derivative of this software made
    50  * or distributed by the recipient and are to be affixed to any copy of
    51  * software made or distributed by the recipient that contains a copy or
    52  * derivative of this software.
    53  *
    54  * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
    55  */
    56 
    57 /* Kate Feng <feng1@bnl.gov> ported it to MVME5500, 4/2004
     12/* Author: Till Straumann, <strauman@slac.stanford.edu>, 4/2002
     13 * Kate Feng <feng1@bnl.gov> ported it to MVME5500, 4/2004
    5814 */
    5915
  • c/src/lib/libbsp/powerpc/mvme5500/startup/reboot.c

    r622e09b rb047186  
    88{
    99
    10   printk("\nPrinting a stack trace for your convenience :-)\n");
     10  printk("Printing a stack trace for your convenience :-)\n");
    1111  CPU_print_stack();
    1212
    1313  printk("RTEMS terminated; Rebooting ...\n");
    14   /* Mvme5500 board reset  <skf> */
     14  /* Mvme5500 board reset : 2004 S. Kate Feng <feng1@bnl.gov> */
    1515  out_8((volatile unsigned char*) (GT64260_DEV1_BASE +2), 0x80);
    1616}
Note: See TracChangeset for help on using the changeset viewer.