Index: c/src/lib/libcpu/arm/at91rm9200/ChangeLog
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/ChangeLog	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/ChangeLog	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,10 @@
+2004-07-15	Jay Monkman
+
+	* ChangeLog, Makefile.am, clock/.cvsignore, clock/clock.c,
+	dbgu/.cvsignore, dbgu/dbgu.c, include/at91rm9200.h,
+	include/at91rm9200_dbgu.h, include/at91rm9200_emac.h,
+	include/at91rm9200_gpio.h, include/at91rm9200_mem.h,
+	include/at91rm9200_pmc.h, include/bits.h, irq/.cvsignore,
+	irq/bsp_irq_asm.S, irq/bsp_irq_init.c, irq/irq.c, irq/irq.h,
+	pmc/pmc.c, timer/.cvsignore, timer/timer.c: New files.
+
Index: c/src/lib/libcpu/arm/at91rm9200/Makefile.am
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/Makefile.am	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/Makefile.am	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,162 @@
+##
+## $Id$
+##
+
+CLEANFILES =
+EXTRA_DIST =
+EXTRA_PROGRAMS =
+noinst_DATA =
+
+include $(top_srcdir)/../../../automake/compile.am
+
+if at91rm9200
+include_at91rm9200dir = $(includedir)/at91rm9200
+include_libcpudir = $(includedir)/libcpu
+include_HEADERS =
+include_HEADERS += include/at91rm9200.h include/at91rm9200_dbgu.h \
+		   include/at91rm9200_emac.h include/at91rm9200_gpio.h \
+		   include/at91rm9200_mem.h include/at91rm9200_pmc.h \
+		   include/bits.h
+
+## clock
+EXTRA_PROGRAMS += clock.rel
+CLEANFILES += clock.rel
+clock_rel_SOURCES = clock/clock.c
+clock_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_OPTIMIZE_V)
+clock_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+EXTRA_PROGRAMS += clock_g.rel
+CLEANFILES += clock_g.rel
+clock_g_rel_SOURCES = $(clock_rel_SOURCES)
+clock_g_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_DEBUG_V)
+clock_g_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+noinst_DATA += clock$(LIB_VARIANT).rel
+
+## dbgu
+EXTRA_PROGRAMS += dbgu.rel
+CLEANFILES += dbgu.rel
+dbgu_rel_SOURCES = dbgu/dbgu.c 
+dbgu_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_OPTIMIZE_V)
+dbgu_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+EXTRA_PROGRAMS += dbgu_g.rel
+CLEANFILES += dbgu_g.rel
+dbgu_g_rel_SOURCES = $(dbgu_rel_SOURCES)
+dbgu_g_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_DEBUG_V)
+dbgu_g_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+noinst_DATA += dbgu$(LIB_VARIANT).rel
+
+## timer
+EXTRA_PROGRAMS += timer.rel
+CLEANFILES += timer.rel
+timer_rel_SOURCES = timer/timer.c
+timer_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_OPTIMIZE_V)
+timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+EXTRA_PROGRAMS += timer_g.rel
+CLEANFILES += timer_g.rel
+timer_g_rel_SOURCES = $(timer_rel_SOURCES)
+timer_g_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_DEBUG_V)
+timer_g_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+noinst_DATA += timer$(LIB_VARIANT).rel
+
+## pmc
+EXTRA_PROGRAMS += pmc.rel
+CLEANFILES += pmc.rel
+pmc_rel_SOURCES = pmc/pmc.c
+pmc_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_OPTIMIZE_V)
+pmc_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+EXTRA_PROGRAMS += pmc_g.rel
+CLEANFILES += pmc_g.rel
+pmc_g_rel_SOURCES = $(pmc_rel_SOURCES)
+pmc_g_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_DEBUG_V)
+pmc_g_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+noinst_DATA += pmc$(LIB_VARIANT).rel
+
+## interrupt
+include_HEADERS += irq/irq.h
+
+EXTRA_PROGRAMS += irq.rel
+CLEANFILES += irq.rel
+irq_rel_SOURCES = irq/irq.c irq/bsp_irq_init.c \
+    ../../../libbsp/arm/shared/irq/irq_init.c irq/bsp_irq_asm.S \
+    ../../../libbsp/arm/shared/irq/irq_asm.S irq/irq.h
+irq_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_OPTIMIZE_V)
+irq_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+EXTRA_PROGRAMS += irq_g.rel
+CLEANFILES += irq_g.rel
+irq_g_rel_SOURCES = $(irq_rel_SOURCES)
+irq_g_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_DEBUG_V)
+irq_g_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+noinst_DATA += irq$(LIB_VARIANT).rel
+
+
+endif
+
+## --
+all-local: $(PREINSTALL_FILES)
+
+PREINSTALL_DIRS =
+PREINSTALL_FILES =
+
+$(PROJECT_INCLUDE)/$(dirstamp):
+	@$(mkdir_p) $(PROJECT_INCLUDE)
+	@: > $(PROJECT_INCLUDE)/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
+
+if at91rm9200
+$(PROJECT_INCLUDE)/at91rm9200/$(dirstamp):
+	@$(mkdir_p) $(PROJECT_INCLUDE)/at91rm9200
+	@: > $(PROJECT_INCLUDE)/at91rm9200/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/at91rm9200/$(dirstamp)
+
+$(PROJECT_INCLUDE)/libcpu/$(dirstamp):
+	@$(mkdir_p) $(PROJECT_INCLUDE)/libcpu
+	@: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
+
+$(PROJECT_INCLUDE)/at91rm9200.h: include/at91rm9200.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/at91rm9200.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/at91rm9200.h
+
+$(PROJECT_INCLUDE)/at91rm9200_dbgu.h: include/at91rm9200_dbgu.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/at91rm9200_dbgu.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/at91rm9200_dbgu.h
+
+$(PROJECT_INCLUDE)/at91rm9200_emac.h: include/at91rm9200_emac.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/at91rm9200_emac.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/at91rm9200_emac.h
+
+$(PROJECT_INCLUDE)/at91rm9200_gpio.h: include/at91rm9200_gpio.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/at91rm9200_gpio.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/at91rm9200_gpio.h
+
+$(PROJECT_INCLUDE)/at91rm9200_mem.h: include/at91rm9200_mem.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/at91rm9200_mem.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/at91rm9200_mem.h
+
+$(PROJECT_INCLUDE)/at91rm9200_pmc.h: include/at91rm9200_pmc.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/at91rm9200_pmc.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/at91rm9200_pmc.h
+
+$(PROJECT_INCLUDE)/bits.h: include/bits.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bits.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bits.h
+
+$(PROJECT_INCLUDE)/irq.h: irq/irq.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/irq.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/irq.h
+
+endif
+
+CLEANFILES += $(PREINSTALL_FILES)
+DISTCLEANFILES = $(PREINSTALL_DIRS)
+
+include $(top_srcdir)/../../../automake/local.am
Index: c/src/lib/libcpu/arm/at91rm9200/clock/.cvsignore
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/clock/.cvsignore	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/clock/.cvsignore	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,14 @@
+Makefile
+Makefile.in
+aclocal.m4
+autom4te.cache
+config.cache
+config.guess
+config.log
+config.status
+config.sub
+configure
+depcomp
+install-sh
+missing
+mkinstalldirs
Index: c/src/lib/libcpu/arm/at91rm9200/clock/clock.c
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/clock/clock.c	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/clock/clock.c	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,166 @@
+/*
+ *  AT91RM9200 clock specific using the System Timer
+ *
+ *  Copyright (c) 2003 by Cogent Computer Systems
+ *  Written by Mike Kelly <mike@cogcomp.com>
+ *         and Jay Monkman <jtm@lopingdog.com>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *
+ *  $Id$
+ */
+#include <rtems.h>
+#include <rtems/clockdrv.h>
+#include <rtems/libio.h>
+
+#include <stdlib.h>
+#include <bsp.h>
+#include <irq.h>
+#include <at91rm9200.h>
+
+
+rtems_device_major_number rtems_clock_major = ~0;
+rtems_device_minor_number rtems_clock_minor;
+volatile uint32_t Clock_driver_ticks;
+static unsigned long st_pimr_reload;
+
+rtems_isr clock_isr(rtems_vector_number vector);
+void Clock_exit(void);
+static void clock_isr_on(const rtems_irq_connect_data *unused);
+static void clock_isr_off(const rtems_irq_connect_data *unused);
+static int clock_isr_is_on(const rtems_irq_connect_data *irq);
+
+/* Replace the first value with the clock's interrupt name. */
+rtems_irq_connect_data clock_isr_data = {AT91RM9200_INT_SYSIRQ,   
+                                         (rtems_irq_hdl)clock_isr,
+                                         clock_isr_on,
+                                         clock_isr_off,
+                                         clock_isr_is_on,
+                                         3,     /* unused for ARM cpus */
+                                         0 };   /* unused for ARM cpus */
+
+
+rtems_isr clock_isr(rtems_vector_number vector)
+{
+    uint32_t st_str;
+
+    Clock_driver_ticks++;
+
+    /* read the status to clear the int */
+    st_str = ST_REG(ST_SR);
+
+    /* reload the timer value */
+    ST_REG(ST_PIMR) = st_pimr_reload; 
+
+    rtems_clock_tick();
+}
+
+void Install_clock(rtems_isr_entry clock_isr)
+{
+    uint32_t st_str;
+    int slck;
+
+    Clock_driver_ticks = 0;
+
+    BSP_install_rtems_irq_handler(&clock_isr_data);
+
+    /* the system timer is driven from SLCK */
+    slck = at91rm9200_get_slck();
+    st_pimr_reload = ((BSP_Configuration.microseconds_per_tick * 1000) /
+                      slck);
+
+    /* read the status to clear the int */ 
+    st_str = ST_REG(ST_SR);
+    
+    /* set priority */
+    AIC_SMR_REG(AIC_SMR_SYSIRQ) = AIC_SMR_PRIOR(0x7); 
+
+    /* set the timer value */
+    ST_REG(ST_PIMR) = st_pimr_reload;
+
+    atexit( Clock_exit );
+}
+
+void Clock_exit( void )
+{
+    BSP_remove_rtems_irq_handler(&clock_isr_data);
+}
+
+rtems_device_driver Clock_initialize(
+    rtems_device_major_number major,
+    rtems_device_minor_number minor,
+    void *pargp
+    )
+{
+    Install_clock( clock_isr );
+ 
+    rtems_clock_major = major;
+    rtems_clock_minor = minor;
+
+    return RTEMS_SUCCESSFUL;
+}
+
+rtems_device_driver Clock_control(
+    rtems_device_major_number major,
+    rtems_device_minor_number minor,
+    void *pargp
+)
+{
+    uint32_t  isrlevel;
+    rtems_libio_ioctl_args_t *args = pargp;
+    
+    if (args == 0) {
+        return RTEMS_SUCCESSFUL;
+    }
+ 
+    if (args->command == rtems_build_name('I', 'S', 'R', ' ')) {
+        clock_isr(0);
+    } else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) {
+        rtems_interrupt_disable(isrlevel);
+
+        BSP_install_rtems_irq_handler(args->buffer);
+
+        rtems_interrupt_enable(isrlevel);
+    }
+ 
+    return RTEMS_SUCCESSFUL;
+}
+
+/**
+ * Enables clock interrupt.
+ *
+ * If the interrupt is always on, this can be a NOP.
+ */
+static void clock_isr_on(const rtems_irq_connect_data *unused)
+{
+    /* enable timer interrupt */
+    ST_REG(ST_IER) = ST_SR_PITS; 
+}
+
+/**
+ * Disables clock interrupts
+ *
+ * If the interrupt is always on, this can be a NOP.
+ */
+static void clock_isr_off(const rtems_irq_connect_data *unused)
+{
+    /* disable timer interrupt */
+    ST_REG(ST_IDR) = ST_SR_PITS;
+    return;
+}
+
+/**
+ * Tests to see if clock interrupt is enabled, and returns 1 if so.
+ * If interrupt is not enabled, returns 0.
+ *
+ * If the interrupt is always on, this always returns 1.
+ */
+static int clock_isr_is_on(const rtems_irq_connect_data *irq)
+{
+    /* check timer interrupt */
+    return ST_REG(ST_IMR) & ST_SR_PITS; 
+}
Index: c/src/lib/libcpu/arm/at91rm9200/dbgu/.cvsignore
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/dbgu/.cvsignore	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/dbgu/.cvsignore	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,14 @@
+Makefile
+Makefile.in
+aclocal.m4
+autom4te.cache
+config.cache
+config.guess
+config.log
+config.status
+config.sub
+configure
+depcomp
+install-sh
+missing
+mkinstalldirs
Index: c/src/lib/libcpu/arm/at91rm9200/dbgu/dbgu.c
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/dbgu/dbgu.c	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/dbgu/dbgu.c	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,221 @@
+/*
+ *  Console driver for AT91RM9200 DBGU port
+ *
+ *  This driver uses the shared console driver in 
+ *  ...../libbsp/shared/console.c
+ *
+ *  Copyright (c) 2003 by Cogent Computer Systems
+ *  Written by Mike Kelly <mike@cogcomp.com>
+ *        and Jay Monkman <jtm@lopingdog.com>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+#include <bsp.h>
+#include <rtems/libio.h>
+#include <termios.h>
+
+#include <at91rm9200.h>
+#include <at91rm9200_dbgu.h>
+#include <at91rm9200_pmc.h>
+#include <rtems/bspIo.h>
+#include <libchip/serial.h>
+#include <libchip/sersupp.h>
+
+volatile int dbg_dly;
+
+/* static function prototypes */
+static int     dbgu_first_open(int major, int minor, void *arg);
+static int     dbgu_last_close(int major, int minor, void *arg);
+static int     dbgu_read(int minor);
+static int     dbgu_write(int minor, const char *buf, int len);
+static void    dbgu_init(int minor);
+static void    dbgu_write_polled(int minor, char c);
+static int     dbgu_set_attributes(int minor, const struct termios *t);
+
+/* Pointers to functions for handling the UART. */
+console_fns dbgu_fns = 
+{ 
+    libchip_serial_default_probe,
+    dbgu_first_open,
+    dbgu_last_close,
+    dbgu_read,
+    dbgu_write,
+    dbgu_init,
+    dbgu_write_polled,   /* not used in this driver */
+    dbgu_set_attributes,
+    FALSE      /* TRUE if interrupt driven, FALSE if not. */
+};
+/*********************************************************************/
+/* Functions called via callbacks (i.e. the ones in uart_fns */
+/*********************************************************************/
+
+/* 
+ * This is called the first time each device is opened. Since
+ * the driver is polled, we don't have to do anything. If the driver 
+ * were interrupt driven, we'd enable interrupts here. 
+ */
+static int dbgu_first_open(int major, int minor, void *arg) 
+{
+    return 0;
+}
+
+
+/* 
+ * This is called the last time each device is closed.  Since
+ * the driver is polled, we don't have to do anything. If the driver 
+ * were interrupt driven, we'd disable interrupts here. 
+ */
+static int dbgu_last_close(int major, int minor, void *arg) 
+{
+    return 0;
+}
+
+
+/*
+ * Read one character from UART.
+ *
+ * return -1 if there's no data, otherwise return
+ * the character in lowest 8 bits of returned int.
+ */
+static int dbgu_read(int minor) 
+{
+    char c;
+    console_tbl *console_entry;
+    at91rm9200_dbgu_regs_t *dbgu;
+
+    console_entry = BSP_get_uart_from_minor(minor);
+
+    if (console_entry == NULL) {
+        return -1;
+    }
+
+    dbgu = (at91rm9200_dbgu_regs_t *)console_entry->ulCtrlPort1;
+
+    if (!(dbgu->sr & DBGU_INT_RXRDY)) {
+        return -1;
+    }
+    
+    c  = dbgu->rhr & 0xff; 
+    
+    return c;
+}
+
+
+/* 
+ * Write buffer to UART 
+ *
+ * return 1 on success, -1 on error
+ */
+static int dbgu_write(int minor, const char *buf, int len)
+{
+    int i, x;
+    char c;
+    console_tbl *console_entry;
+    at91rm9200_dbgu_regs_t *dbgu;
+
+    console_entry = BSP_get_uart_from_minor(minor);
+
+    if (console_entry == NULL) {
+        return -1;
+    }
+
+    dbgu = (at91rm9200_dbgu_regs_t *)console_entry->ulCtrlPort1;
+
+    for (i = 0; i < len; i++) {
+        /* Wait for fifo to have room */
+        while(1) {
+            if (dbgu->sr & DBGU_INT_TXRDY) {
+                break;
+            }
+        }
+        
+        c = (char) buf[i];
+        dbgu->thr = c;
+        
+        /* the TXRDY flag does not seem to update right away (is this true?) */
+        /* so we wait a bit before continuing */
+        for (x = 0; x < 100; x++) {
+            dbg_dly++; /* using a global so this doesn't get optimized out */
+        }
+    }
+    
+    return 1;
+}
+
+
+/* Set up the UART. */
+static void dbgu_init(int minor)
+{
+    console_tbl *console_entry;
+    at91rm9200_dbgu_regs_t *dbgu;
+
+    console_entry = BSP_get_uart_from_minor(minor);
+
+    if (console_entry == NULL) {
+        return;
+    }
+
+    dbgu = (at91rm9200_dbgu_regs_t *)console_entry->ulCtrlPort1;
+
+    /* Clear error bits, and reset */
+    dbgu->cr = (DBGU_CR_RSTSTA | DBGU_CR_RSTTX | DBGU_CR_RSTRX);
+
+    /* Clear pending interrupts */
+    dbgu->idr = DBGU_INT_ALL;
+    dbgu->imr = 0;
+
+    /* Set port to no parity, no loopback */
+    dbgu->mr = DBGU_MR_PAR_NONE | DBGU_MR_CHMODE_NORM;
+
+    /* Set the baud rate */
+    dbgu->brgr = (at91rm9200_get_mck() / 16) / BSP_get_baud();
+
+    /* Enable the DBGU */
+    dbgu->cr = (DBGU_CR_TXEN | DBGU_CR_RXEN);
+}
+
+/* I'm not sure this is needed for the shared console driver. */
+static void dbgu_write_polled(int minor, char c)
+{
+    dbgu_write(minor, &c, 1);
+}
+
+/* This is for setting baud rate, bits, etc. */
+static int dbgu_set_attributes(int minor, const struct termios *t) 
+{
+    return 0;
+}
+
+/***********************************************************************/
+/*
+ * The following functions are not used by TERMIOS, but other RTEMS
+ * functions use them instead.
+ */
+/***********************************************************************/
+/* 
+ * Read from UART. This is used in the exit code, and can't
+ * rely on interrupts.
+ */
+int dbgu_poll_read(int minor)
+{
+    return dbgu_read(minor);
+}
+
+
+/*
+ * Write a character to the console. This is used by printk() and 
+ * maybe other low level functions. It should not use interrupts or any
+ * RTEMS system calls. It needs to be very simple
+ */
+static void _BSP_put_char( char c ) {
+    dbgu_write_polled(0, c);
+}
+
+BSP_output_char_function_type BSP_output_char = _BSP_put_char;
+
+
Index: c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200.h
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200.h	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200.h	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,332 @@
+/*
+ * Atmel AT91RM9200 Register definitions
+ *
+ * Copyright (c) 2003 by Cogent Computer Systems
+ * Written by Mike Kelly <mike@cogcomp.com>
+ *	
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+#ifndef __AT91RM9200_H__
+#define __AT91RM9200_H__
+
+#include "bits.h"
+
+typedef volatile unsigned long vulong;
+
+/* Source Mode Register - 32 of them */
+#define AIC_SMR_BASE            0xFFFFF000
+#define AIC_SMR_REG(_x_)        *(vulong *)(AIC_SMR_BASE + (_x_ & 0x7c))
+
+/* Source Vector Register - 32 of them */
+#define AIC_SVR_BASE            0xFFFFF080
+#define AIC_SVR_REG(_x_)        *(vulong *)(AIC_SVR_BASE + (_x_ & 0x7c))
+
+/* Control Register - 32 of them */
+#define AIC_CTL_BASE            0xFFFFF100      
+#define AIC_CTL_REG(_x_)        *(vulong *)(AIC_CTL_BASE + (_x_ & 0x7f))
+
+/* Register Offsets */
+/* offsets from AIC_SMR_BASE and AIC_SVR_BASE */
+#define AIC_SMR_FIQ             0x00    // Advanced Interrupt Controller FIQ
+#define AIC_SMR_SYSIRQ          0x04    // Advanced Interrupt Controller SYSIRQ
+#define AIC_SMR_PIOA            0x08    // Parallel I/O Controller A
+#define AIC_SMR_PIOB            0x0c    // Parallel I/O Controller B
+#define AIC_SMR_PIOC            0x10    // Parallel I/O Controller C
+#define AIC_SMR_PIOD            0x14    // Parallel I/O Controller D
+#define AIC_SMR_US0             0x18    // USART 0
+#define AIC_SMR_US1             0x1c    // USART 1
+#define AIC_SMR_US2             0x20    // USART 2
+#define AIC_SMR_US3             0x24    // USART 3
+#define AIC_SMR_MCI             0x28    // Multimedia Card Interface
+#define AIC_SMR_UDP             0x2c    // USB Device Port
+#define AIC_SMR_TWI             0x30    // Two-wire Interface
+#define AIC_SMR_SPI             0x34    // Serial Peripheral Interface
+#define AIC_SMR_SSC0            0x38    // Synchronous Serial Controller 0
+#define AIC_SMR_SSC1            0x3c    // Synchronous Serial Controller 1
+#define AIC_SMR_SSC2            0x40    // Synchronous Serial Controller 2
+#define AIC_SMR_TC0             0x44    // Timer/Counter 0
+#define AIC_SMR_TC1             0x48    // Timer/Counter 1
+#define AIC_SMR_TC2             0x4c    // Timer/Counter 2
+#define AIC_SMR_TC3             0x50    // Timer/Counter 3
+#define AIC_SMR_TC4             0x54    // Timer/Counter 4
+#define AIC_SMR_TC5             0x58    // Timer/Counter 5
+#define AIC_SMR_UHP             0x5c    // USB Host Port
+#define AIC_SMR_EMAC            0x60    // Ethernet MAC
+#define AIC_SMR_IRQ0            0x64    // Advanced Interrupt Controller IRQ0
+#define AIC_SMR_IRQ1            0x68    // Advanced Interrupt Controller IRQ1
+#define AIC_SMR_IRQ2            0x6c    // Advanced Interrupt Controller IRQ2
+#define AIC_SMR_IRQ3            0x70    // Advanced Interrupt Controller IRQ3
+#define AIC_SMR_IRQ4            0x74    // Advanced Interrupt Controller IRQ4
+#define AIC_SMR_IRQ5            0x78    // Advanced Interrupt Controller IRQ5
+#define AIC_SMR_IRQ6            0x7c    // Advanced Interrupt Controller IRQ6
+
+/* from AIC_CTL_BASE */
+#define AIC_IVR                 0x00    // IRQ Vector Register
+#define AIC_FVR                 0x04    // FIQ Vector Register
+#define AIC_ISR                 0x08    // Interrupt Status Register
+#define AIC_IPR                 0x0C    // Interrupt Pending Register
+#define AIC_IMR                 0x10    // Interrupt Mask Register
+#define AIC_CISR                0x14    // Core Interrupt Status Register
+#define AIC_IECR                0x20    // Interrupt Enable Command Register
+#define AIC_IDCR                0x24    // Interrupt Disable Command Register
+#define AIC_ICCR                0x28    // Interrupt Clear Command Register
+#define AIC_ISCR                0x2C    // Interrupt Set Command Register
+#define AIC_EOICR               0x30    // End of Interrupt Command Register
+#define AIC_SPU                 0x34    // Spurious Vector Register
+#define AIC_DCR                 0x38    // Debug Control Register (Protect)
+#define AIC_FFER                0x40    // Fast Forcing Enable Register
+#define AIC_FFDR                0x44    // Fast Forcing Disable Register
+#define AIC_FFSR                0x48    // Fast Forcing Status Register
+
+/* Bit Defines */
+/* AIC_ISR - Interrupt Status Register */
+#define AIC_ISR_IRQID_MASK      0x1f    // current interrupt ID         
+
+// AIC_CISR - Core Interrupt Status Register
+#define AIC_CISR_IRQ            BIT1    // 1 = Core IRQ is active
+#define AIC_CISR_FIQ            BIT0    // 1 = Core FIQ is active
+
+// AIC_DCR - Debug Control Register (Protect)
+#define AIC_DCR_GMSK            BIT1    // 0 = AIC controls IRQ and FIQ
+#define AIC_DCR_PROT            BIT0    // 1 = enable protection mode
+
+// AIC_SMR
+#define AIC_SMR_PRIOR(_x_)      ((_x_ & 0x07) << 0)
+#define AIC_SMR_SRC_LVL_LOW     (0 << 5)        // Are these right? docs don't say which is high/low    
+#define AIC_SMR_SRC_EDGE_LOW    (1 << 5)        
+#define AIC_SMR_SRC_LVL_HI      (2 << 5)        
+#define AIC_SMR_SRC_EDGE_HI     (3 << 5)        
+
+/**************************************************************************/
+/* Debug Unit                                                             */
+/**************************************************************************/
+#define DBGU_BASE               0xFFFFF200
+#define DBGU_REG(_x_)   *(vulong *)(DBGU_BASE + _x_)
+
+// Register Offsets
+#define DBGU_CR                 0x00    // Control Register
+#define DBGU_MR                 0x04    // Mode Register
+#define DBGU_IER                0x08    // Interrupt Enable Register
+#define DBGU_IDR                0x0C    // Interrupt Disable Register
+#define DBGU_IMR                0x10    // Interrupt Mask Register
+#define DBGU_CSR                0x14    // Channel Status Register
+#define DBGU_RHR                0x18    // Receiver Holding Register
+#define DBGU_THR                0x1C    // Transmitter Holding Register
+#define DBGU_BRGR               0x20    // Baud Rate Generator Register
+#define DBGU_C1R                0x40    // Chip ID1 Register
+#define DBGU_C2R                0x44    // Chip ID2 Register
+#define DBGU_FNTR               0x48    // Force NTRST Register
+
+/****************/
+/* System Timer */
+/****************/
+#define ST_BASE                 0xFFFFFD00
+#define ST_REG(_x_)             *(vulong *)(ST_BASE + _x_)
+
+// Register Offsets
+#define ST_CR                   0x00    // Control Register
+#define ST_PIMR                 0x04    // Period Interval Mode Register
+#define ST_WDMR                 0x08    // Watchdog Mode Register
+#define ST_RTMR                 0x0C    // Real-time Mode Register
+#define ST_SR                   0x10    // Status Register
+#define ST_IER                  0x14    // Interrupt Enable Register
+#define ST_IDR                  0x18    // Interrupt Disable Register
+#define ST_IMR                  0x1C    // Interrupt Mask Register
+#define ST_RTAR                 0x20    // Real-time Alarm Register
+#define ST_CRTR                 0x24    // Current Real-time Register
+
+// Bit Defines
+// ST_CR - Control Register
+#define ST_CR_WDRST                     BIT0    // write 1 to reload WD counter 
+
+// ST_PIMR - Period Interval Mode Register
+#define ST_PIMR_PIV_MASK        0x0000ffff
+
+// ST_WDMR - Watchdog Mode Register
+#define ST_WDMR_EXTEN           BIT17   // WDOVF is not implemented on AT91RM9200
+#define ST_WDMR_RSTEN           BIT16   // 1 = reset the AT91RM9200 when WD overflows
+#define ST_WDMR_WDV_MASK        0x0000ffff      // WD counter is in the lower 16-bits
+
+// ST_RTMR - Real-time Mode Register
+#define ST_RTMR_RTPRES_MASK     0x0000ffff      // Real-Time Prescaler
+
+// ST_SR - Status Register - Read Only
+// ST_IER - Interrupt Enable Register - Write Only
+// ST_IDR - Interrupt Disable Register - Write Only
+// ST_IMR - Interrupt Mask Register - Read Only
+#define ST_SR_ALMS                      BIT3
+#define ST_SR_RTTINC            BIT2
+#define ST_SR_WDOVF                     BIT1
+#define ST_SR_PITS                      BIT0
+
+// ST_RTAR - Real-time Alarm Register
+#define ST_RTAR_ALMV_MASK       0x000fffff
+
+// ST_CRTR - Current Real-time Register
+#define ST_CRTR_CRTV_MASK       0x000fffff
+
+
+/**************************************************************************
+ * Peripheral Data Control (DMA)
+ * Note that each of the following peripherals has it's own
+ * set of these registers starting at offset 0x100 from it's
+ * base address: DBGU, SPI, USART and SSC
+ * To access the DMA for a peripheral, use the macro for that 
+ * peripheral but with these register offsets
+ **************************************************************************/
+// Register Offsets
+#define PDC_RPR         0x100   // Receive Pointer Register
+#define PDC_RCR         0x104   // Receive Counter Register
+#define PDC_TPR         0x108   // Transmit Pointer Register
+#define PDC_TCR         0x10c   // Transmit Counter Register
+#define PDC_RNPR        0x110   // Receive Next Pointer Register
+#define PDC_RNCR        0x114   // Receive Next Counter Register
+#define PDC_TNPR        0x118   // Transmit Next Pointer Register
+#define PDC_TNCR        0x11c   // Transmit Next Counter Register
+#define PDC_PTCR        0x120   // PDC Transfer Control Register
+#define PDC_PTSR        0x124   // PDC Transfer Status Register
+
+/**************************************************************************
+ * Parallel I/O Unit
+ * There are four PIO blocks - A, B, C and D.  They all have the
+ * same register set, but different base addresses
+ **************************************************************************/
+// Port A
+#define PIOA_BASE               0xFFFFF400
+#define PIOA_REG(_x_)   *(vulong *)(PIOA_BASE + _x_)
+
+// Port B
+#define PIOB_BASE               0xFFFFF600
+#define PIOB_REG(_x_)   *(vulong *)(PIOB_BASE + _x_)
+
+// Port C
+#define PIOC_BASE               0xFFFFF800
+#define PIOC_REG(_x_)   *(vulong *)(PIOC_BASE + _x_)
+
+// Port D
+#define PIOD_BASE               0xFFFFFA00
+#define PIOD_REG(_x_)   *(vulong *)(PIOD_BASE + _x_)
+
+/**************************************************************************
+ * Power Management and Clock Control
+ *************************************************************************/
+#define PMC_BASE                0xFFFFFC00
+#define PMC_REG(_x_)    *(vulong *)(PMC_BASE + _x_)
+
+/**************************************************************************
+ * MAC Unit
+ *************************************************************************/
+#define EMAC_BASE               0xFFFBC000
+#define EMAC_REG(_x_)   *(vulong *)(EMAC_BASE + _x_)
+
+/**************************************************************************
+ * Timer/Counter Unit
+ **************************************************************************/
+#define TC_BASE         0xFFFA0000
+#define TC_REG(_x_)     *(vulong *)(TC_BASE + 0x00 + _x_)
+#define TC_TC0_REG(_x_) *(vulong *)(TC_BASE + 0x00 + _x_)
+#define TC_TC1_REG(_x_) *(vulong *)(TC_BASE + 0x40 + _x_)
+#define TC_TC2_REG(_x_) *(vulong *)(TC_BASE + 0x80 + _x_)
+
+// Offsets from TC_TC?_REG 
+#define TC_CCR      0x00    // Channel Control Register 
+#define TC_CMR      0x04    // Channel Mode Register 
+#define TC_CV       0x10    // Counter Value 
+#define TC_RA       0x14    // Register A 
+#define TC_RB       0x18    // Register B 
+#define TC_RC       0x1C    // Register C 
+#define TC_SR       0x20    // Status Register 
+#define TC_IER      0x24    // Interrupt Enable Register 
+#define TC_IDR      0x28    // Interrupt Disable Register 
+#define TC_IMR      0x2C    // Interrupt Mask Register 
+
+// Offsets from TC_BASE
+#define TC_BCR      0xc0    // Channel Control Register 
+#define TC_BMR      0xc4    // Channel Control Register 
+
+// Block control register
+#define TC_BCR_SYNC    BIT1       // Set to syncronize channels
+
+// Block mode register
+#define TC_BMR_TC0(_x_)    ((_x_ & 0x3) << 0)   // TC0 clock source
+#define TC_BMR_TC1(_x_)    ((_x_ & 0x3) << 2)   // TC1 clock source
+#define TC_BMR_TC2(_x_)    ((_x_ & 0x3) << 4)   // TC2 clock source
+
+// Channel Control register
+#define TC_CCR_CLKEN     BIT0       // Enable clock
+#define TC_CCR_CLKDIS    BIT1       // Disable clock
+#define TC_CCR_SWTRG     BIT2       // Software trigger command
+
+// Channel mode register
+#define TC_CMR_TCCLKS(_x_)   ((_x_ & 0x7) << 0)  // Clock source
+#define TC_CMR_CLKI          BIT3                // Clock invert
+#define TC_BURST(_x_)        ((_x_ & 0x3 << 4)   // Burst signal selection
+#define TC_WAVE              BIT15               // 0 for catpure, 1 for wave
+
+// Channel mode register - capture mode (TC_WAVE = 0)
+#define TC_CMR_LDBSTOP       BIT6                // Set to stop clock when RB loads
+#define TC_CMR_LDBDIS        BIT7                // Set to disable clock when RB loads
+#define TC_CMR_ETRGEDG(_x_)  ((_x_ & 0x3) << 8)  // Select edge triggering mode
+#define TC_CMR_ABETRG        BIT10               // Select ext trigger source
+#define TC_CMR_CPCTRG        BIT14               // RC Compare trigger enable
+#define TC_CMR_LDRA(_x_)     ((_x_ & 0x3) << 16) // RA loading selection
+#define TC_CMR_LDRB(_x_)     ((_x_ & 0x3) << 18) // RB loading selection
+
+// Channel mode register - wave mode (TC_WAVE = 1)
+#define TC_CMR_CPCSTOP       BIT6                 // Clock stopped w/ RC compare
+#define TC_CMR_CPCDIS        BIT7                 // Clock disabled w/ RC compare
+#define TC_CMR_EEVTEDG(_x_)  ((_x_ & 0x3) << 8)   // Ext event edge selection
+#define TC_CMR_EEVT(_x_)     ((_x_ & 0x3) << 10)  // Ext event selection
+#define TC_CMR_ENETRG        BIT12                // Ext event trigger enable
+#define TC_CMR_WAVESEL(_x_)  ((_x_ & 0x3) << 13)  // Waveform selection
+#define TC_CMR_ACPA(_x_)     ((_x_ & 0x3) << 16)  // RA compare effect on TIOA
+#define TC_CMR_ACPC(_x_)     ((_x_ & 0x3) << 18)  // RC compare effect on TIOA
+#define TC_CMR_AEEVT(_x_)    ((_x_ & 0x3) << 20)  // Ext event effect on TIOA
+#define TC_CMR_ASWTRG(_x_)   ((_x_ & 0x3) << 22)  // SW trigger effect on TIOA
+#define TC_CMR_BCPB(_x_)     ((_x_ & 0x3) << 24)  // RB compare effect on TIOB
+#define TC_CMR_BCPC(_x_)     ((_x_ & 0x3) << 26)  // RC compare effect on TIOB
+#define TC_CMR_BEEVT(_x_)    ((_x_ & 0x3) << 28)  // Ext event effect on TIOB
+#define TC_CMR_BSWTRG(_x_)   ((_x_ & 0x3) << 30)  // SW trigger effect on TIOB
+
+// Counter value
+#define TC_CV_MASK            0xffff              // Timer counter mask
+
+// Status, Interrupt enable, Interrupt disable, and Interrupt mask registers
+#define TC_SR_COVFS     BIT0        // Counter overflow status
+#define TC_SR_LOVRS     BIT1        // Load overrun status
+#define TC_SR_CPAS      BIT2        // RA compare status
+#define TC_SR_CPBS      BIT3        // RB compare status
+#define TC_SR_CPCS      BIT4        // RC compare status
+#define TC_SR_LDRAS     BIT5        // RA loading status
+#define TC_SR_LDRBS     BIT6        // RB loading  status
+#define TC_SR_ETRGS     BIT7        // External trigger status
+#define TC_SR_CLKSTA    BIT16       // Clock enabling status
+#define TC_SR_MTIOA     BIT17       // TIOA Mirror
+#define TC_SR_MTIOB     BIT18       // TIOB Mirror
+
+
+
+
+/***************************************************************************
+ * External Bus Interface Unit
+ **************************************************************************/
+#define EBI_BASE                        0xFFFFFF60
+#define EBI_REG(_x_)            *(vulong *)(EBI_BASE + _x_)
+
+/***************************************************************************
+ * Static Memory Interface Unit
+ ***************************************************************************/
+#define SMC_REG(_x_)            *(vulong *)(EBI_BASE + 0x10 + _x_)
+
+/**************************************************************************
+ * SDRAM Memory Interface Unit
+ **************************************************************************/
+#define SDRC_REG(_x_)           *(vulong *)(EBI_BASE + 0x30 + _x_)
+
+#endif /* __AT91RM9200_H__ */
+
Index: c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_dbgu.h
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_dbgu.h	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_dbgu.h	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,92 @@
+/*
+ * Atmel AT91RM9200_DBGU Register definitions
+ *
+ * Copyright (c) 2003 by Cogent Computer Systems
+ * Written by Mike Kelly <mike@cogcomp.com>
+ *      
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+#ifndef __AT91RM9200_DBGU_H__
+#define __AT91RM9200_DBGU_H__
+
+#include "bits.h"
+
+// Register Offsets
+#define DBGU_CR         0x00            // Control Register
+#define DBGU_MR         0x04            // Mode Register
+#define DBGU_IER        0x08            // Interrupt Enable Register
+#define DBGU_IDR        0x0C            // Interrupt Disable Register
+#define DBGU_IMR        0x10            // Interrupt Mask Register
+#define DBGU_SR         0x14            // Channel Status Register
+#define DBGU_RHR        0x18            // Receiver Holding Register
+#define DBGU_THR        0x1C            // Transmitter Holding Register
+#define DBGU_BRGR       0x20            // Baud Rate Generator Register
+#define DBGU_C1R        0x40            // Chip ID1 Register
+#define DBGU_C2R        0x44            // Chip ID2 Register
+#define DBGU_FNTR       0x48            // Force NTRST Register
+
+// Bit Defines
+// Control Register, DBGU_CR, Offset 0x00
+#define DBGU_CR_RSTRX   BIT2            // 1 = Reset and disable receiver
+#define DBGU_CR_RSTTX   BIT3            // 1 = Reset and disable transmitter
+#define DBGU_CR_RXEN    BIT4            // 1 = Receiver enable
+#define DBGU_CR_RXDIS   BIT5            // 1 = Receiver disable
+#define DBGU_CR_TXEN    BIT6            // 1 = Transmitter enable
+#define DBGU_CR_TXDIS   BIT7            // 1 = Transmitter disable
+#define DBGU_CR_RSTSTA  BIT8            // 1 = Reset PARE, FRAME and OVRE in DBGU_SR.
+
+// Mode Register. DBGU_MR. Offset 0x04
+#define DBGU_MR_PAR_EVEN    (0x0 <<  9) // Even Parity
+#define DBGU_MR_PAR_ODD     (0x1 <<  9) // Odd Parity
+#define DBGU_MR_PAR_SPACE   (0x2 <<  9) // Parity forced to 0 (Space)
+#define DBGU_MR_PAR_MARK    (0x3 <<  9) // Parity forced to 1 (Mark)
+#define DBGU_MR_PAR_NONE    (0x4 <<  9) // No Parity
+#define DBGU_MR_PAR_MDROP   (0x6 <<  9) // Multi-drop mode
+#define DBGU_MR_CHMODE_NORM (0x0 << 14) // Normal Mode
+#define DBGU_MR_CHMODE_AUTO (0x1 << 14) // Auto Echo: RXD drives TXD
+#define DBGU_MR_CHMODE_LOC  (0x2 << 14) // Local Loopback: TXD drives RXD
+#define DBGU_MR_CHMODE_REM  (0x3 << 14) // Remote Loopback: RXD pin connected to TXD pin.
+
+// Interrupt Enable Register, DBGU_IER, Offset 0x08
+// Interrupt Disable Register, DBGU_IDR, Offset 0x0C
+// Interrupt Mask Register, DBGU_IMR, Offset 0x10
+// Channel Status Register, DBGU_SR, Offset 0x14
+#define DBGU_INT_RXRDY      BIT0        // RXRDY Interrupt
+#define DBGU_INT_TXRDY      BIT1        // TXRDY Interrupt
+#define DBGU_INT_ENDRX      BIT3        // End of Receive Transfer Interrupt
+#define DBGU_INT_ENDTX      BIT4        // End of Transmit Interrupt
+#define DBGU_INT_OVRE       BIT5        // Overrun Interrupt
+#define DBGU_INT_FRAME      BIT6        // Framing Error Interrupt
+#define DBGU_INT_PARE       BIT7        // Parity Error Interrupt
+#define DBGU_INT_TXEMPTY    BIT9        // TXEMPTY Interrupt
+#define DBGU_INT_TXBUFE     BIT11       // TXBUFE Interrupt
+#define DBGU_INT_RXBUFF     BIT12       // RXBUFF Interrupt
+#define DBGU_INT_COMM_TX    BIT30       // COMM_TX Interrupt
+#define DBGU_INT_COMM_RX    BIT31       // COMM_RX Interrupt
+#define DBGU_INT_ALL        0xC0001AFB  // all assigned bits
+
+// FORCE_NTRST Register, DBGU_FNTR, Offset 0x48
+#define DBGU_FNTR_NTRST         BIT0    // 1 = Force NTRST low in JTAG
+
+typedef struct {
+    volatile uint32_t cr;
+    volatile uint32_t mr;
+    volatile uint32_t ier;
+    volatile uint32_t idr;
+    volatile uint32_t imr;
+    volatile uint32_t sr;
+    volatile uint32_t rhr;
+    volatile uint32_t thr;
+    volatile uint32_t brgr;
+    volatile uint32_t _res0[7];
+    volatile uint32_t cidr;
+    volatile uint32_t exid;
+    volatile uint32_t fnr;
+} at91rm9200_dbgu_regs_t;
+
+#endif /* __AT91RM9200_DBGU_H__ */
Index: c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_emac.h
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_emac.h	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_emac.h	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,157 @@
+/*
+ * Atmel AT91RM9200 EMAC Register definitions
+ *
+ * Copyright (c) 2003 by Cogent Computer Systems
+ * Written by Mike Kelly <mike@cogcomp.com>
+ *      
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+#ifndef __AT91RM9200_EMAC_H__
+#define __AT91RM9200_EMAC_H__
+
+#include <bits.h>
+
+//Register offsets
+#define EMAC_CTL        0x00            // Network Control Register
+#define EMAC_CFG        0x04            // Network Configuration Register
+#define EMAC_SR         0x08            // Network Status Register
+#define EMAC_TAR        0x0C            // Transmit Address Register
+#define EMAC_TCR        0x10            // Transmit Control Register
+#define EMAC_TSR        0x14            // Transmit Status Register
+#define EMAC_RBQP       0x18            // Receive Buffer Queue Pointer
+#define EMAC_RSR        0x20            // Receive Status Register
+#define EMAC_ISR        0x24            // Interrupt Enable Register
+#define EMAC_IER        0x28            // Interrupt Enable Register
+#define EMAC_IDR        0x2C            // Interrupt Disable Register
+#define EMAC_IMR        0x30            // Interrupt Mask Register
+#define EMAC_MAN        0x34            // PHY Maintenance Register
+#define EMAC_FRA        0x40            // Frames Transmitted OK Register
+#define EMAC_SCOL       0x44            // Single Collision Frame Register
+#define EMAC_MCOL       0x48            // Multiple Collision Frame Register
+#define EMAC_OK         0x4C            // Frames Received OK Register
+#define EMAC_SEQE       0x50            // Frame Check Sequence Error Register
+#define EMAC_ALE        0x54            // Alignment Error Register
+#define EMAC_DTE        0x58            // Deferred Transmission Frame Register
+#define EMAC_LCOL       0x5C            // Late Collision Register
+#define EMAC_ECOL       0x60            // Excessive Collision Register
+#define EMAC_CSE        0x64            // Carrier Sense Error Register
+#define EMAC_TUE        0x68            // Transmit Underrun Error Register
+#define EMAC_CDE        0x6C            // Code Error Register
+#define EMAC_ELR        0x70            // Excessive Length Error Register
+#define EMAC_RJB        0x74            // Receive Jabber Register
+#define EMAC_USF        0x78            // Undersize Frame Register
+#define EMAC_SQEE       0x7C            // SQE Test Error Register
+#define EMAC_DRFC       0x80            // Discarded RX Frame Register
+#define EMAC_HSH        0x90            // Hash Address High[63:32]
+#define EMAC_HSL        0x94            // Hash Address Low[31:0]
+#define EMAC_SA1L       0x98            // Specific Addr 1 Low, First 4 bytes
+#define EMAC_SA1H       0x9C            // Specific Addr 1 High, Last 2 bytes
+#define EMAC_SA2L       0xA0            // Specific Addr 2 Low, First 4 bytes
+#define EMAC_SA2H       0xA4            // Specific Addr 2 High, Last 2 bytes
+#define EMAC_SA3L       0xA8            // Specific Addr 3 Low, First 4 bytes
+#define EMAC_SA3H       0xAC            // Specific Addr 3 High, Last 2 bytes
+#define EMAC_SA4L       0xB0            // Specific Addr 4 Low, First 4 bytes
+#define EMAC_SA4H       0xB4            // Specific Addr 4 High, Last 2 bytesr
+
+// Control Register, EMAC_CTL, Offset 0x0
+#define EMAC_CTL_LB     BIT0            // 1 = Set Loopback output signal
+#define EMAC_CTL_LBL    BIT1            // 1 = Loopback local. 
+#define EMAC_CTL_RE     BIT2            // 1 = Receive enable. 
+#define EMAC_CTL_TE     BIT3            // 1 = Transmit enable. 
+#define EMAC_CTL_MPE    BIT4            // 1 = Management port enable. 
+#define EMAC_CTL_CSR    BIT5            // Write 1 to clear stats registers. 
+#define EMAC_CTL_ISR    BIT6            // Write to increment stats registers
+#define EMAC_CTL_WES    BIT7            // 1 = Enable writing to stats regs
+#define EMAC_CTL_BP     BIT8            // 1 = Force collision on all RX frames
+
+// Configuration Register, EMAC_CFG, Offset 0x4
+#define EMAC_CFG_SPD    BIT0            // 1 = 10/100 Speed (not functional?)
+#define EMAC_CFG_FD     BIT1            // 1 = Full duplex. 
+#define EMAC_CFG_BR     BIT2            // write 0 
+#define EMAC_CFG_CAF    BIT4            // 1 = accept all frames
+#define EMAC_CFG_NBC    BIT5            // 1 = disable reception of bcast frms
+#define EMAC_CFG_MTI    BIT6            // 1 = Multicast hash enable
+#define EMAC_CFG_UNI    BIT7            // 1 = Unicast hash enable. 
+#define EMAC_CFG_BIG    BIT8            // 1 = enable reception 1522 byte frms
+#define EMAC_CFG_EAE    BIT9            // write 0
+#define EMAC_CFG_CLK_8  (0 << 10)       // MII Clock = HCLK divided by 8
+#define EMAC_CFG_CLK_16 (1 << 10)       // MII Clock = HCLK divided by 16
+#define EMAC_CFG_CLK_32 (2 << 10)       // MII Clock = HCLK divided by 32
+#define EMAC_CFG_CLK_64 (3 << 10)       // MII Clock = HCLK divided by 64
+#define EMAC_CFG_RTY    BIT12           // Retry Test Mode - Must be 0 
+#define EMAC_CFG_RMII   BIT13           // Reduced MII Mode Enable
+
+// Status Register, EMAC_SR, Offset 0x8
+#define EMAC_LINK       BIT0            // Link pin 
+#define EMAC_MDIO       BIT1            // Real Time state of MDIO pin
+#define EMAC_IDLE       BIT2            // 0 = PHY Logic is idle
+
+// Transmit Control Register, EMAC_TCR, Offset 0x10
+#define EMAC_TCR_LEN(_x_)  ((_x_ & 0x7FF) <<  0)   // Tx frame len minus CRC
+#define EMAC_TCR_NCRC   BIT15                      // Do'nt append CRC on Tx
+
+// Transmit Status Register, EMAC_TSR, Offset 0x14
+#define EMAC_TSR_OVR    BIT0            // 1 = Transmit buffer overrun
+#define EMAC_TSR_COL    BIT1            // 1 = Collision occured
+#define EMAC_TSR_RLE    BIT2            // 1 = Retry lmimt exceeded
+#define EMAC_TSR_TXIDLE BIT3            // 1 = Transmitter is idle
+#define EMAC_TSR_BNQ    BIT4            // 1 = Transmit buffer not queued
+#define EMAC_TSR_COMP   BIT5            // 1 = Transmit complete
+#define EMAC_TSR_UND    BIT6            // 1 = Transmit underrun
+ 
+// Receive Status Register, EMAC_RSR, Offset 0x20
+#define EMAC_RSR_BNA    BIT0            // 1 = Buffer not available
+#define EMAC_RSR_REC    BIT1            // 1 = Frame received
+#define EMAC_RSR_OVR    BIT2            // 1 = Receive overrun
+
+// Interrupt Status Register, EMAC_ISR, Offsen 0x24
+// Interrupt Enable Register, EMAC_IER, Offset 0x28
+// Interrupt Disable Register, EMAC_IDR, Offset 0x2c
+// Interrupt Mask Register, EMAC_IMR, Offset 0x30
+#define EMAC_INT_DONE   BIT0            // Phy management done 
+#define EMAC_INT_RCOM   BIT1            // Receive complete
+#define EMAC_INT_RBNA   BIT2            // Receive buffer not available
+#define EMAC_INT_TOVR   BIT3            // Transmit buffer overrun
+#define EMAC_INT_TUND   BIT4            // Transmit buffer underrun
+#define EMAC_INT_RTRY   BIT5            // Transmit Retry limt
+#define EMAC_INT_TBRE   BIT6            // Transmit buffer register empty
+#define EMAC_INT_TCOM   BIT7            // Transmit complete
+#define EMAC_INT_TIDLE  BIT8            // Transmit idle
+#define EMAC_INT_LINK   BIT9            // Link pin changed value
+#define EMAC_INT_ROVR   BIT10           // Receive overrun
+#define EMAC_INT_ABT    BIT11           // Abort on DMA transfer
+
+// PHY Maintenance Register, EMAC_MAN, Offset 0x34
+#define EMAC_MAN_DATA(_x_)      ((_x_ & 0xFFFF) <<  0)  // PHY data register
+#define EMAC_MAN_CODE           (0x3 << 6)              // IEEE Code
+#define EMAC_MAN_REGA(_x_)      ((_x_ & 0x1F) << 18)    // PHY register address
+#define EMAC_MAN_PHYA(_x_)      ((_x_ & 0x1F) << 23)    // PHY address
+#define EMAC_MAN_WRITE          (0x1 << 28)             // Transfer is a write
+#define EMAC_MAN_READ           (0x2 << 28)             // Transfer is a read
+#define EMAC_MAN_HIGH           BIT30                   // Must be set
+
+// Bit assignments for Receive Buffer Descriptor
+// Address - Word 0
+#define RXBUF_ADD_BASE_MASK     0xfffffffc      // Base addr of the rx buf
+#define RXBUF_ADD_WRAP          BIT1            // set indicates last buf 
+#define RXBUF_ADD_OWNED         BIT0            // 1 = SW owns the pointer
+
+// Status - Word 1
+#define RXBUF_STAT_BCAST        BIT31           // Global bcast addr detected
+#define RXBUF_STAT_MULTI        BIT30           // Multicast hash match
+#define RXBUF_STAT_UNI          BIT29           // Unicast hash match
+#define RXBUF_STAT_EXT          BIT28           // External address (optional)
+#define RXBUF_STAT_UNK          BIT27           // Unknown source address 
+#define RXBUF_STAT_LOC1         BIT26           // Local address 1 match
+#define RXBUF_STAT_LOC2         BIT25           // Local address 2 match
+#define RXBUF_STAT_LOC3         BIT24           // Local address 3 match
+#define RXBUF_STAT_LOC4         BIT23           // Local address 4 match 
+#define RXBUF_STAT_LEN_MASK     0x7ff           // Len of frame including FCS
+
+#endif /* __AT91RM9200_EMAC_H__ */
+
Index: c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_gpio.h
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_gpio.h	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_gpio.h	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,400 @@
+/*
+ * AT91RM9200 GPIO definitions
+ *
+ * Copyright (c) 2002 by Cogent Computer Systems
+ * Written by Mike Kelly <mike@cogcomp.com>
+ *      
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+#ifndef AT91RM9200_GPIO_H
+#define AT91RM9200_GPIO_H
+
+#include <bits.h>
+
+// Register Offsets
+#define PIO_PER         0x00    // PIO Enable Register
+#define PIO_PDR         0x04    // PIO Disable Register
+#define PIO_PSR         0x08    // PIO Status Register
+#define PIO_OER         0x10    // Output Enable Register
+#define PIO_ODR         0x14    // Output Disable Registerr
+#define PIO_OSR         0x18    // Output Status Register
+#define PIO_IFER        0x20    // Input Filter Enable Register
+#define PIO_IFDR        0x24    // Input Filter Disable Register
+#define PIO_IFSR        0x28    // Input Filter Status Register
+#define PIO_SODR        0x30    // Set Output Data Register
+#define PIO_CODR        0x34    // Clear Output Data Register
+#define PIO_ODSR        0x38    // Output Data Status Register
+#define PIO_PDSR        0x3c    // Pin Data Status Register
+#define PIO_IER         0x40    // Interrupt Enable Register
+#define PIO_IDR         0x44    // Interrupt Disable Register
+#define PIO_IMR         0x48    // Interrupt Mask Register
+#define PIO_ISR         0x4c    // Interrupt Status Register
+#define PIO_MDER        0x50    // Multi-driver Enable Register
+#define PIO_MDDR        0x54    // Multi-driver Disable Register
+#define PIO_MDSR        0x58    // Multi-driver Status Register
+#define PIO_PUDR        0x60    // Pull-up Disable Register
+#define PIO_PUER        0x64    // Pull-up Enable Register
+#define PIO_PUSR        0x68    // Pad Pull-up Status Register
+#define PIO_ASR         0x70    // Select A Register
+#define PIO_BSR         0x74    // Select B Register
+#define PIO_ABSR        0x78    // AB Select Status Register
+#define PIO_OWER        0xA0    // Output Write Enable Register
+#define PIO_OWDR        0xA4    // Output Write Disable Register
+#define PIO_OWSR        0xA8    // Output Write Status Register
+
+
+// The AT91RM9200 GPIO's are spread across four 32-bit ports A-D.
+// To make it easier to interface with them and to eliminate the need
+// to track which GPIO is in which port, we     convert the Port x, Bit y
+// into a single GPIO number 0 - 127.
+//
+// Board specific defines will assign the board level signal to a
+// virutal GPIO.
+//
+// PORT A
+#define GPIO_0          BIT0    
+#define GPIO_1          BIT1    
+#define GPIO_2          BIT2    
+#define GPIO_3          BIT3    
+#define GPIO_4          BIT4    
+#define GPIO_5          BIT5    
+#define GPIO_6          BIT6    
+#define GPIO_7          BIT7    
+#define GPIO_8          BIT8    
+#define GPIO_9          BIT9    
+#define GPIO_10         BIT10
+#define GPIO_11         BIT11
+#define GPIO_12         BIT12
+#define GPIO_13         BIT13
+#define GPIO_14         BIT14
+#define GPIO_15         BIT15
+#define GPIO_16         BIT16
+#define GPIO_17         BIT17
+#define GPIO_18         BIT18
+#define GPIO_19         BIT19
+#define GPIO_20         BIT20
+#define GPIO_21         BIT21
+#define GPIO_22         BIT22
+#define GPIO_23         BIT23
+#define GPIO_24         BIT24
+#define GPIO_25         BIT25
+#define GPIO_26         BIT26
+#define GPIO_27         BIT27
+#define GPIO_28         BIT28
+#define GPIO_29         BIT29
+#define GPIO_30         BIT30
+#define GPIO_31         BIT31
+// PORT B
+#define GPIO_32         BIT0    
+#define GPIO_33         BIT1    
+#define GPIO_34         BIT2    
+#define GPIO_35         BIT3    
+#define GPIO_36         BIT4    
+#define GPIO_37         BIT5    
+#define GPIO_38         BIT6    
+#define GPIO_39         BIT7    
+#define GPIO_40         BIT8    
+#define GPIO_41         BIT9    
+#define GPIO_42         BIT10
+#define GPIO_43         BIT11
+#define GPIO_44         BIT12
+#define GPIO_45         BIT13
+#define GPIO_46         BIT14
+#define GPIO_47         BIT15
+#define GPIO_48         BIT16
+#define GPIO_49         BIT17
+#define GPIO_50         BIT18
+#define GPIO_51         BIT19
+#define GPIO_52         BIT20
+#define GPIO_53         BIT21
+#define GPIO_54         BIT22
+#define GPIO_55         BIT23
+#define GPIO_56         BIT24
+#define GPIO_57         BIT25
+#define GPIO_58         BIT26
+#define GPIO_59         BIT27
+#define GPIO_60         BIT28
+#define GPIO_61         BIT29
+#define GPIO_62         BIT30
+#define GPIO_63         BIT31
+// PORT C
+#define GPIO_64         BIT0    
+#define GPIO_65         BIT1    
+#define GPIO_66         BIT2    
+#define GPIO_67         BIT3    
+#define GPIO_68         BIT4    
+#define GPIO_69         BIT5    
+#define GPIO_70         BIT6    
+#define GPIO_71         BIT7    
+#define GPIO_72         BIT8    
+#define GPIO_73         BIT9    
+#define GPIO_74         BIT10
+#define GPIO_75         BIT11
+#define GPIO_76         BIT12
+#define GPIO_77         BIT13
+#define GPIO_78         BIT14
+#define GPIO_79         BIT15
+#define GPIO_80         BIT16
+#define GPIO_81         BIT17
+#define GPIO_82         BIT18
+#define GPIO_83         BIT19
+#define GPIO_84         BIT20
+#define GPIO_85         BIT21
+#define GPIO_86         BIT22
+#define GPIO_87         BIT23
+#define GPIO_88         BIT24
+#define GPIO_89         BIT25
+#define GPIO_90         BIT26
+#define GPIO_91         BIT27
+#define GPIO_92         BIT28
+#define GPIO_93         BIT29
+#define GPIO_94         BIT30
+#define GPIO_95         BIT31
+// PORT D
+#define GPIO_96         BIT0    
+#define GPIO_97         BIT1    
+#define GPIO_98         BIT2    
+#define GPIO_99         BIT3    
+#define GPIO_100        BIT4    
+#define GPIO_101        BIT5    
+#define GPIO_102        BIT6    
+#define GPIO_103        BIT7    
+#define GPIO_104        BIT8    
+#define GPIO_105        BIT9    
+#define GPIO_106        BIT10
+#define GPIO_107        BIT11
+#define GPIO_108        BIT12
+#define GPIO_109        BIT13
+#define GPIO_110        BIT14
+#define GPIO_111        BIT15
+#define GPIO_112        BIT16
+#define GPIO_113        BIT17
+#define GPIO_114        BIT18
+#define GPIO_115        BIT19
+#define GPIO_116        BIT20
+#define GPIO_117        BIT21
+#define GPIO_118        BIT22
+#define GPIO_119        BIT23
+#define GPIO_120        BIT24
+#define GPIO_121        BIT25
+#define GPIO_122        BIT26
+#define GPIO_123        BIT27
+#define GPIO_124        BIT28
+#define GPIO_125        BIT29
+#define GPIO_126        BIT30
+#define GPIO_127        BIT31
+
+// Most of the GPIO pins can have one of two alternate functions
+// in addition to being GPIO
+
+// Port A, Alternate Function A
+#define PIOA_ASR_MISO   BIT0    // SPI Master In (RX), Slave out
+#define PIOA_ASR_MOSI   BIT1    // SPI Master Out (TX), Slave In
+#define PIOA_ASR_SPCK   BIT2    // SPI Clock
+#define PIOA_ASR_NPCS0  BIT3    // SPI Chip Select 0
+#define PIOA_ASR_NPCS1  BIT4    // SPI Chip Select 1
+#define PIOA_ASR_NPCS2  BIT5    // SPI Chip Select 2
+#define PIOA_ASR_NPCS3  BIT6    // SPI Chip Select 3
+#define PIOA_ASR_ETXCK  BIT7    // EMAC TX Clock
+#define PIOA_ASR_ETXEN  BIT8    // EMAC TXEN
+#define PIOA_ASR_ETX0   BIT9    // EMAC TXD0
+#define PIOA_ASR_ETX1   BIT10   // EMAC TXD1 
+#define PIOA_ASR_ECRS   BIT11   // EMAC CRS
+#define PIOA_ASR_ERX0   BIT12   // EMAC RXD0
+#define PIOA_ASR_ERX1   BIT13   // EMAC RXD1
+#define PIOA_ASR_ERXER  BIT14   // EMAC RXER
+#define PIOA_ASR_EMDC   BIT15   // EMAC MDC
+#define PIOA_ASR_EMDIO  BIT16   // EMAC MDIO
+#define PIOA_ASR_TXD0   BIT17   // USART 0 Receive
+#define PIOA_ASR_RXD0   BIT18   // USART 0 Transmit
+#define PIOA_ASR_SCK0   BIT19   // USART 0 Clock
+#define PIOA_ASR_CTS0   BIT20   // USART 0 CTS
+#define PIOA_ASR_RTS0   BIT21   // USART 0 RTS
+#define PIOA_ASR_RXD2   BIT22   // USART 2 Receive
+#define PIOA_ASR_TXD2   BIT23   // USART 2 Transmit
+#define PIOA_ASR_SCK2   BIT24   // USART 2 Clock
+#define PIOA_ASR_TWD    BIT25   // Two-Wire (I2C) Data
+#define PIOA_ASR_TWCK   BIT26   // Two-Wire (I2C) Clock
+#define PIOA_ASR_MCCK   BIT27   // MMC/SD Card Clock
+#define PIOA_ASR_MCCDA  BIT28   // MMC/SD Card A Command
+#define PIOA_ASR_MCDA0  BIT29   // MMC/SD Card A Data 0
+#define PIOA_ASR_DRXD   BIT30   // Debug Uart Receive
+#define PIOA_ASR_DTXD   BIT31   // Debug Uart Transmit
+
+// Port A, Alternate Function B
+#define PIOA_BSR_PCK3   BIT0    // Peripheral Clock 3
+#define PIOA_BSR_PCK0   BIT1    // Peripheral Clock 0
+#define PIOA_BSR_IRQ4   BIT2    // IRQ4
+#define PIOA_BSR_IRQ5   BIT3    // IRQ5
+//#define PIOA_BSR_PCK1 BIT4    // Peripheral Clock 1 ***DUPLICATED at BIT24 ???
+#define PIOA_BSR_TXD3   BIT5    // USART 3 Transmit
+#define PIOA_BSR_RXD3   BIT6    // USART 3 Receive
+#define PIOA_BSR_PCK2   BIT7    // Peripheral Clock 2
+#define PIOA_BSR_MCCDB  BIT8    // MMC/SD Card B Command
+#define PIOA_BSR_MCDB0  BIT9    // MMC/SD Card B Data 0
+#define PIOA_BSR_MCDB1  BIT10   // MMC/SD Card B Data 1
+#define PIOA_BSR_MCDB2  BIT11   // MMC/SD Card B Data 2
+#define PIOA_BSR_MCDB3  BIT12   // MMC/SD C ard B Data 3
+#define PIOA_BSR_TCLK0  BIT13   // Timer 0 Clock
+#define PIOA_BSR_TCLK1  BIT14   // Timer 1 Clck
+#define PIOA_BSR_TCLK2  BIT15   // Timer 2 Clock
+#define PIOA_BSR_IRQ6   BIT16   // IRQ6
+#define PIOA_BSR_TIOA0  BIT17   // Timer 0 I/O A
+#define PIOA_BSR_TIOB0  BIT18   // Timer 0 I/O B
+#define PIOA_BSR_TIOA1  BIT19   // Timer 1 I/O A
+#define PIOA_BSR_TIOB1  BIT20   // Timer 1 I/O B
+#define PIOA_BSR_TIOA2  BIT21   // Timer 2 I/O A
+#define PIOA_BSR_TIOB2  BIT22   // Timer 2 I/O B
+#define PIOA_BSR_IRQ3   BIT23   // IRQ3
+#define PIOA_BSR_PCK1   BIT24   // Peripheral Clock 1   
+#define PIOA_BSR_IRQ2   BIT25   // IRQ2
+#define PIOA_BSR_IRQ1   BIT26   // IRQ1
+#define PIOA_BSR_TCLK3  BIT27   // Timer Block Clock 3 (docs only show 0-2?)
+#define PIOA_BSR_TCLK4  BIT28   // Timer Block Clock 4
+#define PIOA_BSR_TCLK5  BIT29   // Timer Block Clock 5
+#define PIOA_BSR_CTS2   BIT30   // USART 2 CTS
+#define PIOA_BSR_RTS2   BIT31   // USART 2 RTS
+
+// Port B, Function A
+#define PIOB_ASR_TF0    BIT0    // AC'97/I2S 0 Transmit Frame 
+#define PIOB_ASR_TK0    BIT1    // AC'97/I2S 0 Transmit Clock 
+#define PIOB_ASR_TD0    BIT2    // AC'97/I2S 0 Transmit Data
+#define PIOB_ASR_RD0    BIT3    // AC'97/I2S 0 Receive Data
+#define PIOB_ASR_RK0    BIT4    // AC'97/I2S 0 Receive Clock
+#define PIOB_ASR_RF0    BIT5    // AC'97/I2S 0 Receive Frame
+#define PIOB_ASR_TF1    BIT6    // AC'97/I2S 1 Transmit Frame 
+#define PIOB_ASR_TK1    BIT7    // AC'97/I2S 1 Transmit Clock 
+#define PIOB_ASR_TD1    BIT8    // AC'97/I2S 1 Transmit Data 
+#define PIOB_ASR_RD1    BIT9    // AC'97/I2S 1 Receive Data 
+#define PIOB_ASR_RK1    BIT10   // AC'97/I2S 1 Receive Clock 
+#define PIOB_ASR_RF1    BIT11   // AC'97/I2S 1 Receive Frame 
+#define PIOB_ASR_TF2    BIT12   // AC'97/I2S 1 Transmit Frame 
+#define PIOB_ASR_TK2    BIT13   // AC'97/I2S 1 Transmit Clock 
+#define PIOB_ASR_TD2    BIT14   // AC'97/I2S 1 Transmit Data  
+#define PIOB_ASR_RD2    BIT15   // AC'97/I2S 1 Receive Data  
+#define PIOB_ASR_RK2    BIT16   // AC'97/I2S 1 Receive Clock  
+#define PIOB_ASR_RF2    BIT17   // AC'97/I2S 1 Receive Frame  
+#define PIOB_ASR_RI1    BIT18   // USART 1 RI 
+#define PIOB_ASR_DTR1   BIT19   // USART 1 DTR
+#define PIOB_ASR_TXD1   BIT20   // USART 1 TXD
+#define PIOB_ASR_RXD1   BIT21   // USART 1 RXD
+#define PIOB_ASR_SCK1   BIT22   // USART 1 SCK
+#define PIOB_ASR_DCD1   BIT23   // USART 1 DCD
+#define PIOB_ASR_CTS1   BIT24   // USART 1 CTS
+#define PIOB_ASR_DSR1   BIT25   // USART 1 DSR
+#define PIOB_ASR_RTS1   BIT26   // USART 1 RTS
+#define PIOB_ASR_PCK0   BIT27   // Peripheral Clock 0 
+#define PIOB_ASR_FIQ    BIT28   // FIQ
+#define PIOB_ASR_IRQ0   BIT29   // IRQ0
+
+// Port B, Function B
+#define PIOB_BSR_RTS3   BIT0    // USART 3
+#define PIOB_BSR_CTS3   BIT1    // USART 3
+#define PIOB_BSR_SCK3   BIT2    // USART 3
+#define PIOB_BSR_MCDA1  BIT3    // MMC/SD Card A, Data 1
+#define PIOB_BSR_MCDA2  BIT4    // MMC/SD Card A, Data 2
+#define PIOB_BSR_MCDA3  BIT5    // MMC/SD Card A, Data 3
+#define PIOB_BSR_TIOA3  BIT6    // Timer 3 IO A
+#define PIOB_BSR_TIOB3  BIT7    // Timer 3 IO B
+#define PIOB_BSR_TIOA4  BIT8    // Timer 4 IO A
+#define PIOB_BSR_TIOB4  BIT9    // Timer 4 IO B
+#define PIOB_BSR_TIOA5  BIT10   // Timer 5 IO A
+#define PIOB_BSR_TIOB5  BIT11   // Timer 5 IO B
+#define PIOB_BSR_ETX2   BIT12   // EMAC TXD2
+#define PIOB_BSR_ETX3   BIT13   // EMAC TXD3
+#define PIOB_BSR_ETXER  BIT14   // EMAC TXER
+#define PIOB_BSR_ERX2   BIT15   // EMAC RXD2
+#define PIOB_BSR_ERX3   BIT16   // EMAC RXD3
+#define PIOB_BSR_ERXDV  BIT17   // EMAC RXDV
+#define PIOB_BSR_ECOL   BIT18   // EMAC COL
+#define PIOB_BSR_ERXCK  BIT19   // EMAC RX Clock
+#define PIOB_BSR_EF100  BIT25   // EMAC Speed 100 (RMII Only)
+
+// Port C, Alternate Function A
+#define PIOC_ASR_BFCK   BIT0    // Burst Flash Clock
+#define PIOC_ASR_BFRDY  BIT1    // Burst Flash Ready or SMC Card OE
+#define PIOC_ASR_BFAVD  BIT2    // Burst Flash Address Valid
+#define PIOC_ASR_BFBAA  BIT3    // Burst Flash Address Advance or SMC Card WE
+#define PIOC_ASR_BFOE   BIT4    // Burst Flash OE
+#define PIOC_ASR_BFWE   BIT5    // Burst Flash WE
+#define PIOC_ASR_NWAIT  BIT6    // WAIT Input
+#define PIOC_ASR_A23    BIT7    // A23
+#define PIOC_ASR_A24    BIT8    // A24
+#define PIOC_ASR_A25    BIT9    // A25 or Compact Flash R/W
+#define PIOC_ASR_NCS4   BIT10   // CS4 or Compact Flash CS
+#define PIOC_ASR_NCS5   BIT11   // CS5 or Compact Flash CE1
+#define PIOC_ASR_NCS6   BIT12   // CS6 or Compact Flash CE2
+#define PIOC_ASR_NCS7   BIT13   // CS7
+#define PIOC_ASR_D16    BIT16   // Databus Bit 16
+#define PIOC_ASR_D17    BIT17   // Databus Bit 17
+#define PIOC_ASR_D18    BIT18   // Databus Bit 18
+#define PIOC_ASR_D19    BIT19   // Databus Bit 19
+#define PIOC_ASR_D20    BIT20   // Databus Bit 20
+#define PIOC_ASR_D21    BIT21   // Databus Bit 21
+#define PIOC_ASR_D22    BIT22   // Databus Bit 22
+#define PIOC_ASR_D23    BIT23   // Databus Bit 23
+#define PIOC_ASR_D24    BIT24   // Databus Bit 24
+#define PIOC_ASR_D25    BIT25   // Databus Bit 25
+#define PIOC_ASR_D26    BIT26   // Databus Bit 26
+#define PIOC_ASR_D27    BIT27   // Databus Bit 27
+#define PIOC_ASR_D28    BIT28   // Databus Bit 28
+#define PIOC_ASR_D29    BIT29   // Databus Bit 29
+#define PIOC_ASR_D30    BIT30   // Databus Bit 30
+#define PIOC_ASR_D31    BIT31   // Databus Bit 31
+
+// Port C, Alternate Function B - None
+
+// Port D, Alternate Function A
+#define PIOD_ASR_ETX0   BIT0    // EMAC TXD0
+#define PIOD_ASR_ETX1   BIT1    // EMAC TXD1
+#define PIOD_ASR_ETX2   BIT2    // EMAC TXD2
+#define PIOD_ASR_ETX3   BIT3    // EMAC TXD3
+#define PIOD_ASR_ETXEN  BIT4    // EMAC TXEN
+#define PIOD_ASR_ETXER  BIT5    // EMAC TXER
+#define PIOD_ASR_DTXD   BIT6    // Debug UART Transmit
+#define PIOD_ASR_PCK0   BIT7    // Peripheral Clock 0
+#define PIOD_ASR_PCK1   BIT8    // Peripheral Clock 1
+#define PIOD_ASR_PCK2   BIT9    // Peripheral Clock 2
+#define PIOD_ASR_PCK3   BIT10   // Peripheral Clock 3
+#define PIOD_ASR_TD0    BIT15   // AC'97/I2S 0 Transmit Data
+#define PIOD_ASR_TD1    BIT16   // AC'97/I2S 1 Transmit Data
+#define PIOD_ASR_TD2    BIT17   // AC'97/I2S 2 Transmit Data
+#define PIOD_ASR_NPCS1  BIT18   // SPI Chip Select 1
+#define PIOD_ASR_NPCS2  BIT19   // SPI Chip Select 2
+#define PIOD_ASR_NPCS3  BIT20   // SPI Chip Select 3
+#define PIOD_ASR_RTS0   BIT21   // USART 0 RTS
+#define PIOD_ASR_RTS1   BIT22   // USART 1 RTS
+#define PIOD_ASR_RTS2   BIT23   // USART 2 RTS
+#define PIOD_ASR_RTS3   BIT24   // USART 3 RTS
+#define PIOD_ASR_DTR1   BIT25   // USART 1 DTR
+                   
+// Port D, Alternate Function B
+                
+#define PIOC_ASR_TSYNC  BIT7    // ETM Sync     
+#define PIOC_ASR_TCLK   BIT8    // ETM Clock
+#define PIOC_ASR_TPS0   BIT9    // ETM Processor Status 0
+#define PIOC_ASR_TPS1   BIT10   // ETM Processor Status 1
+#define PIOC_ASR_TPS2   BIT11   // ETM Processor Status 2
+#define PIOC_ASR_TPK0   BIT12   // ETM Packet Data 0
+#define PIOC_ASR_TPK1   BIT13   // ETM Packet Data 1
+#define PIOC_ASR_TPK2   BIT14   // ETM Packet Data 2
+#define PIOC_ASR_TPK3   BIT15   // ETM Packet Data 3
+#define PIOC_ASR_TPK4   BIT16   // ETM Packet Data 4
+#define PIOC_ASR_TPK5   BIT17   // ETM Packet Data 5
+#define PIOC_ASR_TPK6   BIT18   // ETM Packet Data 6
+#define PIOC_ASR_TPK7   BIT19   // ETM Packet Data 7
+#define PIOC_ASR_TPK8   BIT20   // ETM Packet Data 8
+#define PIOC_ASR_TPK9   BIT21   // ETM Packet Data 9
+#define PIOC_ASR_TPK10  BIT22   // ETM Packet Data 10
+#define PIOC_ASR_TPK11  BIT23   // ETM Packet Data 11
+#define PIOC_ASR_TPK12  BIT24   // ETM Packet Data 12
+#define PIOC_ASR_TPK13  BIT25   // ETM Packet Data 13
+#define PIOC_ASR_TPK14  BIT26   // ETM Packet Data 14
+#define PIOC_ASR_TPK15  BIT27   // ETM Packet Data 15
+
+#endif
Index: c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_mem.h
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_mem.h	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_mem.h	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,118 @@
+/*
+ * AT91RM9200 Memory Controller definitions
+ *
+ * Copyright (c) 2002 by Cogent Computer Systems
+ * Written by Mike Kelly <mike@cogcomp.com>
+ *      
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+#ifndef AT91RM9200_MEM_H
+#define AT91RM9200_MEM_H
+
+// *****************************************************************************
+// External Bus Interface Unit
+// *****************************************************************************
+#define EBI_CSA                                 0x00    // Chip Select Assignment Register
+#define EBI_CFGR                                0x04    // Configuration Register
+
+// Bit Defines
+// EBI_CSA - Chip Select Assignment Register
+#define EBI_CSA_CS4_CF                  BIT4    // 1 = CS4-6 are assigned to Compact Flash, 0 = Chip Selects
+#define EBI_CSA_CS3_SMM                 BIT3    // 1 = CS3 is assigned to SmartMedia, 0 = Chip Select
+#define EBI_CSA_CS1_SDRAM               BIT1    // 1 = CS1 is assigned to SDRAM, 0 = Chip Select
+#define EBI_CSA_CS0_BF                  BIT0    // 1 = CS0 is assigned to Burst Flash, 0 = Chip Select
+
+// EBI_CFGR     - Configuration Register
+#define EBI_CFGR_DBPU                   BIT0    // 1 = Disable D0-15 pullups                            
+
+// *****************************************************************************
+// Static Memory Interface Unit
+// *****************************************************************************
+#define SMC_CSR0                                0x00    // Chip Select Register 0 
+#define SMC_CSR1                                0x04    // Chip Select Register 1 
+#define SMC_CSR2                                0x08    // Chip Select Register 2 
+#define SMC_CSR3                                0x0C    // Chip Select Register 3 
+#define SMC_CSR4                                0x10    // Chip Select Register 4 
+#define SMC_CSR5                                0x14    // Chip Select Register 5 
+#define SMC_CSR6                                0x18    // Chip Select Register 6 
+#define SMC_CSR7                                0x1C    // Chip Select Register 7 
+
+// Bit Defines
+// SMC_CSR0 -7 - Chip Selects 0 - 7 Register
+#define SMC_CSR_RWHOLD(_x_)             ((_x_ & 0x3) << 28)     // Hold CS after R/W strobes
+#define SMC_CSR_RWSETUP(_x_)    ((_x_ & 0x3) << 24)     // Setup CS before R/W strobes
+#define SMC_CSR_ACSS_0                  (0 << 16)                               // Setup/Hold Address 0 clocks before/after CS
+#define SMC_CSR_ACSS_1                  (1 << 16)                               // Setup/Hold Address 1 clock before/after CS
+#define SMC_CSR_ACSS_2                  (2 << 16)                               // Setup/Hold Address 2 clocks before/after CS
+#define SMC_CSR_ACSS_3                  (3 << 16)                               // Setup/Hold Address 3 clocks before/after CS
+#define SMC_CSR_DRP_NORMAL              0                                               // 0 = normal read protocol
+#define SMC_CSR_DRP_EARLY               BIT15                                   // 1 = early read protocol
+#define SMC_CSR_DBW_16                  (1 << 13)                               // CS DataBus Width = 16-Bits
+#define SMC_CSR_DBW_8                   (2 << 13)                               // CS DataBus Width = 8 Bits
+#define SMC_CSR_BAT_16_1                0                                               // Single 16-Bit device (when DBW is 16)
+#define SMC_CSR_BAT_16_2                BIT12                                   // Dual 8-Bit devices (when DBW is 16)
+#define SMC_CSR_TDF(_x_)                ((_x_ & 0xf) << 8)              // Intercycle Data Float Time
+#define SMC_CSR_WSEN                    BIT7                                    // 1 = wait states are enabled
+#define SMC_CSR_NWS(_x_)                ((_x_ & 0x7f) << 0)     // Wait States + 1
+
+// *****************************************************************************
+// SDRAM Memory Interface Unit
+// *****************************************************************************
+#define SDRC_MR                                 0x00            // Mode Register
+#define SDRC_TR                                 0x04            // Refresh Timer Register
+#define SDRC_CR                                 0x08            // Configuration Register
+#define SDRC_SRR                                0x0C            // Self Refresh Register
+#define SDRC_LPR                                0x10            // Low Power Register
+#define SDRC_IER                                0x14            // Interrupt Enable Register
+#define SDRC_IDR                                0x18            // Interrupt Disable Register
+#define SDRC_IMR                                0x1C            // Interrupt Mask Register
+#define SDRC_ISR                                0x20            // Interrupt Status Register
+
+// Bit Defines
+// SDRC_MR - Mode Register
+#define SDRC_MR_DBW_16                  BIT4            // 1 = SDRAM is 16-bits wide, 0 = 32-bits
+#define SDRC_MR_NORM                    (0 << 0)        // Normal Mode - All accesses to SDRAM are decoded normally
+#define SDRC_MR_NOP                             (1 << 0)        // NOP Command is sent to SDRAM
+#define SDRC_MR_PRE                             (2 << 0)        // Precharge All Command is sent to SDRAM
+#define SDRC_MR_MRS                             (3 << 0)        // Mode Register Set Command is sent to SDRAM
+#define SDRC_MR_REF                             (4 << 0)        // Refresh Command is sent to SDRAM
+
+// SDRC_TR - Refresh Timer Register
+#define SDRC_TR_COUNT(_x_)              ((_x_ & 0xfff) << 0)
+
+// SDRC_CR - Configuration Register
+#define SDRC_CR_TXSR(_x_)               ((_x_ & 0xf) << 27)     // CKE to ACT Time
+#define SDRC_CR_TRAS(_x_)               ((_x_ & 0xf) << 23)     // ACT to PRE Time
+#define SDRC_CR_TRCD(_x_)               ((_x_ & 0xf) << 19)     // RAS to CAS Time
+#define SDRC_CR_TRP(_x_)                ((_x_ & 0xf) << 15)     // PRE to ACT Time
+#define SDRC_CR_TRC(_x_)                ((_x_ & 0xf) << 11)     // REF to ACT Time
+#define SDRC_CR_TWR(_x_)                ((_x_ & 0xf) << 7)      // Write Recovery Time
+#define SDRC_CR_CAS_2                   (2 << 5)        // Cas Delay = 2, this is the only supported value
+#define SDRC_CR_NB_2                    0                       // 2 Banks per device
+#define SDRC_CR_NB_4                    BIT4            // 4 Banks per device
+#define SDRC_CR_NR_11                   (0 << 2)        // Number of rows = 11
+#define SDRC_CR_NR_12                   (1 << 2)        // Number of rows = 12
+#define SDRC_CR_NR_13                   (2 << 2)        // Number of rows = 13
+#define SDRC_CR_NC_8                    (0 << 0)        // Number of columns = 8
+#define SDRC_CR_NC_9                    (1 << 0)        // Number of columns = 9
+#define SDRC_CR_NC_10                   (2 << 0)        // Number of columns = 10
+#define SDRC_CR_NC_11                   (3 << 0)        // Number of columns = 11
+
+// SDRC_SRR - Self Refresh Register
+#define SDRC_SRR_SRCB                   BIT0            // 1 = Enter Self Refresh
+
+// SDRC_LPR - Low Power Register
+#define SDRC_LPR_LPCB                   BIT0            // 1 = De-assert CKE between accesses
+
+// SDRC_IER - Interrupt Enable Register
+// SDRC_IDR - Interrupt Disable Register
+// SDRC_ISR - Interrupt Mask Register
+// SDRC_IMR - Interrupt Mask Register
+#define SDRC_INT_RES                    BIT0            // Refresh Error Status
+
+#endif
Index: c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_pmc.h
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_pmc.h	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_pmc.h	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,172 @@
+/*
+ * AT91RM9200 Power Management and Clock definitions
+ *
+ * Copyright (c) 2002 by Cogent Computer Systems
+ * Written by Mike Kelly <mike@cogcomp.com>
+ *      
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+#ifndef __AT91RM9200_PMC_H__
+#define __AT91RM9200_PMC_H__
+
+#include <bits.h>
+
+// *****************************************************************************
+// Power Management and Clock Control Register Offsets
+// *****************************************************************************
+int at91rm9200_get_mainclk(void);
+int at91rm9200_get_slck(void);
+int at91rm9200_get_mck(void);
+
+
+#define PMC_SCER        0x00    // System Clock Enable Register
+#define PMC_SCDR        0x04    // System Clock Disable Register
+#define PMC_SCSR        0x08    // System Clock Status Register
+#define PMC_PCER        0x10    // Peripheral Clock Enable Register
+#define PMC_PCDR        0x14    // Peripheral Clock Disable Register
+#define PMC_PCSR        0x18    // Peripheral Clock Status Register
+#define PMC_MOR         0x20    // Main Oscillator Register
+#define PMC_MCFR        0x24    // Main Clock  Frequency Register
+#define PMC_PLLAR       0x28    // PLL A Register
+#define PMC_PLLBR       0x2C    // PLL B Register
+#define PMC_MCKR        0x30    // Master Clock Register
+#define PMC_PCKR0       0x40    // Programmable Clock Register 0
+#define PMC_PCKR1       0x44    // Programmable Clock Register 1
+#define PMC_PCKR2       0x48    // Programmable Clock Register 2
+#define PMC_PCKR3       0x4C    // Programmable Clock Register 3
+#define PMC_PCKR4       0x50    // Programmable Clock Register 4
+#define PMC_PCKR5       0x54    // Programmable Clock Register 5
+#define PMC_PCKR6       0x58    // Programmable Clock Register 6
+#define PMC_PCKR7       0x5C    // Programmable Clock Register 7
+#define PMC_IER         0x60    // Interrupt Enable Register
+#define PMC_IDR         0x64    // Interrupt Disable Register
+#define PMC_SR          0x68    // Status Register
+#define PMC_IMR         0x6C    // Interrupt Mask Register
+
+// Bit Defines
+
+// PMC_SCDR - System Clock Disable Register
+// PMC_SCSR - System Clock Status Register
+// PMC_SCER - System Clock Enable Register
+#define PMC_SCR_PCK7                    BIT15
+#define PMC_SCR_PCK6                    BIT14
+#define PMC_SCR_PCK5                    BIT13
+#define PMC_SCR_PCK4                    BIT12
+#define PMC_SCR_PCK3                    BIT11
+#define PMC_SCR_PCK2                    BIT10
+#define PMC_SCR_PCK1                    BIT9
+#define PMC_SCR_PCK0                    BIT8
+#define PMC_SCR_UHP                             BIT4
+#define PMC_SCR_MCKUDP                  BIT2
+#define PMC_SCR_UDP                     BIT1
+#define PMC_SCR_PCK                     BIT0
+
+// PMC_PCER - Peripheral Clock Enable Register
+// PMC_PCDR - Peripheral Clock Disable Register
+// PMC_PCSR - Peripheral Clock Status Register
+#define PMC_PCR_PID_EMAC                BIT24           // Ethernet Peripheral Clock
+#define PMC_PCR_PID_UHP                 BIT23           // USB Host Ports Peripheral Clock
+#define PMC_PCR_PID_TC5                 BIT22           // Timer/Counter 5 Peripheral Clock
+#define PMC_PCR_PID_TC4                 BIT21           // Timer/Counter 4 Peripheral Clock
+#define PMC_PCR_PID_TC3                 BIT20           // Timer/Counter 3 Peripheral Clock
+#define PMC_PCR_PID_TC2                 BIT19           // Timer/Counter 2 Peripheral Clock
+#define PMC_PCR_PID_TC1                 BIT18           // Timer/Counter 1 Peripheral Clock
+#define PMC_PCR_PID_TC0                 BIT17           // Timer/Counter 0 Peripheral Clock
+#define PMC_PCR_PID_SSC2                BIT16           // Synchronous Serial 2 Peripheral Clock
+#define PMC_PCR_PID_SSC1                BIT15           // Synchronous Serial 1 Peripheral Clock
+#define PMC_PCR_PID_SSC0                BIT14           // Synchronous Serial 0 Peripheral Clock
+#define PMC_PCR_PID_SPI                 BIT13           // Serial Peripheral Interface Peripheral Clock
+#define PMC_PCR_PID_TWI                 BIT12           // Two-Wire Interface Peripheral Clock
+#define PMC_PCR_PID_UDP                 BIT11           // USB Device Port Peripheral Clock
+#define PMC_PCR_PID_MCI                 BIT10           // MMC/SD Card Peripheral Clock
+#define PMC_PCR_PID_US3                 BIT9            // USART 3 Peripheral Clock
+#define PMC_PCR_PID_US2                 BIT8            // USART 2 Peripheral Clock
+#define PMC_PCR_PID_US1                 BIT7            // USART 1 Peripheral Clock
+#define PMC_PCR_PID_US0                 BIT6            // USART 0 Peripheral Clock
+#define PMC_PCR_PID_PIOD                BIT5            // Parallel I/O D Peripheral Clock
+#define PMC_PCR_PID_PIOC                BIT4            // Parallel I/O C Peripheral Clock
+#define PMC_PCR_PID_PIOB                BIT3            // Parallel I/O B Peripheral Clock
+#define PMC_PCR_PID_PIOA                BIT2            // Parallel I/O A Peripheral Clock
+
+// PMC_MOR - Main Oscillator Register
+#define PMC_MOR_MOSCEN                  BIT0
+
+// PMC_MCFR - Main Clock  Frequency Register
+#define PMC_MCFR_MAINRDY                BIT16
+
+// PMC_PLLAR - PLL A Register
+#define PMC_PLLAR_MUST_SET              BIT29                                   // This bit must be set according to the docs
+#define PMC_PLLAR_MUL(_x_)              ((_x_ & 0x7ff) << 16)   // Multiplier   
+#define PMC_PLLAR_MUL_MASK              (0x7ff << 16)   // Multiplier mask
+
+#define PMC_PLLAR_OUT_80_160    (0 << 14)                               // select when PLL frequency is 80-160 Mhz
+#define PMC_PLLAR_OUT_150_240   (2 << 14)                               // select when PLL frequency is 150-240 Mhz
+#define PMC_PLLAR_DIV(_x_)              ((_x_ & 0xff) << 0)             // Divider
+#define PMC_PLLAR_DIV_MASK              (0xff)          // Divider mask
+
+// PMC_PLLBR - PLL B Register
+#define PMC_PLLBR_USB_96M               BIT28                                   // Set when PLL is 96Mhz to divide it by 2 for USB
+#define PMC_PLLBR_MUL(_x_)              ((_x_ & 0x7ff) << 16)   // Multiplier   
+#define PMC_PLLBR_MUL_MASK              (0x7ff << 16)   // Multiplier mask
+#define PMC_PLLBR_OUT_80_160    (0 << 14)                               // select when PLL frequency is 80-160 Mhz
+#define PMC_PLLBR_OUT_150_240   (2 << 14)                               // select when PLL frequency is 150-240 Mhz
+#define PMC_PLLBR_DIV(_x_)              ((_x_ & 0xff) << 0)             // Divider
+#define PMC_PLLBR_DIV_MASK              (0xff)          // Divider mask
+
+// PMC_MCKR - Master Clock Register
+#define PMC_MCKR_MDIV_MASK              (3 << 8)                                // for masking out the MDIV field
+#define PMC_MCKR_MDIV_1                 (0 << 8)                                // MCK = Core/1
+#define PMC_MCKR_MDIV_2                 (1 << 8)                                // MCK = Core/2
+#define PMC_MCKR_MDIV_3                 (2 << 8)                                // MCK = Core/3
+#define PMC_MCKR_MDIV_4                 (3 << 8)                                // MCK = Core/4
+#define PMC_MCKR_PRES_MASK              (7 << 2)                                // for masking out the PRES field
+#define PMC_MCKR_PRES_1                 (0 << 2)                                // Core = CSS/1
+#define PMC_MCKR_PRES_2                 (1 << 2)                                // Core = CSS/2
+#define PMC_MCKR_PRES_4                 (2 << 2)                                // Core = CSS/4
+#define PMC_MCKR_PRES_8                 (3 << 2)                                // Core = CSS/8
+#define PMC_MCKR_PRES_16                (4 << 2)                                // Core = CSS/16
+#define PMC_MCKR_PRES_32                (5 << 2)                                // Core = CSS/32
+#define PMC_MCKR_PRES_64                (6 << 2)                                // Core = CSS/64
+#define PMC_MCKR_CSS_MASK               (3 << 0)                                // for masking out the CSS field
+#define PMC_MCKR_CSS_SLOW               (0 << 0)                                // Core Source = Slow Clock
+#define PMC_MCKR_CSS_MAIN               (1 << 0)                                // Core Source = Main Oscillator
+#define PMC_MCKR_CSS_PLLA               (2 << 0)                                // Core Source = PLL A
+#define PMC_MCKR_CSS_PLLB               (3 << 0)                                // Core Source = PLL B
+
+// PMC_PCKR0 - 7 - Programmable Clock Register 0
+#define PMC_PCKR_PRES_1                 (0 << 2)                                // Peripheral Clock = CSS/1
+#define PMC_PCKR_PRES_2                 (1 << 2)                                // Peripheral Clock = CSS/2
+#define PMC_PCKR_PRES_4                 (2 << 2)                                // Peripheral Clock = CSS/4
+#define PMC_PCKR_PRES_8                 (3 << 2)                                // Peripheral Clock = CSS/8
+#define PMC_PCKR_PRES_16                (4 << 2)                                // Peripheral Clock = CSS/16
+#define PMC_PCKR_PRES_32                (5 << 2)                                // Peripheral Clock = CSS/32
+#define PMC_PCKR_PRES_64                (6 << 2)                                // Peripheral Clock = CSS/64
+#define PMC_PCKR_CSS_SLOW               (0 << 0)                                // Peripheral Clock Source = Slow Clock
+#define PMC_PCKR_CSS_MAIN               (1 << 0)                                // Peripheral Clock Source = Main Oscillator
+#define PMC_PCKR_CSS_PLLA               (2 << 0)                                // Peripheral Clock Source = PLL A
+#define PMC_PCKR_CSS_PLLB               (3 << 0)                                // Peripheral Clock Source = PLL B
+
+// PMC_IER - Interrupt Enable Register
+// PMC_IDR - Interrupt Disable Register
+// PMC_SR - Status Register
+// PMC_IMR - Interrupt Mask Register
+#define PMC_INT_PCK7_RDY                BIT15
+#define PMC_INT_PCK6_RDY                BIT14
+#define PMC_INT_PCK5_RDY                BIT13
+#define PMC_INT_PCK4_RDY                BIT12
+#define PMC_INT_PCK3_RDY                BIT11
+#define PMC_INT_PCK2_RDY                BIT10
+#define PMC_INT_PCK1_RDY                BIT9
+#define PMC_INT_PCK0_RDY                BIT8
+#define PMC_INT_MCK_RDY                 BIT3
+#define PMC_INT_LOCKB                   BIT2
+#define PMC_INT_LCKA                    BIT1
+#define PMC_INT_MOSCS                   BIT0
+
+
+#endif
Index: c/src/lib/libcpu/arm/at91rm9200/include/bits.h
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/include/bits.h	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/include/bits.h	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,51 @@
+/*
+ * Bit position definitions
+ *
+ * Copyright (c) 2002 by Cogent Computer Systems
+ * Written by Mike Kelly <mike@cogcomp.com>
+ *      
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+#ifndef __BITS_H__
+#define __BITS_H__
+
+#define BIT0				0x00000001
+#define BIT1				0x00000002
+#define BIT2				0x00000004
+#define BIT3				0x00000008
+#define BIT4				0x00000010
+#define BIT5				0x00000020
+#define BIT6				0x00000040
+#define BIT7				0x00000080
+#define BIT8				0x00000100
+#define BIT9				0x00000200
+#define BIT10				0x00000400
+#define BIT11				0x00000800
+#define BIT12				0x00001000
+#define BIT13				0x00002000
+#define BIT14				0x00004000
+#define BIT15				0x00008000
+#define BIT16				0x00010000
+#define BIT17				0x00020000
+#define BIT18				0x00040000
+#define BIT19				0x00080000
+#define BIT20				0x00100000
+#define BIT21				0x00200000
+#define BIT22				0x00400000
+#define BIT23				0x00800000
+#define BIT24				0x01000000
+#define BIT25				0x02000000
+#define BIT26				0x04000000
+#define BIT27				0x08000000
+#define BIT28				0x10000000
+#define BIT29				0x20000000
+#define BIT30				0x40000000
+#define BIT31				0x80000000
+
+#endif /* __BITS_H__ */
+
Index: c/src/lib/libcpu/arm/at91rm9200/irq/.cvsignore
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/irq/.cvsignore	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/irq/.cvsignore	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,14 @@
+Makefile
+Makefile.in
+aclocal.m4
+autom4te.cache
+config.cache
+config.guess
+config.log
+config.status
+config.sub
+configure
+depcomp
+install-sh
+missing
+mkinstalldirs
Index: c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_asm.S
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_asm.S	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_asm.S	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,38 @@
+/*
+ * Atmel AT91RM9200 Interrupt handler
+ *
+ * Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com>
+ *      
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *
+ *  $Id$
+ */
+#define __asm__
+        
+        .globl ExecuteITHandler
+ExecuteITHandler :
+/*
+ * Look at interrupt status register to determine source.
+ * From source, determine offset into expanded vector table
+ * and load handler address into r0.
+ */
+        ldr     r0, =0xFFFFF100   /* AIC_CTL_BASE + AIC_IVR */
+        ldr     r1, [r0]                
+        str     r1, [r0]          /* write back in case we are using protect */
+
+        stmdb   sp!,{lr}
+        ldr     lr, =IRQ_return   /* prepare the return from handler  */
+
+        mov     pc, r1            /* execute handler */
+
+IRQ_return:
+        ldr   r2, =0xFFFFF130     /* AIC_CTL_BASE + AIC_EIOCR */
+        str   r1, [r2]
+       
+        ldmia sp!,{lr}
+
+        mov pc, lr
Index: c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_init.c
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_init.c	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_init.c	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,29 @@
+/*
+ * Atmel AT91RM9200 Interrupt handler
+ *
+ * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
+ *      
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *
+ *  $Id$
+ */
+#include <irq.h>
+#include <bsp.h>
+#include <at91rm9200.h>
+
+extern void default_int_handler();
+
+/* 
+ * Interrupt system initialization. Disable interrupts, clear 
+ * any that are pending.
+ */
+void BSP_rtems_irq_mngt_init()
+{
+    /* disable all interrupts */
+    AIC_CTL_REG(AIC_IDCR) = 0xffffffff;
+}
+
Index: c/src/lib/libcpu/arm/at91rm9200/irq/irq.c
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/irq/irq.c	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/irq/irq.c	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,115 @@
+/*
+ * Atmel AT91RM9200 Interrupt handler
+ *
+ * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
+ *      
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+#include <bsp.h>
+#include <irq.h>
+#include <rtems/score/thread.h>
+#include <rtems/score/apiext.h>
+#include <at91rm9200.h>
+
+/*
+ * This function check that the value given for the irq line
+ * is valid.
+ */
+static int isValidInterrupt(int irq)
+{
+    if ( (irq < 0) || (irq >= AT91RM9200_MAX_INT)) {
+        return 0;
+    }
+    return 1;
+}
+
+/*
+ * Installs the interrupt handler.
+ */
+int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
+{
+    rtems_interrupt_level level;
+    
+    if (!isValidInterrupt(irq->name)) {
+        return 0;
+    }
+    
+    /*
+     * Check if default handler is actually connected. If not, issue 
+     * an error. Note: irq->name is a number corresponding to the 
+     * sources PID (see the at91rm9200_pid for this mapping).  We 
+     * convert it to a long word offset to get source's vector register 
+     */
+    if (AIC_SVR_REG(irq->name * 4) != default_int_handler) {
+        return 0;
+    }
+    
+    _CPU_ISR_Disable(level);
+    
+    /*
+     * store the new handler
+     */
+    AIC_SVR_REG(irq->name * 4) = irq->hdl;
+    
+    /*
+     * unmask interrupt
+     */
+    AIC_CTL_REG(AIC_IECR) = 1 << irq->name;
+    
+    /*
+     * Enable interrupt on device
+     */
+    if(irq->on) {
+        irq->on(irq);
+    }
+    
+    _CPU_ISR_Enable(level);
+    
+    return 1;
+}
+
+/* 
+ * Remove and interrupt handler
+ */
+int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
+{
+    rtems_interrupt_level level;
+  
+    if (!isValidInterrupt(irq->name)) {
+        return 0;
+    }
+
+    /*
+     * Check if the handler is actually connected. If not, issue an error.
+     */
+    if (AIC_SVR_REG(irq->name * 4) != irq->hdl) {
+      return 0;
+    }
+    _CPU_ISR_Disable(level);
+
+    /*
+     * mask interrupt
+     */
+    AIC_CTL_REG(AIC_IDCR) = 1 << irq->name;
+    
+    /*
+     * Disable interrupt on device
+     */
+    if(irq->off) {
+        irq->off(irq);
+    }
+
+    /*
+     * restore the default irq value
+     */
+    AIC_SVR_REG(irq->name * 4) = default_int_handler;
+    
+    _CPU_ISR_Enable(level);
+
+    return 1;
+}
Index: c/src/lib/libcpu/arm/at91rm9200/irq/irq.h
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/irq/irq.h	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/irq/irq.h	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,137 @@
+/*
+ * Interrupt handler Header file
+ *
+ * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
+ *      
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *
+ *  $Id$
+ */
+
+#ifndef __IRQ_H__
+#define __IRQ_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __asm__
+
+/*
+ * Include some preprocessor value also used by assember code
+ */
+  
+#include <rtems.h>
+#include <at91rm9200.h>
+
+extern void default_int_handler();
+/***********************************************************************
+ * Constants
+ **********************************************************************/
+/* enum of the possible interrupt sources on the AT91RM9200 */
+typedef enum {
+    AT91RM9200_INT_FIQ  = 0,
+    AT91RM9200_INT_SYSIRQ,
+    AT91RM9200_INT_PIOA,
+    AT91RM9200_INT_PIOB,
+    AT91RM9200_INT_PIOC,
+    AT91RM9200_INT_PIOD,
+    AT91RM9200_INT_US0,
+    AT91RM9200_INT_US1,
+    AT91RM9200_INT_US2,
+    AT91RM9200_INT_US3,
+    AT91RM9200_INT_MCI,
+    AT91RM9200_INT_UDP,
+    AT91RM9200_INT_TWI,
+    AT91RM9200_INT_SPI,
+    AT91RM9200_INT_SSC0,
+    AT91RM9200_INT_SSC1,
+    AT91RM9200_INT_SSC2,
+    AT91RM9200_INT_TC0,
+    AT91RM9200_INT_TC1,
+    AT91RM9200_INT_TC2,
+    AT91RM9200_INT_TC3,
+    AT91RM9200_INT_TC4,
+    AT91RM9200_INT_TC5,
+    AT91RM9200_INT_UHP,
+    AT91RM9200_INT_EMAC,
+    AT91RM9200_INT_IRQ0,
+    AT91RM9200_INT_IRQ1,
+    AT91RM9200_INT_IRQ2,
+    AT91RM9200_INT_IRQ3,
+    AT91RM9200_INT_IRQ4,
+    AT91RM9200_INT_IRQ5,
+    AT91RM9200_INT_IRQ6,
+    AT91RM9200_MAX_INT
+} rtems_irq_symbolic_name;
+
+/* vector table used by shared/irq_init.c */
+/* we can treat the AT91RM9200 AIC_SVR_BASE as */
+/* a vector table */
+#define VECTOR_TABLE AIC_SVR_BASE
+                                                                                           
+typedef unsigned char  rtems_irq_level;
+typedef unsigned char  rtems_irq_trigger;
+
+struct  __rtems_irq_connect_data__;     /* forward declaratiuon */
+
+typedef void (*rtems_irq_hdl)       (void);
+typedef void (*rtems_irq_enable)    (const struct __rtems_irq_connect_data__*);
+typedef void (*rtems_irq_disable)   (const struct __rtems_irq_connect_data__*);
+typedef int  (*rtems_irq_is_enabled)(const struct __rtems_irq_connect_data__*);
+
+typedef struct __rtems_irq_connect_data__ {
+    /* IRQ line */
+    rtems_irq_symbolic_name       name;
+
+    /* Handler */
+    rtems_irq_hdl                 hdl;
+
+    /* function for enabling interrupts at device level. */
+    rtems_irq_enable              on;
+
+    /* function for disabling interrupts at device level. */
+    rtems_irq_disable             off;
+
+    /* Function to test if interrupt is enabled */
+    rtems_irq_is_enabled        isOn;
+
+    /* priority level of interrupt */
+    rtems_irq_level               irqLevel;
+
+    /* Trigger method (rising/falling edge or high/low level) */
+    rtems_irq_trigger             irqTrigger;
+} rtems_irq_connect_data;
+
+/*
+ * function to initialize the interrupt for a specific BSP
+ */
+void BSP_rtems_irq_mngt_init();
+
+
+/*
+ * function to connect a particular irq handler.
+ */
+int BSP_install_rtems_irq_handler       (const rtems_irq_connect_data*);
+
+/*
+ * function to get the current RTEMS irq handler for ptr->name. 
+ */
+int BSP_get_current_rtems_irq_handler   (rtems_irq_connect_data* ptr);
+
+/*
+ * function to disconnect the RTEMS irq handler for ptr->name.
+ */
+int BSP_remove_rtems_irq_handler        (const rtems_irq_connect_data*);
+
+#endif /* __asm__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IRQ_H__ */
Index: c/src/lib/libcpu/arm/at91rm9200/pmc/pmc.c
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/pmc/pmc.c	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/pmc/pmc.c	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,99 @@
+/*
+ * Atmel AT91RM9200 PMC functions
+ *
+ * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
+ *	
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+#include <at91rm9200.h>
+#include <at91rm9200_pmc.h>
+
+int at91rm9200_get_mainclk(void)
+{
+    return BSP_MAIN_FREQ;
+}
+
+int at91rm9200_get_slck(void)
+{
+    return BSP_SLCK_FREQ;
+}
+
+int at91rm9200_get_mck(void)
+{
+    uint32_t mck_reg;
+    uint32_t mck_freq;
+    uint32_t pll_reg;
+    int prescaler;
+
+    mck_reg = PMC_REG(PMC_MCKR);
+
+    switch(mck_reg & PMC_MCKR_PRES_MASK) {
+    case PMC_MCKR_PRES_1:
+        prescaler = 1;
+        break;
+    case PMC_MCKR_PRES_2:
+        prescaler = 2;
+        break;
+    case PMC_MCKR_PRES_4:
+        prescaler = 4;
+        break;
+    case PMC_MCKR_PRES_8:
+        prescaler = 8;
+        break;
+    case PMC_MCKR_PRES_16:
+        prescaler = 16;
+        break;
+    case PMC_MCKR_PRES_32:
+        prescaler = 32;
+        break;
+    case PMC_MCKR_PRES_64:
+        prescaler = 64;
+        break;
+    }
+
+    /* Let's find out what MCK's source is */
+    switch (mck_reg & PMC_MCKR_CSS_MASK) {
+    case PMC_MCKR_CSS_SLOW:
+        /* I'm assuming the slow clock is 32.768 MHz */
+        mck_freq = at91rm9200_get_slck() / prescaler;
+        break;
+
+    case PMC_MCKR_CSS_MAIN:
+        mck_freq = at91rm9200_get_mainclk() / prescaler;
+        break;
+
+    case PMC_MCKR_CSS_PLLA:
+        pll_reg = PMC_REG(PMC_PLLAR);
+        mck_freq = at91rm9200_get_mainclk() / prescaler;
+        mck_freq = mck_freq / (pll_reg & PMC_PLLAR_DIV_MASK);
+        mck_freq = mck_freq * (((pll_reg & PMC_PLLAR_MUL_MASK) >> 16) + 1);
+        break;
+
+    case PMC_MCKR_CSS_PLLB:
+        pll_reg = PMC_REG(PMC_PLLBR);
+        mck_freq = at91rm9200_get_mainclk() / prescaler;
+        mck_freq = mck_freq / (pll_reg & PMC_PLLBR_DIV_MASK);
+        mck_freq = mck_freq * (((pll_reg & PMC_PLLBR_MUL_MASK) >> 16) + 1);
+        break;
+    }
+
+    if ((mck_reg & PMC_MCKR_MDIV_MASK) == PMC_MCKR_MDIV_2) {
+        mck_freq = mck_freq / 2;
+    } else if ((mck_reg & PMC_MCKR_MDIV_MASK) == PMC_MCKR_MDIV_3) {
+        mck_freq = mck_freq / 3;
+    } else if ((mck_reg & PMC_MCKR_MDIV_MASK) == PMC_MCKR_MDIV_4) {
+        mck_freq = mck_freq / 4;
+    }
+
+
+    return mck_freq;
+}
+
Index: c/src/lib/libcpu/arm/at91rm9200/timer/.cvsignore
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/timer/.cvsignore	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/timer/.cvsignore	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,14 @@
+Makefile
+Makefile.in
+aclocal.m4
+autom4te.cache
+config.cache
+config.guess
+config.log
+config.status
+config.sub
+configure
+depcomp
+install-sh
+missing
+mkinstalldirs
Index: c/src/lib/libcpu/arm/at91rm9200/timer/timer.c
===================================================================
--- c/src/lib/libcpu/arm/at91rm9200/timer/timer.c	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
+++ c/src/lib/libcpu/arm/at91rm9200/timer/timer.c	(revision af854856a832a3dad6e0b5d4ebe84ad64eab6987)
@@ -0,0 +1,111 @@
+/*
+ * Cogent CSB337 Timer driver
+ *
+ * This uses timer 0 for timing measurments.
+ *
+ * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
+ *	
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ * Notes:
+ *  This file manages the benchmark timer used by the RTEMS Timing Test
+ *  Suite.  Each measured time period is demarcated by calls to
+ *  Timer_initialize() and Read_timer().  Read_timer() usually returns
+ *  the number of microseconds since Timer_initialize() exitted.
+ *
+ *  It is important that the timer start/stop overhead be determined 
+ *  when porting or modifying this code.
+ *
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+#include <at91rm9200.h>
+#include <at91rm9200_pmc.h>
+
+rtems_unsigned16 tstart;
+rtems_boolean Timer_driver_Find_average_overhead;
+unsigned32 tick_time;
+/*
+ * Set up TC0 - 
+ *   timer_clock2 (MCK/8)
+ *   capture mode - this shouldn't matter
+ */
+void Timer_initialize( void )
+{
+    unsigned32 tmr_freq;
+
+    /* since we are using timer_clock2, divide mck by 8 */
+    tmr_freq = at91rm9200_get_mck() / 8;
+
+    TC_TC0_REG(TC_CMR) = TC_CMR_TCCLKS(1);   /* timer_clock2 */
+    TC_TC0_REG(TC_CCR) = (TC_CCR_CLKEN       /* enable the counter */
+                          | TC_CCR_SWTRG);   /* start it up */
+
+    /* tick time in nanoseconds */
+    tick_time = 1000000000/tmr_freq;
+
+}
+
+/*
+ *  The following controls the behavior of Read_timer().
+ *
+ *  AVG_OVEREHAD is the overhead for starting and stopping the timer.  It
+ *  is usually deducted from the number returned.
+ *
+ *  LEAST_VALID is the lowest number this routine should trust.  Numbers
+ *  below this are "noise" and zero is returned.
+ */
+
+#define AVG_OVERHEAD      0  /* It typically takes X.X microseconds */
+                             /* (Y countdowns) to start/stop the timer. */
+                             /* This value is in microseconds. */
+#define LEAST_VALID       1  /* Don't trust a clicks value lower than this */
+
+int Read_timer( void )
+{
+  rtems_unsigned16 t;
+  rtems_unsigned32 total;
+  t = TC_TC0_REG(TC_CV);
+
+  /*
+   *  Total is calculated by taking into account the number of timer overflow
+   *  interrupts since the timer was initialized and clicks since the last
+   *  interrupts.
+   */
+
+  total = t * tick_time;
+
+  if ( Timer_driver_Find_average_overhead == 1 )
+    return total;          /* in nanosecond units */
+  else {
+    if ( total < LEAST_VALID )
+      return 0;            /* below timer resolution */
+  /*
+   *  Somehow convert total into microseconds
+   */
+      return (total - AVG_OVERHEAD);
+    }
+}
+
+/*
+ *  Empty function call used in loops to measure basic cost of looping
+ *  in Timing Test Suite.
+ */
+
+rtems_status_code Empty_function( void )
+{
+  return RTEMS_SUCCESSFUL;
+}
+
+void Set_find_average_overhead(
+  rtems_boolean find_flag
+)
+{
+  Timer_driver_Find_average_overhead = find_flag;
+}
+
