Changeset af16a7d2 in rtems


Ignore:
Timestamp:
Jul 16, 2010, 8:45:02 AM (9 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
89b85e51
Parents:
9f9a82b
Message:

2010-07-16 Sebastian Huber <sebastian.huber@…>

  • rtems/new-exceptions/cpu.h: Removed file.
  • Makefile.am, preinstall.am: Reflect change above.
  • rtems/score/cpu.h: Include <rtems/score/types.h> first. Added contents of <rtems/new-exceptions/cpu.h>.
  • rtems/score/types.h: Use <rtems/score/basedefs.h> header file.
Location:
cpukit/score/cpu/powerpc
Files:
1 deleted
5 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/powerpc/ChangeLog

    r9f9a82b raf16a7d2  
     12010-07-16      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * rtems/new-exceptions/cpu.h: Removed file.
     4        * Makefile.am, preinstall.am: Reflect change above.
     5        * rtems/score/cpu.h: Include <rtems/score/types.h> first.  Added
     6        contents of <rtems/new-exceptions/cpu.h>.
     7        * rtems/score/types.h: Use <rtems/score/basedefs.h> header file.
     8
    192010-06-30      Peter Dufault <dufault@hda.com>
    210
  • cpukit/score/cpu/powerpc/Makefile.am

    r9f9a82b raf16a7d2  
    1212    rtems/score/types.h
    1313
    14 include_rtems_new_exceptionsdir = $(includedir)/rtems/new-exceptions
    15 include_rtems_new_exceptions_HEADERS = rtems/new-exceptions/cpu.h
    16 
    1714include_rtems_powerpcdir = $(includedir)/rtems/powerpc
    1815include_rtems_powerpc_HEADERS = rtems/powerpc/registers.h
  • cpukit/score/cpu/powerpc/preinstall.am

    r9f9a82b raf16a7d2  
    4040PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h
    4141
    42 $(PROJECT_INCLUDE)/rtems/new-exceptions/$(dirstamp):
    43         @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/new-exceptions
    44         @: > $(PROJECT_INCLUDE)/rtems/new-exceptions/$(dirstamp)
    45 PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/new-exceptions/$(dirstamp)
    46 
    47 $(PROJECT_INCLUDE)/rtems/new-exceptions/cpu.h: rtems/new-exceptions/cpu.h $(PROJECT_INCLUDE)/rtems/new-exceptions/$(dirstamp)
    48         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/new-exceptions/cpu.h
    49 PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/new-exceptions/cpu.h
    50 
    5142$(PROJECT_INCLUDE)/rtems/powerpc/$(dirstamp):
    5243        @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/powerpc
  • cpukit/score/cpu/powerpc/rtems/score/cpu.h

    r9f9a82b raf16a7d2  
    66 *  COPYRIGHT (c) 1989-2007.
    77 *  On-Line Applications Research Corporation (OAR).
     8 *
     9 *  COPYRIGHT (c) 1995 i-cubed ltd.
     10 *
     11 *  To anyone who acknowledges that this file is provided "AS IS"
     12 *  without any express or implied warranty:
     13 *      permission to use, copy, modify, and distribute this file
     14 *      for any purpose is hereby granted without fee, provided that
     15 *      the above copyright notice and this notice appears in all
     16 *      copies, and that the name of i-cubed limited not be used in
     17 *      advertising or publicity pertaining to distribution of the
     18 *      software without specific, written prior permission.
     19 *      i-cubed limited makes no representations about the suitability
     20 *      of this software for any purpose.
     21 *
     22 *  Copyright (c) 2001 Andy Dachs <a.dachs@sstl.co.uk>.
     23 *
     24 *  Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL).
     25 *
     26 *  Copyright (c) 2010 embedded brains GmbH.
    827 *
    928 *  The license and distribution terms for this file may be
     
    1736#define _RTEMS_SCORE_CPU_H
    1837
    19 #include <rtems/score/powerpc.h>              /* pick up machine definitions */
     38#include <rtems/score/types.h>
     39#include <rtems/score/powerpc.h>
     40#include <rtems/powerpc/registers.h>
    2041
    2142#ifndef ASM
    2243  #include <string.h> /* for memset() */
    23   #include <rtems/score/types.h>
     44#endif
     45
     46#ifdef __cplusplus
     47extern "C" {
    2448#endif
    2549
     
    320344#endif /* ASM */
    321345
    322 #include <rtems/new-exceptions/cpu.h>
     346/*
     347 *  Does RTEMS manage a dedicated interrupt stack in software?
     348 *
     349 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
     350 *  If FALSE, nothing is done.
     351 *
     352 *  If the CPU supports a dedicated interrupt stack in hardware,
     353 *  then it is generally the responsibility of the BSP to allocate it
     354 *  and set it up.
     355 *
     356 *  If the CPU does not support a dedicated interrupt stack, then
     357 *  the porter has two options: (1) execute interrupts on the
     358 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
     359 *  interrupt stack.
     360 *
     361 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
     362 *
     363 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
     364 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
     365 *  possible that both are FALSE for a particular CPU.  Although it
     366 *  is unclear what that would imply about the interrupt processing
     367 *  procedure on that CPU.
     368 */
     369
     370#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
     371
     372/*
     373 *  Does this CPU have hardware support for a dedicated interrupt stack?
     374 *
     375 *  If TRUE, then it must be installed during initialization.
     376 *  If FALSE, then no installation is performed.
     377 *
     378 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
     379 *
     380 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
     381 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
     382 *  possible that both are FALSE for a particular CPU.  Although it
     383 *  is unclear what that would imply about the interrupt processing
     384 *  procedure on that CPU.
     385 */
     386
     387#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
     388
     389/*
     390 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
     391 *
     392 *  If TRUE, then the memory is allocated during initialization.
     393 *  If FALSE, then the memory is allocated during initialization.
     394 *
     395 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
     396 */
     397
     398#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
     399
     400/*
     401 *  Does the RTEMS invoke the user's ISR with the vector number and
     402 *  a pointer to the saved interrupt frame (1) or just the vector
     403 *  number (0)?
     404 */
     405
     406#define CPU_ISR_PASSES_FRAME_POINTER 0
     407
     408/*
     409 *  Should the saving of the floating point registers be deferred
     410 *  until a context switch is made to another different floating point
     411 *  task?
     412 *
     413 *  If TRUE, then the floating point context will not be stored until
     414 *  necessary.  It will remain in the floating point registers and not
     415 *  disturned until another floating point task is switched to.
     416 *
     417 *  If FALSE, then the floating point context is saved when a floating
     418 *  point task is switched out and restored when the next floating point
     419 *  task is restored.  The state of the floating point registers between
     420 *  those two operations is not specified.
     421 *
     422 *  If the floating point context does NOT have to be saved as part of
     423 *  interrupt dispatching, then it should be safe to set this to TRUE.
     424 *
     425 *  Setting this flag to TRUE results in using a different algorithm
     426 *  for deciding when to save and restore the floating point context.
     427 *  The deferred FP switch algorithm minimizes the number of times
     428 *  the FP context is saved and restored.  The FP context is not saved
     429 *  until a context switch is made to another, different FP task.
     430 *  Thus in a system with only one FP task, the FP context will never
     431 *  be saved or restored.
     432 *
     433 *  Note, however that compilers may use floating point registers/
     434 *  instructions for optimization or they may save/restore FP registers
     435 *  on the stack. You must not use deferred switching in these cases
     436 *  and on the PowerPC attempting to do so will raise a "FP unavailable"
     437 *  exception.
     438 */
     439/*
     440 *  ACB Note:  This could make debugging tricky..
     441 */
     442
     443/* conservative setting (FALSE); probably doesn't affect performance too much */
     444#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
     445
     446/*
     447 *  Processor defined structures required for cpukit/score.
     448 */
     449
     450#ifndef ASM
     451
     452/*
     453 *  This variable is optional.  It is used on CPUs on which it is difficult
     454 *  to generate an "uninitialized" FP context.  It is filled in by
     455 *  _CPU_Initialize and copied into the task's FP context area during
     456 *  _CPU_Context_Initialize.
     457 */
     458
     459/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
     460
     461#endif /* ndef ASM */
     462
     463/*
     464 *  This defines the number of levels and the mask used to pick those
     465 *  bits out of a thread mode.
     466 */
     467
     468#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
     469#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
     470
     471/*
     472 *  Nothing prevents the porter from declaring more CPU specific variables.
     473 */
     474
     475#ifndef ASM
     476
     477SCORE_EXTERN struct {
     478  uint32_t      *Disable_level;
     479  void          *Stack;
     480  volatile bool *Switch_necessary;
     481  bool          *Signal;
     482
     483} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
     484
     485#endif /* ndef ASM */
     486
     487/*
     488 *  The size of the floating point context area.  On some CPUs this
     489 *  will not be a "sizeof" because the format of the floating point
     490 *  area is not defined -- only the size is.  This is usually on
     491 *  CPUs with a "floating point save context" instruction.
     492 */
     493
     494#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
     495
     496/*
     497 * (Optional) # of bytes for libmisc/stackchk to check
     498 * If not specifed, then it defaults to something reasonable
     499 * for most architectures.
     500 */
     501
     502#define CPU_STACK_CHECK_SIZE    (128)
     503
     504/*
     505 *  Amount of extra stack (above minimum stack size) required by
     506 *  MPCI receive server thread.  Remember that in a multiprocessor
     507 *  system this thread must exist and be able to process all directives.
     508 */
     509
     510#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
     511
     512/*
     513 *  This defines the number of entries in the ISR_Vector_table managed
     514 *  by RTEMS.
     515 */
     516
     517#define CPU_INTERRUPT_NUMBER_OF_VECTORS     (0)
     518#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (UINT32_MAX)
     519
     520/*
     521 *  This is defined if the port has a special way to report the ISR nesting
     522 *  level.  Most ports maintain the variable _ISR_Nest_level. Note that
     523 *  this is not an option - RTEMS/score _relies_ on _ISR_Nest_level
     524 *  being maintained (e.g. watchdog queues).
     525 */
     526
     527#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
     528
     529/*
     530 *  ISR handler macros
     531 */
     532
     533#define _CPU_Initialize_vectors()
     534
     535/*
     536 *  Disable all interrupts for an RTEMS critical section.  The previous
     537 *  level is returned in _isr_cookie.
     538 */
     539
     540#ifndef ASM
     541
     542static inline uint32_t   _CPU_ISR_Get_level( void )
     543{
     544  register unsigned int msr;
     545  _CPU_MSR_GET(msr);
     546  if (msr & MSR_EE) return 0;
     547  else  return 1;
     548}
     549
     550static inline void _CPU_ISR_Set_level( uint32_t   level )
     551{
     552  register unsigned int msr;
     553  _CPU_MSR_GET(msr);
     554  if (!(level & CPU_MODES_INTERRUPT_MASK)) {
     555    msr |= ppc_interrupt_get_disable_mask();
     556  }
     557  else {
     558    msr &= ~ppc_interrupt_get_disable_mask();
     559  }
     560  _CPU_MSR_SET(msr);
     561}
     562
     563void BSP_panic(char *);
     564
     565/* Fatal Error manager macros */
     566
     567/*
     568 *  This routine copies _error into a known place -- typically a stack
     569 *  location or a register, optionally disables interrupts, and
     570 *  halts/stops the CPU.
     571 */
     572
     573void _BSP_Fatal_error(unsigned int);
     574
     575#endif /* ASM */
     576
     577#define _CPU_Fatal_halt( _error ) \
     578  _BSP_Fatal_error(_error)
     579
     580/* end of Fatal Error manager macros */
     581
     582/*
     583 * SPRG0 was previously used to make sure that the BSP fixed the PR288 bug.
     584 * Now SPRG0 is devoted to the interrupt disable mask.
     585 */
     586
     587#define PPC_BSP_HAS_FIXED_PR288 ppc_this_is_now_the_interrupt_disable_mask
    323588
    324589/*
     
    708973#endif /* ASM */
    709974
     975#ifdef __cplusplus
     976}
     977#endif
     978
    710979#endif /* _RTEMS_SCORE_CPU_H */
  • cpukit/score/cpu/powerpc/rtems/score/types.h

    r9f9a82b raf16a7d2  
    3737#define _RTEMS_SCORE_TYPES_H
    3838
     39#include <rtems/score/basedefs.h>
     40
    3941#ifndef ASM
    40 
    41 #include <stdbool.h>
    42 #include <stdint.h>
    4342
    4443#ifdef __cplusplus
     
    5251typedef void ppc_isr;
    5352
    54 #ifdef RTEMS_DEPRECATED_TYPES
    55 typedef bool    boolean;                /* Boolean value   */
    56 typedef float   single_precision;       /* single precision float */
    57 typedef double  double_precision;       /* double precision float */
    58 #endif
    59 
    6053#ifdef __cplusplus
    6154}
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