Changeset aecfa2b in rtems


Ignore:
Timestamp:
Sep 30, 1998, 9:55:53 PM (21 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
02c14a0
Parents:
be4284d0
Message:

BSP submitted by Thomas Doerfler <td@…>:

Finally I am through: I have found the last bugs that made RTEMS-
4.0-beta3 start on my ppc403 board from ROM. So now the '403
support is up to date again.

Roughly I have added the following features:

  • support for the on-chip interrupt controller (in a separate module)
  • interrupt support for the console device
  • termios support for the console device

==============================================
Since the BSP behaivour changed in some details (console no
longer is polling, other memory layout etc) I have created a new
BSP "helas403" rather than changing the "papyrus" BSP. The old
"polled" console driver still sticks around in "console.c.polled"

To get the BSP up and running, I had to create the new BSP files
(derived from papyrus). Besides that, the following source areas
have been changed:

  • c/src/lib/libcpu/powerpc/ppc403: changes to console driver, small changes to clock driver, new "ictrl" interrupt controller driver
  • c/src/exec/score/cpu/powerpc/ppc.h: some small changes (added ppc403 characteristics like a exception vector prefix register, some special register definitions). I am quite sure, they are compatible with the existing sources, although I did not check
  • c/src/exec/score/cpu/powerpc/cpu.c: There is one severe limitation in the exception entries: Due to the current code arrangement, the "branch absolute" to the ISR handler may only jump to the first 128MByte or the last 128MByte of the 4GByte address range. When the ppc403 is running out of ROM, the ROM functions are located in the last 128MByte (0xFFF00000 and up). These addresses were not handled correctly (sign reduced) in "install_raw_handler". The change I added should work on existing ppc BSPs aswell...
  • c/src/lib/libc/termios.c: During my tests, I added one change you sent me, so this patch will already be incorporated in the current source tree.

There are some smaller changes, see the attached diff file.

=========================================
Concerning the GNU toolchain:

I tried several tool chains. Finally I almost succeeded with

egcs-1.0.3a with patch egcs-1.0.3-rtems-diff-19980527

I had to add the following lines to the egcs files. Without them
configure complaint that the cross compiler could not generate
executable output.

  • additional lines needed in egcs distribution in file gcc/config/rs6000/rtems.h:

+++ lines start
#undef STARTFILE_DEFAULT_SPEC
#define STARTFILE_DEFAULT_SPEC "ecrti.o%s"

#undef ENDFILE_DEFAULT_SPEC
#define ENDFILE_DEFAULT_SPEC "ecrtn.o%s"
++++ lines end

As far as I have seen in the Changelog of egcs, you have recently
sent two patches affecting the powerpc support, but they were
added in the wrong order.... :-(

egcs-19980628 with patch egcs-19980628-rtems-diff-19980707 does
not work!

I used binutils 2.9.1 with patch binutils-2.9.1-rtems-diff-19980515

(binutils 2.8.1 does not work, internal error in gas)

and newlib-1.8.0 with patch newlib-1.8.0-rtems-diff-19980707

Finally I had to poke a line in the "bit" script, since, on my LINUX
machine, the GNU make is only available as "make", not as
"gmake"...

For all the tools and newlib I selected configuration "powerpc-
rtems".

IMD Ingenieurbuero fuer Microcomputertechnik
Thomas Doerfler Herbststrasse 8
D-82178 Puchheim Germany
email: td@…

Location:
c/src/lib/libcpu/powerpc/ppc403
Files:
4 added
3 edited

Legend:

Unmodified
Added
Removed

  • c/src/lib/libcpu/powerpc/ppc403/Makefile.in

    rbe4284d0 raecfa2b  
    1212include $(RTEMS_ROOT)/make/directory.cfg
    1313
    14 SUB_DIRS=include console clock timer vectors
     14SUB_DIRS=include console clock timer vectors ictrl

  • c/src/lib/libcpu/powerpc/ppc403/clock/clock.c

    rbe4284d0 raecfa2b  
    2121 *  Derived from c/src/lib/libcpu/hppa1.1/clock/clock.c:
    2222 *
     23 *  Modifications for deriving timer clock from cpu system clock by
     24 *              Thomas Doerfler <td@imd.m.isar.de>
     25 *  for these modifications:
     26 *  COPYRIGHT (c) 1997 by IMD, Puchheim, Germany.
     27 *
     28 *
    2329 *  COPYRIGHT (c) 1989-1998.
    2430 *  On-Line Applications Research Corporation (OAR).
    … …  
    134140 
    135141    asm volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */
    136     iocr &= ~4;
    137     iocr |= 4;  /* Select external timer clock */
     142
     143    if (Cpu_table.timer_internal_clock) {
     144        iocr &= ~4; /* timer clocked from system clock */
     145    }
     146    else {
     147        iocr |= 4; /* select external timer clock */
     148    }
     149
    138150    asm volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */
    139151 
    … …  
    144156 
    145157    if ((pvr & 0xff00) == 0x0000) /* 403GA */
     158#if 0 /* FIXME: in which processor versions will "autoload" work properly? */
    146159      auto_restart = (pvr & 0x00f0) > 0x0000 ? 1 : 0;
     160#else
     161    /* no known chip version supports auto restart of timer... */
     162    auto_restart = 0;
     163#endif
    147164    else if ((pvr & 0xff00) == 0x0100) /* 403GB */
    148165      auto_restart = 1;

  • c/src/lib/libcpu/powerpc/ppc403/console/console.c

    rbe4284d0 raecfa2b  
    11/*
    22 *  This file contains the PowerPC 403GA console IO package.
     3 *
     4 *  Author:     Thomas Doerfler <td@imd.m.isar.de>
     5 *              IMD Ingenieurbuero fuer Microcomputertechnik
     6 *
     7 *  COPYRIGHT (c) 1998 by IMD
     8 *
     9 *  Changes from IMD are covered by the original distributions terms.
     10 *  changes include interrupt support and termios support
     11 *  for backward compatibility, the original polled driver has been
     12 *  renamed to console.c.polled
     13 *
     14 *  This file has been initially created (polled version) by
    315 *
    416 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
    … …  
    1729 *      of this software for any purpose.
    1830 *
     31 *  Modifications for spooling (interrupt driven) console driver
     32 *            by Thomas Doerfler <td@imd.m.isar.de>
     33 *  for these modifications:
     34 *  COPYRIGHT (c) 1997 by IMD, Puchheim, Germany.
     35 *
     36 *  To anyone who acknowledges that this file is provided "AS IS"
     37 *  without any express or implied warranty:
     38 *      permission to use, copy, modify, and distribute this file
     39 *      for any purpose is hereby granted without fee, provided that
     40 *      the above copyright notice and this notice appears in all
     41 *      copies. IMD makes no representations about the suitability
     42 *      of this software for any purpose.
     43 *
    1944 *  Derived from c/src/lib/libbsp/no_cpu/no_bsp/console/console.c:
    2045 *
    21  *  COPYRIGHT (c) 1989-1998.
     46 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
    2247 *  On-Line Applications Research Corporation (OAR).
    23  *  Copyright assigned to U.S. Government, 1994.
    24  *
    25  *  The license and distribution terms for this file may be
    26  *  found in the file LICENSE in this distribution or at
    27  *  http://www.OARcorp.com/rtems/license.html.
    28  *
    29  *  $Id$
     48 *  All rights assigned to U.S. Government, 1994.
     49 *
     50 *  This material may be reproduced by or for the U.S. Government pursuant
     51 *  to the copyright license under the clause at DFARS 252.227-7013.  This
     52 *  notice must appear in all copies of this file and its derivatives.
     53 *
     54 *  console.c,v 1.4 1995/12/05 19:23:02 joel Exp
    3055 */
    3156
    … …  
    3459#include <bsp.h>
    3560#include <rtems/libio.h>
    36 
     61#include "../ictrl/ictrl.h"
     62#include <stdlib.h>                                     /* for atexit() */
    3763extern rtems_cpu_table           Cpu_table;             /* owned by BSP */
    3864
    3965struct async {
    40 /*-----------------------------------------------------------------------------+
     66/*---------------------------------------------------------------------------+
    4167| Line Status Register.
    42 +-----------------------------------------------------------------------------*/
    43     unsigned char SPLS;
    44     unsigned char SPLSset;
     68+---------------------------------------------------------------------------*/
     69  unsigned char SPLS;
     70  unsigned char SPLSset;
    4571#define LSRDataReady             0x80
    4672#define LSRFramingError          0x40
    … …  
    5177#define LSRTxShiftEmpty          0x02
    5278
    53 /*-----------------------------------------------------------------------------+
     79/*---------------------------------------------------------------------------+
    5480| Handshake Status Register.
    55 +-----------------------------------------------------------------------------*/
    56     unsigned char SPHS;
    57     unsigned char SPHSset;
     81+---------------------------------------------------------------------------*/
     82  unsigned char SPHS;
     83  unsigned char SPHSset;
    5884#define HSRDsr                   0x80
    5985#define HSRCts                   0x40
    6086
    61 /*-----------------------------------------------------------------------------+
     87/*---------------------------------------------------------------------------+
    6288| Baud rate divisor registers
    63 +-----------------------------------------------------------------------------*/
    64     unsigned char BRDH;
    65     unsigned char BRDL;
    66 
    67 /*-----------------------------------------------------------------------------+
     89+---------------------------------------------------------------------------*/
     90  unsigned char BRDH;
     91  unsigned char BRDL;
     92
     93/*---------------------------------------------------------------------------+
    6894| Control Register.
    69 +-----------------------------------------------------------------------------*/
    70     unsigned char SPCTL;
    71 #define CRNormal                      0x00
    72 #define CRLoopback                    0x40
    73 #define CRAutoEcho                    0x80
     95+---------------------------------------------------------------------------*/
     96  unsigned char SPCTL;
     97#define CRNormal                 0x00
     98#define CRLoopback               0x40
     99#define CRAutoEcho               0x80
    74100#define CRDtr                    0x20
    75101#define CRRts                    0x10
    … …  
    79105#define CRParityEnable           0x04
    80106#define CREvenParity             0x00
    81 #define CROddParity           0x02
     107#define CROddParity              0x02
    82108#define CRStopBitsOne            0x00
    83109#define CRStopBitsTwo            0x01
    84 #define CRDisableDtrRts       0x00
    85 
    86 /*-----------------------------------------------------------------------------+
     110#define CRDisableDtrRts          0x00
     111
     112/*--------------------------------------------------------------------------+
    87113| Receiver Command Register.
    88 +-----------------------------------------------------------------------------*/
    89     unsigned char SPRC;
    90 #define RCRDisable                    0x00
    91 #define RCREnable                     0x80
    92 #define RCRIntDisable         0x00
    93 #define RCRIntEnabled         0x20
    94 #define RCRDMACh2                     0x40
    95 #define RCRDMACh3                     0x60
    96 #define RCRErrorInt           0x10
    97 #define RCRPauseEnable        0x08
    98 
    99 /*-----------------------------------------------------------------------------+
     114+--------------------------------------------------------------------------*/
     115  unsigned char SPRC;
     116#define RCRDisable               0x00
     117#define RCREnable                0x80
     118#define RCRIntDisable            0x00
     119#define RCRIntEnabled            0x20
     120#define RCRDMACh2                0x40
     121#define RCRDMACh3                0x60
     122#define RCRErrorInt              0x10
     123#define RCRPauseEnable           0x08
     124
     125/*--------------------------------------------------------------------------+
    100126| Transmitter Command Register.
    101 +-----------------------------------------------------------------------------*/
     127+--------------------------------------------------------------------------*/
    102128    unsigned char SPTC;
    103 #define TCRDisable                    0x00
    104 #define TCREnable                     0x80
    105 #define TCRIntDisable         0x00
    106 #define TCRIntEnabled         0x20
    107 #define TCRDMACh2                     0x40
    108 #define TCRDMACh3                     0x60
    109 #define TCRTxEmpty                    0x10
    110 #define TCRErrorInt           0x08
    111 #define TCRStopPause          0x04
    112 #define TCRBreakGen           0x02
    113 
    114 /*-----------------------------------------------------------------------------+
     129#define TCRDisable               0x00
     130#define TCREnable                0x80
     131#define TCRIntDisable            0x00
     132#define TCRIntEnabled            0x20
     133#define TCRDMACh2                0x40
     134#define TCRDMACh3                0x60
     135#define TCRTxEmpty               0x10
     136#define TCRErrorInt              0x08
     137#define TCRStopPause             0x04
     138#define TCRBreakGen              0x02
     139
     140/*--------------------------------------------------------------------------+
    115141| Miscellanies defines.
    116 +-----------------------------------------------------------------------------*/
    117     unsigned char SPTB;
     142+--------------------------------------------------------------------------*/
     143  unsigned char SPTB;
    118144#define SPRB    SPTB
    119145};
    120146
    121 #define XOFFchar                      0x13
    122 #define XONchar                       0x11
    123 
    124147typedef volatile struct async *pasync;
    125148static const pasync port = (pasync)0x40000000;
     149
     150static void *spittyp;         /* handle for termios */
     151int ppc403_spi_interrupt = 1; /* do not use interrupts... */
     152
     153/*
     154 * Rx Interrupt handler
     155 */
     156static rtems_isr
     157spiRxInterruptHandler (rtems_vector_number v)
     158{
     159  char ch;
     160
     161  /* clear any receive errors (errors are ignored now) */
     162  port->SPLS = (LSRFramingError | LSROverrunError |
     163                LSRParityError  | LSRBreakInterrupt);
     164  /*
     165   * Buffer received?
     166   */
     167  if (port->SPLS & LSRDataReady) {
     168    ch = port->SPRB; /* read receive buffer */
     169    rtems_termios_enqueue_raw_characters (spittyp,&ch,1);
     170  }
     171}
     172
     173/*
     174 * Tx Interrupt handler
     175 */
     176static rtems_isr
     177spiTxInterruptHandler (rtems_vector_number v)
     178{
     179  /*
     180   * char transmitted?
     181   */
     182  if (0 != (port->SPLS & LSRTxHoldEmpty)) { /* must always be true!! */
     183    port->SPTC &= ~TCRIntEnabled;           /* stop irqs for now...  */
     184                                            /* and call termios...   */
     185    rtems_termios_dequeue_characters (spittyp,1);
     186  }
     187}
     188
     189/*
     190 * enable/disable RTS line to start/stop remote transmitter
     191 */
     192static int
     193spiStartRemoteTx (int minor)
     194{
     195  rtems_interrupt_level level;
     196
     197  rtems_interrupt_disable (level);
     198  port->SPCTL |= CRRts;           /* activate RTS  */
     199  rtems_interrupt_enable (level);
     200  return 0;
     201}
     202
     203static int
     204spiStopRemoteTx (int minor)
     205{
     206  rtems_interrupt_level level;
     207
     208  rtems_interrupt_disable (level);
     209  port->SPCTL &= ~CRRts;           /* deactivate RTS  */
     210  rtems_interrupt_enable (level);
     211  return 0;
     212}
     213
     214void
     215spiBaudSet(unsigned32 baudrate)
     216{
     217  unsigned32 tmp;
     218  tmp = Cpu_table.serial_per_sec / Cpu_table.serial_rate;
     219  tmp = ((tmp) >> 4) - 1;
     220  port->BRDL = tmp & 0xff;
     221  port->BRDH = tmp >> 8;
     222
     223}
     224/*
     225 * Hardware-dependent portion of tcsetattr().
     226 */
     227static int
     228spiSetAttributes (int minor, const struct termios *t)
     229{
     230  int baud;
     231
     232  /* FIXME: check c_cflag & CRTSCTS for hardware flowcontrol */
     233  /* FIXME: check and IMPLEMENT XON/XOFF                     */
     234  switch (t->c_cflag & CBAUD) {
     235  default:      baud = -1;      break;
     236  case B50:     baud = 50;      break;
     237  case B75:     baud = 75;      break;
     238  case B110:    baud = 110;     break;
     239  case B134:    baud = 134;     break;
     240  case B150:    baud = 150;     break;
     241  case B200:    baud = 200;     break;
     242  case B300:    baud = 300;     break;
     243  case B600:    baud = 600;     break;
     244  case B1200:   baud = 1200;    break;
     245  case B1800:   baud = 1800;    break;
     246  case B2400:   baud = 2400;    break;
     247  case B4800:   baud = 4800;    break;
     248  case B9600:   baud = 9600;    break;
     249  case B19200:  baud = 19200;   break;
     250  case B38400:  baud = 38400;   break;
     251  case B57600:  baud = 57600;   break;
     252  case B115200: baud = 115200;  break;
     253  case B230400: baud = 230400;  break;
     254  case B460800: baud = 460800;  break;
     255  }
     256  if (baud > 0) {
     257    spiBaudSet(baud);
     258  }
     259  return 0;
     260}
     261
     262static int
     263spiPollRead (int minor)
     264{
     265  unsigned char status;
     266
     267  while (0 == ((status = port->SPLS) & LSRDataReady)) {
     268    /* Clean any dodgy status */
     269    if ((status & (LSRFramingError | LSROverrunError | LSRParityError |
     270                   LSRBreakInterrupt)) != 0) {
     271      port->SPLS = (LSRFramingError | LSROverrunError | LSRParityError |
     272                    LSRBreakInterrupt);
     273    }
     274  }
     275  return port->SPRB; 
     276}
     277
     278static int
     279spiInterruptWrite (int minor, const char *buf, int len)
     280{
     281  port->SPTB = *buf;           /* write char to send         */
     282  port->SPTC |= TCRIntEnabled; /* always enable tx interrupt */
     283  return 0;
     284}
     285
     286static int
     287spiPollWrite(int minor,const char *buf,int len)
     288{ 
     289  unsigned char status;
     290
     291  while (len-- > 0) {
     292    do {
     293      if (port->SPHS) {
     294        port->SPHS = (HSRDsr | HSRCts);
     295      }
     296      status = port->SPLS;
     297    } while (0 == (status & LSRTxHoldEmpty));
     298    port->SPTB = *buf++;
     299  }
     300  return 0;
     301}
     302
     303/*
     304 *
     305 * deinit SPI
     306 *
     307 */
     308void
     309spiDeInit(void)
     310{
     311  /*
     312   * disable interrupts for serial port
     313   * set it to state to work with polling boot monitor, if any...
     314   */
     315
     316  /* set up baud rate to original state */
     317  spiBaudSet(Cpu_table.serial_rate);
     318
     319  /* clear any receive (error) status */
     320  port->SPLS = (LSRDataReady   | LSRFramingError | LSROverrunError |
     321                LSRParityError | LSRBreakInterrupt);
     322
     323  /* set up port control: DTR/RTS active,8 bit,1 stop,no parity */
     324  port->SPCTL = (CRNormal |
     325                 CRDtr | CRRts |
     326                 CRWordLength8 | CRParityDisable | CRStopBitsOne);
     327
     328  /* clear handshake status bits */
     329  port->SPHS = (HSRDsr | HSRCts);
     330
     331  /* enable receiver/transmitter, no interrupts */
     332  port->SPRC = (RCREnable | RCRIntDisable);
     333  port->SPTC = (TCREnable | TCRIntDisable);
     334
     335}
     336
     337/*
     338 *
     339 * init SPI
     340 *
     341 */
     342rtems_status_code
     343spiInitialize(void)
     344{
     345  register unsigned tmp;
     346  rtems_isr_entry previous_isr; /* this is a dummy */
     347
     348  /*
     349   * Initialise the serial port
     350   */
     351
     352  /*
     353   * select RTS/CTS hardware handshake lines,
     354   * select clock source
     355   */
     356  asm volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */
     357
     358  tmp &= ~3;
     359  tmp |= (Cpu_table.serial_external_clock ? 2 : 0) | 1;
     360
     361  asm volatile ("mtdcr 0xa0, %0" : "=r" (tmp) : "0" (tmp)); /* IOCR */
     362
     363  /* clear any receive (error) status */
     364  port->SPLS = (LSRDataReady   | LSRFramingError | LSROverrunError |
     365                LSRParityError | LSRBreakInterrupt);
     366
     367  /* set up baud rate */
     368  spiBaudSet(Cpu_table.serial_rate);
     369
     370  /* set up port control: DTR/RTS active,8 bit,1 stop,no parity */
     371  port->SPCTL = (CRNormal |
     372                 CRDtr | CRRts |
     373                 CRWordLength8 | CRParityDisable | CRStopBitsOne);
     374
     375  /* clear handshake status bits */
     376  port->SPHS = (HSRDsr | HSRCts);
     377
     378  if (ppc403_spi_interrupt) {
     379    /* add rx/tx isr to vector table */
     380    ictrl_set_vector(spiRxInterruptHandler,
     381                     PPC_IRQ_EXT_SPIR,
     382                     &previous_isr);
     383
     384    ictrl_set_vector(spiTxInterruptHandler,
     385                     PPC_IRQ_EXT_SPIT,
     386                     &previous_isr);
     387
     388    port->SPRC = (RCREnable | RCRIntEnabled | RCRErrorInt);
     389    port->SPTC = (TCREnable | TCRIntDisable); /* don't enable TxInt yet */
     390  }
     391  else {
     392    /* enable receiver/transmitter, no interrupts */
     393    port->SPRC = (RCREnable | RCRIntDisable);
     394    port->SPTC = (TCREnable | TCRIntDisable);
     395  }
     396
     397  atexit(spiDeInit);
     398
     399  return RTEMS_SUCCESSFUL;
     400}
     401
     402/*
     403 ***************
     404 * BOILERPLATE *
     405 ***************
     406 */
     407
     408/*
     409 * Reserve resources consumed by this driver
     410 */
     411void console_reserve_resources(
     412  rtems_configuration_table *configuration
     413)
     414{
     415        rtems_termios_reserve_resources (configuration, 1);
     416}
    126417
    127418/*  console_initialize
    … …  
    143434{
    144435  rtems_status_code status;
    145   register unsigned tmp;
    146 
    147   /* Initialise the serial port */
    148   asm volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */
    149   tmp &= ~3;
    150   tmp |= (Cpu_table.serial_external_clock ? 2 : 0) |
    151       (Cpu_table.serial_cts_rts ? 1 : 0);
    152   asm volatile ("mtdcr 0xa0, %0" : "=r" (tmp) : "0" (tmp)); /* IOCR */
    153   port->SPLS = (LSRDataReady | LSRFramingError | LSROverrunError |
    154          LSRParityError | LSRBreakInterrupt);
    155   tmp = Cpu_table.serial_per_sec / Cpu_table.serial_rate;
    156   tmp = ((tmp + 8) >> 4) - 1;
    157   port->BRDL = tmp & 0x255;
    158   port->BRDH = tmp >> 8;
    159   port->SPCTL = (CRNormal | CRDtr | CRRts | CRWordLength8 | CRParityDisable |
    160      CRStopBitsOne);
    161   port->SPRC = (RCREnable | RCRIntDisable | RCRPauseEnable);
    162   port->SPTC = (TCREnable | TCRIntDisable);
    163   port->SPHS = (HSRDsr | HSRCts);
    164 
    165   status = rtems_io_register_name(
    166     "/dev/console",
    167     major,
    168     (rtems_device_minor_number) 0
    169   );
    170  
     436
     437  /*
     438   * Set up TERMIOS
     439   */
     440  rtems_termios_initialize ();
     441
     442  /*
     443   * Do device-specific initialization
     444   */
     445  spiInitialize ();
     446
     447  /*
     448   * Register the device
     449   */
     450  status = rtems_io_register_name ("/dev/console", major, 0);
    171451  if (status != RTEMS_SUCCESSFUL)
    172     rtems_fatal_error_occurred(status);
    173  
     452    rtems_fatal_error_occurred (status);
    174453  return RTEMS_SUCCESSFUL;
    175454}
    176455
    177 
    178 /*  is_character_ready
    179  *
    180  *  This routine returns TRUE if a character is available.
    181  *
    182  *  Input parameters: NONE
    183  *
    184  *  Output parameters:  NONE
    185  *
    186  *  Return values:
    187  */
    188 
    189 rtems_boolean is_character_ready(
    190   char *ch
    191 )
    192 {
    193   unsigned char status;
    194 
    195   if ((status = port->SPLS) & LSRDataReady)
    196     {
    197       *ch = port->SPRB; 
    198       return(TRUE);
    199     }
    200 
    201   /* Clean any dodgy status */
    202   if ((status & (LSRFramingError | LSROverrunError | LSRParityError |
    203                  LSRBreakInterrupt)) != 0)
    204     {
    205       port->SPLS = (LSRFramingError | LSROverrunError | LSRParityError |
    206                  LSRBreakInterrupt);
    207     }
    208 
    209   return FALSE;
    210 }
    211 
    212 /*  inbyte
    213  *
    214  *  This routine reads a character from the SOURCE.
    215  *
    216  *  Input parameters: NONE
    217  *
    218  *  Output parameters:  NONE
    219  *
    220  *  Return values:
    221  *    character read from SOURCE
    222  */
    223 
    224 char inbyte( void )
    225 {
    226   unsigned char status;
    227 
    228   while (1)
    229     {
    230       if ((status = port->SPLS) & LSRDataReady)
    231               break;
    232 
    233       /* Clean any dodgy status */
    234       if ((status & (LSRFramingError | LSROverrunError | LSRParityError |
    235                      LSRBreakInterrupt)) != 0)
    236             {
    237               port->SPLS = (LSRFramingError | LSROverrunError | LSRParityError |
    238                             LSRBreakInterrupt);
    239             }
    240     }
    241 
    242   return port->SPRB; 
    243 }
    244 
    245 /*  outbyte
    246  *
    247  *  This routine transmits a character out the SOURCE.  It may support
    248  *  XON/XOFF flow control.
    249  *
    250  *  Input parameters:
    251  *    ch  - character to be transmitted
    252  *
    253  *  Output parameters:  NONE
    254  */
    255 
    256 void outbyte(
    257   char ch
    258 )
    259 {
    260   unsigned char status;
    261 
    262   while (port->SPHS)
    263     port->SPHS = (HSRDsr | HSRCts);
    264 
    265   while (1)
    266     {
    267       status = port->SPLS;
    268 
    269       if (port->SPHS)
    270         port->SPHS = (HSRDsr | HSRCts);
    271       else if (status & LSRTxHoldEmpty)
    272               break;
    273     }
    274 
    275   if (Cpu_table.serial_xon_xoff)
    276     while (is_character_ready(&status))
    277     {
    278             if (status == XOFFchar)
    279               do {
    280                 while (!is_character_ready(&status));
    281               } while (status != XONchar);
    282     }
    283 
    284   port->SPTB = ch;
    285 }
    286456
    287457/*
    … …  
    295465)
    296466{
    297   return RTEMS_SUCCESSFUL;
     467  rtems_status_code sc;
     468  static const rtems_termios_callbacks intrCallbacks = {
     469    NULL,               /* firstOpen */
     470    NULL,               /* lastClose */
     471    NULL,               /* pollRead */
     472    spiInterruptWrite,  /* write */
     473    spiSetAttributes,   /* setAttributes */
     474    spiStopRemoteTx,    /* stopRemoteTx */
     475    spiStartRemoteTx,   /* startRemoteTx */
     476    1                   /* outputUsesInterrupts */
     477  };
     478
     479  static const rtems_termios_callbacks pollCallbacks = {
     480    NULL,               /* firstOpen */
     481    NULL,               /* lastClose */
     482    spiPollRead,        /* pollRead */
     483    spiPollWrite,       /* write */
     484    spiSetAttributes,   /* setAttributes */
     485    spiStopRemoteTx,    /* stopRemoteTx */
     486    spiStartRemoteTx,   /* startRemoteTx */
     487    0                   /* outputUsesInterrupts */
     488  };
     489
     490  if (ppc403_spi_interrupt) {
     491    rtems_libio_open_close_args_t *args = arg;
     492   
     493    sc = rtems_termios_open (major, minor, arg, &intrCallbacks);
     494    spittyp = args->iop->data1;
     495  }
     496  else {
     497    sc = rtems_termios_open (major, minor, arg, &pollCallbacks);
     498  }
     499  return sc;
    298500}
    299501 
    … …  
    308510)
    309511{
    310   return RTEMS_SUCCESSFUL;
     512  return rtems_termios_close (arg);
    311513}
    312514 
    … …  
    321523)
    322524{
    323   rtems_libio_rw_args_t *rw_args;
    324   char *buffer;
    325   int maximum;
    326   int count = 0;
    327  
    328   rw_args = (rtems_libio_rw_args_t *) arg;
    329  
    330   buffer = rw_args->buffer;
    331   maximum = rw_args->count;
    332  
    333   for (count = 0; count < maximum; count++) {
    334     buffer[ count ] = inbyte();
    335     if (buffer[ count ] == '\n' || buffer[ count ] == '\r') {
    336       buffer[ count++ ]  = '\n';
    337       buffer[ count ]  = 0;
    338       break;
    339     }
    340   }
    341  
    342   rw_args->bytes_moved = count;
    343   return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED;
     525  return rtems_termios_read (arg);
    344526}
    345527 
    … …  
    354536)
    355537{
    356   int count;
    357   int maximum;
    358   rtems_libio_rw_args_t *rw_args;
    359   char *buffer;
    360  
    361   rw_args = (rtems_libio_rw_args_t *) arg;
    362  
    363   buffer = rw_args->buffer;
    364   maximum = rw_args->count;
    365  
    366   for (count = 0; count < maximum; count++) {
    367     if ( buffer[ count ] == '\n') {
    368       outbyte('\r');
    369     }
    370     outbyte( buffer[ count ] );
    371   }
    372   return maximum;
     538  return rtems_termios_write (arg);
    373539}
    374540 
    … …  
    383549)
    384550{
    385   return RTEMS_SUCCESSFUL;
    386 }
    387 
     551  return rtems_termios_ioctl (arg);
     552}
     553
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