Ignore:
Timestamp:
Oct 27, 1999, 5:25:53 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
2bdc1e98
Parents:
2ea8df3
Message:

rxgen960 now compiles -- may not link.

Location:
c/src/lib/libbsp/i960/rxgen960/include
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/i960/rxgen960/include/bsp.h

    r2ea8df3 rae7325bd  
    9191 */
    9292
    93 static inline PRCB *get_prcb( void )
     93static inline i960_PRCB *get_prcb( void )
    9494{
    95   register PRCB *_prcb = 0;
     95  register i960_PRCB *_prcb = 0;
    9696
    9797  asm volatile( "calls 5; \
     
    119119extern rtems_configuration_table BSP_Configuration;
    120120
    121 BSP_EXTERN PRCB          *Prcb;
    122 BSP_EXTERN CNTL_TBL      *Ctl_tbl;
    123 
    124 /*
    125 #if defined(i960ca)
    126 BSP_EXTERN i960ca_control_table *Ctl_tbl;
    127 #elif defined(i960rp)
    128 BSP_EXTERN i960rp_control_table *Ctl_tbl;
    129 #else
    130 #error "invalid processor selection!"
    131 #endif
    132 */
     121BSP_EXTERN i960_PRCB          *Prcb;
     122BSP_EXTERN i960_control_table *Ctl_tbl;
    133123
    134124/*
  • c/src/lib/libbsp/i960/rxgen960/include/rxgen960_config.h

    r2ea8df3 rae7325bd  
    99/* The following define the PMC960 bus regions */
    1010/* Bus configuration */
    11 #define RP_CONFIG_REGS     BUS_WIDTH(32)
    12 #define FLASH              BUS_WIDTH(8)
    13 #define DRAM               BUS_WIDTH(32)
    14 #define UART_LED           BUS_WIDTH(8)
    15 #define DEFAULT            BUS_WIDTH(32)
     11#define RP_CONFIG_REGS     I960RP_BUS_WIDTH(32)
     12#define FLASH              I960RP_BUS_WIDTH(8)
     13#define DRAM               I960RP_BUS_WIDTH(32)
     14#define UART_LED           I960RP_BUS_WIDTH(8)
     15#define DEFAULT            I960RP_BUS_WIDTH(32)
    1616
    1717/* Region Configuration */
     
    2424#define  REGION_C_CONFIG      UART_LED
    2525#define  REGION_E_CONFIG      DEFAULT
    26 /* #define  REGION_BOOT_CONFIG   (FLASH | BYTE_ORDER)*/
     26/* #define  REGION_BOOT_CONFIG   (FLASH | I960RP_ZBYTE_ORDER)*/
    2727#define  REGION_BOOT_CONFIG   (DRAM)
    2828
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