Changeset ae7325bd in rtems


Ignore:
Timestamp:
Oct 27, 1999, 5:25:53 PM (22 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
2bdc1e98
Parents:
2ea8df3
Message:

rxgen960 now compiles -- may not link.

Files:
14 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/i960/cpu.c

    r2ea8df3 rae7325bd  
    6868
    6969#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
    70 #define _Is_vector_caching_enabled( _prcb ) \
     70#define i960_vector_caching_enabled( _prcb ) \
    7171   ((_prcb)->control_tbl->icon & 0x2000)
    7272#elif defined(__i960RP__)
    73 #define _Is_vector_caching_enabled( _prcb ) \
     73#define i960_vector_caching_enabled( _prcb ) \
    7474   ((*((unsigned int *) ICON_ADDR)) & 0x2000)
    7575#endif
     
    9494  prcb->intr_tbl[ vector + 1 ] = new_handler;
    9595
    96   if ( _Is_vector_caching_enabled( prcb ) )
     96  if ( i960_vector_caching_enabled( prcb ) )
    9797    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
    9898      cached_intr_tbl[ vector >> 4 ] = new_handler;
  • c/src/exec/score/cpu/i960/i960RP.h

    r2ea8df3 rae7325bd  
    271271/* Byte order bit for region configuration */
    272272/* Set to Little Endian for the 80960RP*/
    273 #define BYTE_ORDER BIG_ENDIAN(0)
    274 #define BUS_WIDTH(bw)  ((bw==16)?(1<<22):(0)) | ((bw==32)?(2<<22):(0))
    275 #define BIG_ENDIAN(on) ((on)?(0x1<<31):0)
    276 #define BYTE_N(n,data)  (((unsigned)(data) >> (n*8)) & 0xFF)
    277 #define BUS_WIDTH_8 0
    278 #define BUS_WIDTH_16 (1<<22)
    279 #define BUS_WIDTH_32 (1<<23)
     273#define I960RP_BYTE_ORDER I960RP_BIG_ENDIAN(0)
     274#define I960RP_BUS_WIDTH(bw)  ((bw==16)?(1<<22):(0)) | ((bw==32)?(2<<22):(0))
     275#define I960RP_BIG_ENDIAN(on) ((on)?(0x1<<31):0)
     276#define I960RP_BYTE_N(n,data)  (((unsigned)(data) >> (n*8)) & 0xFF)
     277#define I960RP_BUS_WIDTH_8 0
     278#define I960RP_BUS_WIDTH_16 (1<<22)
     279#define I960RP_BUS_WIDTH_32 (1<<23)
    280280
    281281
  • c/src/lib/libbsp/i960/rxgen960/console/Makefile.in

    r2ea8df3 rae7325bd  
    1717
    1818# C source names, if any, go here -- minus the .c
    19 C_PIECES = console pcimsgreg
     19C_PIECES = console
    2020C_FILES = $(C_PIECES:%=%.c)
    2121C_O_FILES = $(C_PIECES:%=${ARCH}/%.o)
  • c/src/lib/libbsp/i960/rxgen960/console/console.c

    r2ea8df3 rae7325bd  
    2222#include <rtems/libio.h>
    2323#include "concntl.h"
    24 #include "pcimsgreg.h"
     24/* #include "pcimsgreg.h" XXX JRS */
    2525
    2626#ifndef lint
  • c/src/lib/libbsp/i960/rxgen960/include/bsp.h

    r2ea8df3 rae7325bd  
    9191 */
    9292
    93 static inline PRCB *get_prcb( void )
     93static inline i960_PRCB *get_prcb( void )
    9494{
    95   register PRCB *_prcb = 0;
     95  register i960_PRCB *_prcb = 0;
    9696
    9797  asm volatile( "calls 5; \
     
    119119extern rtems_configuration_table BSP_Configuration;
    120120
    121 BSP_EXTERN PRCB          *Prcb;
    122 BSP_EXTERN CNTL_TBL      *Ctl_tbl;
    123 
    124 /*
    125 #if defined(i960ca)
    126 BSP_EXTERN i960ca_control_table *Ctl_tbl;
    127 #elif defined(i960rp)
    128 BSP_EXTERN i960rp_control_table *Ctl_tbl;
    129 #else
    130 #error "invalid processor selection!"
    131 #endif
    132 */
     121BSP_EXTERN i960_PRCB          *Prcb;
     122BSP_EXTERN i960_control_table *Ctl_tbl;
    133123
    134124/*
  • c/src/lib/libbsp/i960/rxgen960/include/rxgen960_config.h

    r2ea8df3 rae7325bd  
    99/* The following define the PMC960 bus regions */
    1010/* Bus configuration */
    11 #define RP_CONFIG_REGS     BUS_WIDTH(32)
    12 #define FLASH              BUS_WIDTH(8)
    13 #define DRAM               BUS_WIDTH(32)
    14 #define UART_LED           BUS_WIDTH(8)
    15 #define DEFAULT            BUS_WIDTH(32)
     11#define RP_CONFIG_REGS     I960RP_BUS_WIDTH(32)
     12#define FLASH              I960RP_BUS_WIDTH(8)
     13#define DRAM               I960RP_BUS_WIDTH(32)
     14#define UART_LED           I960RP_BUS_WIDTH(8)
     15#define DEFAULT            I960RP_BUS_WIDTH(32)
    1616
    1717/* Region Configuration */
     
    2424#define  REGION_C_CONFIG      UART_LED
    2525#define  REGION_E_CONFIG      DEFAULT
    26 /* #define  REGION_BOOT_CONFIG   (FLASH | BYTE_ORDER)*/
     26/* #define  REGION_BOOT_CONFIG   (FLASH | I960RP_ZBYTE_ORDER)*/
    2727#define  REGION_BOOT_CONFIG   (DRAM)
    2828
  • c/src/lib/libbsp/i960/rxgen960/startup/asmstub.S

    r2ea8df3 rae7325bd  
    6565_asm_ipend:
    6666        chkbit   0, g1
    67         alterbit g0, sf0, sf0
     67        /* alterbit g0, sf0, sf0 XXX JRS */
    6868        ret
    6969########################################################################
     
    8383_asm_imask:
    8484        chkbit   0, g1
    85         alterbit g0, sf1, sf1
     85        /* alterbit g0, sf1, sf1 XXX JRS */
    8686        ret
    8787
     
    101101        .text
    102102_asm_get_imask:
    103         mov             sf1, g0
     103        /* mov          sf1, g0 XXX JRS */
    104104        ret
    105105
  • c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.c

    r2ea8df3 rae7325bd  
    2121
    2222/* Bus configuration */
    23 #define RP_CONFIG_REGS     BUS_WIDTH_32
    24 #define FLASH              BUS_WIDTH_8
    25 #define DRAM               BUS_WIDTH_32
    26 #define UART_LED           BUS_WIDTH_8
    27 #define DEFAULT            BUS_WIDTH_32
     23#define RP_CONFIG_REGS     I960RP_BUS_WIDTH_32
     24#define FLASH              I960RP_BUS_WIDTH_8
     25#define DRAM               I960RP_BUS_WIDTH_32
     26#define UART_LED           I960RP_BUS_WIDTH_8
     27#define DEFAULT            I960RP_BUS_WIDTH_32
    2828
    2929/* Region Configuration */
  • c/src/lib/libbsp/i960/rxgen960/startup/fault.c

    r2ea8df3 rae7325bd  
    7171      /* Check sum has changed.
    7272       */
    73 #ifdef 0
     73#if 0
    7474    faultCheckSum = faultNewCheckSum();
    7575#endif
     
    9696      * whatever you want.
    9797      */
    98 # ifdef 0
     98#if 0
    9999  if (OsfIsUp)  {   
    100100    asm_exit(romFaultStart, & ram_prcb);
     
    118118      /* Check sum has changed.
    119119       */
    120 #ifdef 0
     120#if 0
    121121    faultCheckSum = faultNewCheckSum();
    122122#endif
  • c/src/lib/libbsp/i960/rxgen960/startup/rom_cntrltbl.c

    r2ea8df3 rae7325bd  
    2121
    2222/* Bus configuration */
    23 #define RP_CONFIG_REGS     BUS_WIDTH_32
    24 #define FLASH              BUS_WIDTH_8
    25 #define DRAM               BUS_WIDTH_32
    26 #define UART_LED           BUS_WIDTH_8
    27 #define DEFAULT            BUS_WIDTH_32
     23#define RP_CONFIG_REGS     I960RP_BUS_WIDTH_32
     24#define FLASH              I960RP_BUS_WIDTH_8
     25#define DRAM               I960RP_BUS_WIDTH_32
     26#define UART_LED           I960RP_BUS_WIDTH_8
     27#define DEFAULT            I960RP_BUS_WIDTH_32
    2828
    2929/* Region Configuration */
  • c/src/lib/libbsp/i960/rxgen960/startup/rxgen_romld.S

    r2ea8df3 rae7325bd  
    8181        mov     0, g14
    8282
    83         ldconst 0, sf0
     83        /* ldconst      0, sf0 XXX JRS */
    8484/*
    8585          # To get ready to invoke procedures.
  • c/src/lib/libbsp/i960/rxgen960/timer/Makefile.in

    r2ea8df3 rae7325bd  
    2424
    2525# Assembly source names, if any, go here -- minus the .S
    26 S_PIECES = timerisr
     26S_PIECES =
    2727S_FILES = $(S_PIECES:%=%.S)
    2828S_O_FILES = $(S_FILES:%.S=${ARCH}/%.o)
  • c/src/lib/libbsp/i960/rxgen960/timer/timerisr.S

    r2ea8df3 rae7325bd  
    5151        st      r6,_Ttimer_val           # increment test timer
    5252loop_til_cleared:
    53         clrbit 4,sf0,sf0
    54         bbs    4,sf0,loop_til_cleared
     53        /* clrbit 4,sf0,sf0 XXX JRS */
     54        /* bbs    4,sf0,loop_til_cleared XXX JRS */
    5555leaf:   ret
    5656
  • cpukit/score/cpu/i960/cpu.c

    r2ea8df3 rae7325bd  
    6868
    6969#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
    70 #define _Is_vector_caching_enabled( _prcb ) \
     70#define i960_vector_caching_enabled( _prcb ) \
    7171   ((_prcb)->control_tbl->icon & 0x2000)
    7272#elif defined(__i960RP__)
    73 #define _Is_vector_caching_enabled( _prcb ) \
     73#define i960_vector_caching_enabled( _prcb ) \
    7474   ((*((unsigned int *) ICON_ADDR)) & 0x2000)
    7575#endif
     
    9494  prcb->intr_tbl[ vector + 1 ] = new_handler;
    9595
    96   if ( _Is_vector_caching_enabled( prcb ) )
     96  if ( i960_vector_caching_enabled( prcb ) )
    9797    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
    9898      cached_intr_tbl[ vector >> 4 ] = new_handler;
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