Changeset ae2b1e0 in rtems


Ignore:
Timestamp:
Jun 7, 2011, 12:59:39 PM (9 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
b81c3dec
Parents:
95fe2fd
Message:

2011-06-07 Sebastian Huber <sebastian.huber@…>

  • new-exceptions/cpu_asm.S: Use BSP_DATA_CACHE_ENABLED instead of PPC_USE_DATA_CACHE.
Location:
c/src/lib/libcpu/powerpc
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/ChangeLog

    r95fe2fd rae2b1e0  
     12011-06-07      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * new-exceptions/cpu_asm.S: Use BSP_DATA_CACHE_ENABLED instead of
     4        PPC_USE_DATA_CACHE.
     5
    162011-06-07      Sebastian Huber <sebastian.huber@embedded-brains.de>
    27
  • c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S

    r95fe2fd rae2b1e0  
    294294        isync
    295295        /* This assumes that all the registers are in the given order */
    296 #if ( PPC_USE_DATA_CACHE )
     296#if ( BSP_DATA_CACHE_ENABLED )
    297297#if PPC_CACHE_ALIGNMENT != 32
    298298#error "code assumes PPC_CACHE_ALIGNMENT == 32!"
     
    301301#endif
    302302        addi    r9,r3,-4
    303 #if ( PPC_USE_DATA_CACHE )
     303#if ( BSP_DATA_CACHE_ENABLED )
    304304        dcbz    r5, r9
    305305#endif
     
    308308#if (PPC_USE_MULTIPLE == 1)
    309309        addi    r9, r9, GP_18+4
    310 #if ( PPC_USE_DATA_CACHE )
     310#if ( BSP_DATA_CACHE_ENABLED )
    311311        dcbz    r5, r9
    312312#endif
     
    319319        stw     r17, GP_17+4(r9)
    320320        stwu    r18, GP_18+4(r9)
    321 #if ( PPC_USE_DATA_CACHE )
     321#if ( BSP_DATA_CACHE_ENABLED )
    322322        dcbz    r5, r9
    323323#endif
     
    336336        stw     r31, GP_31-GP_18(r9)
    337337#endif
    338 #if ( PPC_USE_DATA_CACHE )
     338#if ( BSP_DATA_CACHE_ENABLED )
    339339        dcbt    r0, r4
    340340#endif
     
    351351        bl              _CPU_Context_switch_altivec
    352352        mr      r4, r14
    353 #if ( PPC_USE_DATA_CACHE )
     353#if ( BSP_DATA_CACHE_ENABLED )
    354354        li      r5, PPC_CACHE_ALIGNMENT
    355355#endif
    356356#endif
    357357
    358 #if ( PPC_USE_DATA_CACHE )
     358#if ( BSP_DATA_CACHE_ENABLED )
    359359        dcbt    r5, r4
    360360#endif
     
    363363#if (PPC_USE_MULTIPLE == 1)
    364364        addi    r4, r4, GP_19
    365 #if ( PPC_USE_DATA_CACHE )
     365#if ( BSP_DATA_CACHE_ENABLED )
    366366        dcbt    r5, r4
    367367#endif
     
    375375        lwz     r18, GP_18(r4)
    376376        lwzu    r19, GP_19(r4)
    377 #if ( PPC_USE_DATA_CACHE )
     377#if ( BSP_DATA_CACHE_ENABLED )
    378378        dcbt    r5, r4
    379379#endif
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