Changeset ae20a3e2 in rtems


Ignore:
Timestamp:
Jul 18, 2003, 5:24:18 PM (18 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
7b59de1c
Parents:
674b9497
Message:

2003-07-18 Till Straumann <strauman@…>

PR 288/rtems

  • irq/irq_asm.S, startup/bspstart.c: _ISR_Nest_level is now properly maintained.
Location:
c/src/lib/libbsp/powerpc
Files:
6 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/eth_comm/ChangeLog

    r674b9497 rae20a3e2  
     12003-07-18      Till Straumann <strauman@slac.stanford.edu>
     2
     3        PR 288/rtems
     4        * irq/irq_asm.S, startup/bspstart.c: _ISR_Nest_level is now properly
     5        maintained.
     6
    172003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    28
  • c/src/lib/libbsp/powerpc/eth_comm/irq/irq_asm.S

    r674b9497 rae20a3e2  
    1010 *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
    1111 *
     12 *  Till Straumann <strauman@slac.stanford.edu>, 2003/7:
     13 *    - store isr nesting level in _ISR_Nest_level rather than
     14 *      SPRG0 - RTEMS relies on that variable.
    1215 *
    1316 * $Id$
     
    137140         */
    138141        addis r15,0, _Thread_Dispatch_disable_level@ha
     142#if BROKEN_ISR_NEST_LEVEL
    139143        /*
    140144         * Get current nesting level in R2
    141145         */
    142146        mfspr   r2, SPRG0
     147#else
     148        /*
     149         * Retrieve current nesting level from _ISR_Nest_level
     150         */
     151        lis             r7, _ISR_Nest_level@ha
     152        lwz             r2, _ISR_Nest_level@l(r7)
     153#endif
    143154        /*
    144155         * Check if stack switch is necessary
     
    157168         */
    158169        lwz     r6,_Thread_Dispatch_disable_level@l(r15)
    159         /*
    160          * store new nesting level in SPRG0
     170#if BROKEN_ISR_NEST_LEVEL
     171        /*
     172         * Store new nesting level in SPRG0
    161173         */
    162174        mtspr   SPRG0, r2
     175#else
     176        /* store new nesting level in _ISR_Nest_level */
     177        stw             r2, _ISR_Nest_level@l(r7)
     178#endif
    163179       
    164180        addi    r6, r6, 1
     
    184200         * then _Thread_Dispatch_disable_level > 1
    185201         */
     202#if BROKEN_ISR_NEST_LEVEL
    186203        mfspr   r2, SPRG0
     204#else
     205        lis             r7, _ISR_Nest_level@ha
     206        lwz             r2, _ISR_Nest_level@l(r7)
     207#endif
    187208        /*
    188209         * start decrementing _Thread_Dispatch_disable_level
     
    191212        addi    r2, r2, -1      /* Continue decrementing nesting level */
    192213        addi    r3, r3, -1      /* Continue decrementing _Thread_Dispatch_disable_level */
     214#if BROKEN_ISR_NEST_LEVEL
    193215        mtspr   SPRG0, r2       /* End decrementing nesting level */
     216#else
     217        stw             r2, _ISR_Nest_level@l(r7) /* End decrementing nesting level */
     218#endif
    194219        stw     r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */
    195220        cmpwi   r3, 0
  • c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c

    r674b9497 rae20a3e2  
    2626#include <info.h>
    2727#include <libcpu/cpuIdent.h>
     28#include <libcpu/spr.h>
    2829#include <rtems/bspIo.h>
    2930
     
    109110}
    110111
     112SPR_RW(SPRG0)
     113SPR_RW(SPRG1)
    111114
    112115void bsp_start(void)
     
    118121  ppc_cpu_revision_t myCpuRevision;
    119122  register unsigned char* intrStack;
    120   register unsigned int intrNestingLevel = 0;
    121123  extern void cpu_init(void);
    122124   
     
    135137   
    136138  intrStack = (((unsigned char*)&intrStackPtr) - CPU_MINIMUM_STACK_FRAME_SIZE);
    137   asm volatile ("mtspr  273, %0" : "=r" (intrStack) : "0" (intrStack));
    138   asm volatile ("mtspr  272, %0" : "=r" (intrNestingLevel) : "0" (intrNestingLevel));
     139
     140  _write_SPRG1((unsigned int)intrStack);
     141
     142  /* Signal them that this BSP has fixed PR288 - eventually, this should go away */
     143  _write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
    139144 
    140145   /*
  • c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog

    r674b9497 rae20a3e2  
     12003-07-18      Till Straumann <strauman@slac.stanford.edu>
     2
     3        PR 288/rtems
     4        * irq/irq_asm.S, startup/bspstart.c: _ISR_Nest_level is now properly
     5        maintained.
     6
    172003-04-04       Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    28
  • c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S

    r674b9497 rae20a3e2  
    1010 *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
    1111 *
     12 *  Till Straumann <strauman@slac.stanford.edu>, 2003/7:
     13 *    - store isr nesting level in _ISR_Nest_level rather than
     14 *      SPRG0 - RTEMS relies on that variable.
    1215 *
    1316 * $Id$
     
    177180         */
    178181        addis r15,0, _Thread_Dispatch_disable_level@ha
     182#if BROKEN_ISR_NEST_LEVEL
    179183        /*
    180184         * Get current nesting level in R2
    181185         */
    182186        mfspr   r2, SPRG0
     187#else
     188        /*
     189         * Retrieve current nesting level from _ISR_Nest_level
     190         */
     191        lis             r7, _ISR_Nest_level@ha
     192        lwz             r2, _ISR_Nest_level@l(r7)
     193#endif
    183194        /*
    184195         * Check if stack switch is necessary
     
    197208         */
    198209        lwz     r6,_Thread_Dispatch_disable_level@l(r15)
    199         /*
    200          * store new nesting level in SPRG0
     210#if BROKEN_ISR_NEST_LEVEL
     211        /*
     212         * Store new nesting level in SPRG0
    201213         */
    202214        mtspr   SPRG0, r2
     215#else
     216        /* store new nesting level in _ISR_Nest_level */
     217        stw             r2, _ISR_Nest_level@l(r7)
     218#endif
    203219       
    204220        addi    r6, r6, 1
     
    224240         * then _Thread_Dispatch_disable_level > 1
    225241         */
     242#if BROKEN_ISR_NEST_LEVEL
    226243        mfspr   r2, SPRG0
     244#else
     245        lis             r7, _ISR_Nest_level@ha
     246        lwz             r2, _ISR_Nest_level@l(r7)
     247#endif
    227248        /*
    228249         * start decrementing _Thread_Dispatch_disable_level
     
    231252        addi    r2, r2, -1      /* Continue decrementing nesting level */
    232253        addi    r3, r3, -1      /* Continue decrementing _Thread_Dispatch_disable_level */
     254#if BROKEN_ISR_NEST_LEVEL
    233255        mtspr   SPRG0, r2       /* End decrementing nesting level */
     256#else
     257        stw             r2, _ISR_Nest_level@l(r7) /* End decrementing nesting level */
     258#endif
    234259        stw     r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */
    235260        cmpwi   r3, 0
  • c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c

    r674b9497 rae20a3e2  
    2727#include <rtems/bspIo.h>
    2828#include <libcpu/cpuIdent.h>
     29#include <libcpu/spr.h>
     30
     31
     32SPR_RW(SPRG0)
     33SPR_RW(SPRG1)
    2934
    3035/*
     
    135140  ppc_cpu_revision_t myCpuRevision;
    136141  register unsigned char* intrStack;
    137   register unsigned int intrNestingLevel = 0;
    138142 
    139143  /*
     
    167171 
    168172  intrStack = (((unsigned char*)&intrStackPtr) - CPU_MINIMUM_STACK_FRAME_SIZE);
    169   asm volatile ("mtspr  273, %0" : "=r" (intrStack) : "0" (intrStack));
    170   asm volatile ("mtspr  272, %0" : "=r" (intrNestingLevel) : "0" (intrNestingLevel));
     173  _write_SPRG1((unsigned int)intrStack);
     174  /* signal them that we have fixed PR288 - eventually, this should go away */
     175  _write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
    171176
    172177  /*
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