Changeset ad17f7f in rtems
- Timestamp:
- 10/21/04 13:24:40 (19 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- d4d624e2
- Parents:
- ee5769ad
- Location:
- c/src/lib/libcpu/powerpc
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libcpu/powerpc/ChangeLog
ree5769ad rad17f7f 1 2004-10-21 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * mpc5xx/clock/clock.c, mpc5xx/include/mpc5xx.h 4 mpc5xx/timer/timer.c: Use POSIX fixed size types. 5 1 6 2004-10-20 Eric Norum <norume@aps.anl.gov> 2 7 3 8 Add Kate Feng's MPC7455 support 4 9 * configure.ac 5 * mpc6xx/exceptions/raw_exception.c6 * mpc6xx/mmu/mmuAsm.S7 8 * shared/include/cpuIdent.c9 * shared/include/cpuIdent.h10 * mpc6xx/exceptions/raw_exception.c 11 * mpc6xx/mmu/mmuAsm.S 12 * mpc6xx/mmu/pte121.c 13 * shared/include/cpuIdent.c 14 * shared/include/cpuIdent.h 10 15 11 16 2004-10-19 Ralf Corsepius <ralf_corsepius@rtems.org> -
c/src/lib/libcpu/powerpc/mpc5xx/clock/clock.c
ree5769ad rad17f7f 50 50 #include <mpc5xx.h> 51 51 52 volatile rtems_unsigned32Clock_driver_ticks;52 volatile uint32_t Clock_driver_ticks; 53 53 extern int BSP_connect_clock_handler(rtems_isr_entry); 54 54 extern int BSP_disconnect_clock_handler(); … … 79 79 { 80 80 unsigned desiredLevel; 81 rtems_unsigned32pit_value;81 uint32_t pit_value; 82 82 83 83 /* calculate and set modulus */ -
c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h
ree5769ad rad17f7f 185 185 ************************************************************************* 186 186 */ 187 #define USIU_MEMC_BR_BA(x) ((( rtems_unsigned32)x)&0xffff8000)187 #define USIU_MEMC_BR_BA(x) (((uint32_t)x)&0xffff8000) 188 188 /* Base address */ 189 189 #define USIU_MEMC_BR_AT(x) ((x)<<12) /* Address type */ … … 390 390 */ 391 391 typedef struct m5xxMEMCRegisters_ { 392 rtems_unsigned32_br;393 rtems_unsigned32_or; /* Used to be called 'or'; reserved ANSI C++ keyword */392 uint32_t _br; 393 uint32_t _or; /* Used to be called 'or'; reserved ANSI C++ keyword */ 394 394 } m5xxMEMCRegisters_t; 395 395 … … 401 401 * SIU Block 402 402 */ 403 rtems_unsigned32siumcr;404 rtems_unsigned32sypcr;405 rtems_unsigned32_pad70;406 rtems_unsigned16_pad0;407 rtems_unsigned16swsr;408 rtems_unsigned32sipend;409 rtems_unsigned32simask;410 rtems_unsigned32siel;411 rtems_unsigned32sivec;412 rtems_unsigned32tesr;413 rtems_unsigned32sgpiodt1;414 rtems_unsigned32sgpiodt2;415 rtems_unsigned32sgpiocr;416 rtems_unsigned32emcr;417 rtems_unsigned8_pad71[0x03C-0x034];418 rtems_unsigned32pdmcr;419 rtems_unsigned8_pad2[0x100-0x40];403 uint32_t siumcr; 404 uint32_t sypcr; 405 uint32_t _pad70; 406 uint16_t _pad0; 407 uint16_t swsr; 408 uint32_t sipend; 409 uint32_t simask; 410 uint32_t siel; 411 uint32_t sivec; 412 uint32_t tesr; 413 uint32_t sgpiodt1; 414 uint32_t sgpiodt2; 415 uint32_t sgpiocr; 416 uint32_t emcr; 417 uint8_t _pad71[0x03C-0x034]; 418 uint32_t pdmcr; 419 uint8_t _pad2[0x100-0x40]; 420 420 421 421 /* … … 423 423 */ 424 424 m5xxMEMCRegisters_t memc[4]; 425 rtems_unsigned8_pad7[0x140-0x120];426 rtems_unsigned32dmbr;427 rtems_unsigned32dmor;428 rtems_unsigned8_pad8[0x178-0x148];429 rtems_unsigned16mstat;430 rtems_unsigned8_pad9[0x200-0x17A];425 uint8_t _pad7[0x140-0x120]; 426 uint32_t dmbr; 427 uint32_t dmor; 428 uint8_t _pad8[0x178-0x148]; 429 uint16_t mstat; 430 uint8_t _pad9[0x200-0x17A]; 431 431 432 432 /* 433 433 * System integration timers 434 434 */ 435 rtems_unsigned16tbscr;436 rtems_unsigned16_pad10;437 rtems_unsigned32tbreff0;438 rtems_unsigned32tbreff1;439 rtems_unsigned8_pad11[0x220-0x20c];440 rtems_unsigned16rtcsc;441 rtems_unsigned16_pad12;442 rtems_unsigned32rtc;443 rtems_unsigned32rtsec;444 rtems_unsigned32rtcal;445 rtems_unsigned32_pad13[4];446 rtems_unsigned16piscr;447 rtems_unsigned16_pad14;448 rtems_unsigned16pitc;449 rtems_unsigned16_pad_14_1;450 rtems_unsigned16pitr;451 rtems_unsigned16_pad_14_2;452 rtems_unsigned8_pad15[0x280-0x24c];435 uint16_t tbscr; 436 uint16_t _pad10; 437 uint32_t tbreff0; 438 uint32_t tbreff1; 439 uint8_t _pad11[0x220-0x20c]; 440 uint16_t rtcsc; 441 uint16_t _pad12; 442 uint32_t rtc; 443 uint32_t rtsec; 444 uint32_t rtcal; 445 uint32_t _pad13[4]; 446 uint16_t piscr; 447 uint16_t _pad14; 448 uint16_t pitc; 449 uint16_t _pad_14_1; 450 uint16_t pitr; 451 uint16_t _pad_14_2; 452 uint8_t _pad15[0x280-0x24c]; 453 453 454 454 /* 455 455 * Clocks and Reset 456 456 */ 457 rtems_unsigned32sccr;458 rtems_unsigned32plprcr;459 rtems_unsigned16rsr;460 rtems_unsigned16_pad72;461 rtems_unsigned16colir;462 rtems_unsigned16_pad73;463 rtems_unsigned16vsrmcr;464 rtems_unsigned8_pad16[0x300-0x292];457 uint32_t sccr; 458 uint32_t plprcr; 459 uint16_t rsr; 460 uint16_t _pad72; 461 uint16_t colir; 462 uint16_t _pad73; 463 uint16_t vsrmcr; 464 uint8_t _pad16[0x300-0x292]; 465 465 466 466 /* 467 467 * System integration timers keys 468 468 */ 469 rtems_unsigned32tbscrk;470 rtems_unsigned32tbreff0k;471 rtems_unsigned32tbreff1k;472 rtems_unsigned32tbk;473 rtems_unsigned32_pad17[4];474 rtems_unsigned32rtcsk;475 rtems_unsigned32rtck;476 rtems_unsigned32rtseck;477 rtems_unsigned32rtcalk;478 rtems_unsigned32_pad18[4];479 rtems_unsigned32piscrk;480 rtems_unsigned32pitck;481 rtems_unsigned8_pad19[0x380-0x348];469 uint32_t tbscrk; 470 uint32_t tbreff0k; 471 uint32_t tbreff1k; 472 uint32_t tbk; 473 uint32_t _pad17[4]; 474 uint32_t rtcsk; 475 uint32_t rtck; 476 uint32_t rtseck; 477 uint32_t rtcalk; 478 uint32_t _pad18[4]; 479 uint32_t piscrk; 480 uint32_t pitck; 481 uint8_t _pad19[0x380-0x348]; 482 482 483 483 /* 484 484 * Clocks and Reset Keys 485 485 */ 486 rtems_unsigned32sccrk;487 rtems_unsigned32plprck;488 rtems_unsigned32rsrk;489 rtems_unsigned8_pad20[0x400-0x38c];486 uint32_t sccrk; 487 uint32_t plprck; 488 uint32_t rsrk; 489 uint8_t _pad20[0x400-0x38c]; 490 490 } usiu_t; 491 491 … … 502 502 */ 503 503 typedef struct m5xxDPTRAMRegisters_ { 504 rtems_unsigned8pad[0x4000]; /* define later */504 uint8_t pad[0x4000]; /* define later */ 505 505 } m5xxDPTRAMRegisters_t; 506 506 … … 509 509 */ 510 510 typedef struct m5xxTPU3Registers_ { 511 rtems_unsigned8pad[0x400]; /* define later */511 uint8_t pad[0x400]; /* define later */ 512 512 } m5xxTPU3Registers_t; 513 513 … … 516 516 */ 517 517 typedef struct m5xxQADC64Registers_ { 518 rtems_unsigned8pad[0x400]; /* define later */518 uint8_t pad[0x400]; /* define later */ 519 519 } m5xxQADC64Registers_t; 520 520 … … 523 523 */ 524 524 typedef struct m5xxSCIRegisters_ { 525 rtems_unsigned16sccr0;526 rtems_unsigned16sccr1;527 rtems_unsigned16scsr;528 rtems_unsigned16scdr;525 uint16_t sccr0; 526 uint16_t sccr1; 527 uint16_t scsr; 528 uint16_t scdr; 529 529 } m5xxSCIRegisters_t; 530 530 … … 533 533 */ 534 534 typedef struct m5xxSPIRegisters_ { 535 rtems_unsigned16spcr0;536 rtems_unsigned16spcr1;537 rtems_unsigned16spcr2;538 rtems_unsigned8spcr3;539 rtems_unsigned8spsr;535 uint16_t spcr0; 536 uint16_t spcr1; 537 uint16_t spcr2; 538 uint8_t spcr3; 539 uint8_t spsr; 540 540 } m5xxSPIRegisters_t; 541 541 … … 544 544 */ 545 545 typedef struct m5xxQSMCMRegisters_ { 546 rtems_unsigned16qsmcmmcr;547 rtems_unsigned16qtest;548 rtems_unsigned16qdsci_il;549 rtems_unsigned16qspi_il;546 uint16_t qsmcmmcr; 547 uint16_t qtest; 548 uint16_t qdsci_il; 549 uint16_t qspi_il; 550 550 551 551 m5xxSCIRegisters_t sci1; 552 552 553 rtems_unsigned8_pad10[0x14-0x10];554 555 rtems_unsigned16portqs;556 rtems_unsigned16pqspar;553 uint8_t _pad10[0x14-0x10]; 554 555 uint16_t portqs; 556 uint16_t pqspar; 557 557 m5xxSPIRegisters_t spi; 558 558 559 559 m5xxSCIRegisters_t sci2; 560 560 561 rtems_unsigned16qsci1cr;562 rtems_unsigned16qsci1sr;563 rtems_unsigned16sctq[0x10];564 rtems_unsigned16scrq[0x10];565 566 rtems_unsigned8_pad6C[0x140-0x06C];567 568 rtems_unsigned16recram[0x20];569 rtems_unsigned16tranram[0x20];570 rtems_unsigned16comdram[0x20];561 uint16_t qsci1cr; 562 uint16_t qsci1sr; 563 uint16_t sctq[0x10]; 564 uint16_t scrq[0x10]; 565 566 uint8_t _pad6C[0x140-0x06C]; 567 568 uint16_t recram[0x20]; 569 uint16_t tranram[0x20]; 570 uint16_t comdram[0x20]; 571 571 } m5xxQSMCMRegisters_t; 572 572 … … 575 575 */ 576 576 typedef struct m5xxMIOS1Registers_ { 577 rtems_unsigned8pad[0x1000]; /* define later */577 uint8_t pad[0x1000]; /* define later */ 578 578 } m5xxMIOS1Registers_t; 579 579 … … 582 582 */ 583 583 typedef struct m5xxTouCANRegisters_ { 584 rtems_unsigned8pad[0x400]; /* define later */584 uint8_t pad[0x400]; /* define later */ 585 585 } m5xxTouCANRegisters_t; 586 586 … … 589 589 */ 590 590 typedef struct m5xxUIMBRegisters_ { 591 rtems_unsigned32umcr;592 rtems_unsigned32utstcreg;593 rtems_unsigned32uipend;591 uint32_t umcr; 592 uint32_t utstcreg; 593 uint32_t uipend; 594 594 } m5xxUIMBRegisters_t; 595 595 … … 602 602 m5xxQADC64Registers_t qadc[2]; 603 603 m5xxQSMCMRegisters_t qsmcm; 604 rtems_unsigned8_pad5200[0x6000-0x5200];604 uint8_t _pad5200[0x6000-0x5200]; 605 605 m5xxMIOS1Registers_t mios; 606 606 m5xxTouCANRegisters_t toucan[2]; 607 rtems_unsigned8_pad7800[0x7F80-0x7800];607 uint8_t _pad7800[0x7F80-0x7800]; 608 608 m5xxUIMBRegisters_t uimb; 609 609 } imb_t; -
c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c
ree5769ad rad17f7f 52 52 #include <mpc5xx.h> 53 53 54 static volatile rtems_unsigned32Timer_starting;54 static volatile uint32_t Timer_starting; 55 55 static rtems_boolean Timer_driver_Find_average_overhead; 56 56 … … 58 58 * This is so small that this code will be reproduced where needed. 59 59 */ 60 static inline rtems_unsigned32get_itimer(void)60 static inline uint32_t get_itimer(void) 61 61 { 62 rtems_unsigned32ret;62 uint32_t ret; 63 63 64 64 asm volatile ("mftb %0" : "=r" ((ret))); /* TBLO */ … … 90 90 int Read_timer(void) 91 91 { 92 rtems_unsigned32clicks;93 rtems_unsigned32total;92 uint32_t clicks; 93 uint32_t total; 94 94 95 95 clicks = get_itimer();
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