Ignore:
Timestamp:
Apr 21, 2005, 12:25:53 AM (16 years ago)
Author:
Eric Norum <WENorum@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
6d4ad17
Parents:
4279a35
Message:

Try insructioin-only cache.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c

    r4279a35 rac9bbe7  
    7070 * DATECODES AFFECTED: All
    7171 */
    72 #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr ; nop" : : "d" (_cacr))
     72#define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
     73#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
    7374#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
    7475#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
     
    7677/*
    7778 * Read/write copy of cache registers
    78  *   Split I/D cache
     79 *   Split instruction/data or instruction-only
    7980 *   Allow CPUSHL to invalidate a cache line
    8081 *   Enable buffered writes
     
    8384 */
    8485uint32_t mcf5282_cacr_mode = MCF5XXX_CACR_CENB |
     86#ifndef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
     87                             MCF5XXX_CACR_DISD |
     88#endif
    8589                             MCF5XXX_CACR_DBWE |
    8690                             MCF5XXX_CACR_DCM;
     
    123127void _CPU_cache_invalidate_entire_instruction(void)
    124128{
    125     m68k_set_cacr(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
     129    m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
    126130}
    127131
     
    137141void _CPU_cache_enable_data(void)
    138142{
     143#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
    139144    rtems_interrupt_level level;
    140145
    141146    rtems_interrupt_disable(level);
    142     mcf5282_cacr_mode &= ~MCF5XXX_CACR_DISD;
     147    mcf5282_cacr_mode &= ~MCF5XXX_CACR_CENB;
    143148    m68k_set_cacr(mcf5282_cacr_mode);
    144149    rtems_interrupt_enable(level);
     150#endif
    145151}
    146152
    147153void _CPU_cache_disable_data(void)
    148154{
     155#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
    149156    rtems_interrupt_level level;
    150157
    151158    rtems_interrupt_disable(level);
    152159    rtems_interrupt_disable(level);
    153     mcf5282_cacr_mode |= MCF5XXX_CACR_DISD;
     160    mcf5282_cacr_mode |= MCF5XXX_CACR_CENB;
    154161    m68k_set_cacr(mcf5282_cacr_mode);
    155162    rtems_interrupt_enable(level);
     163#endif
    156164}
    157165
    158166void _CPU_cache_invalidate_entire_data(void)
    159167{
    160     m68k_set_cacr(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
     168#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
     169    m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
     170#endif
    161171}
    162172
    163173void _CPU_cache_invalidate_1_data_line(const void *addr)
    164174{
     175#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
    165176    /*
    166177     * Bottom half of cache is D-space
     
    168179    addr = (void *)((int)addr & ~0x400);
    169180    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
     181#endif
    170182}
    171183
     
    221233    m68k_set_acr0(mcf5282_acr0_mode);
    222234    m68k_set_acr1(mcf5282_acr1_mode);
    223     m68k_set_cacr(MCF5XXX_CACR_CINV);
     235    m68k_set_cacr_nop(MCF5XXX_CACR_CINV);
    224236
    225237    /*
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