Changeset ac9bbe7 in rtems
- Timestamp:
- 04/21/05 00:25:53 (19 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 6d4ad173
- Parents:
- 4279a35
- Location:
- c/src/lib/libbsp/m68k/uC5282
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/m68k/uC5282/ChangeLog
r4279a35 rac9bbe7 1 2005-04-20 Eric Norum <norume@aps.anl.gov> 2 3 * startup/bspstart.c 4 * network/network.c: Try instruction-only cache. 5 1 6 2005-04-19 Eric Norum <norume@aps.anl.gov> 2 7 -
c/src/lib/libbsp/m68k/uC5282/include/bsp.h
r4279a35 rac9bbe7 16 16 #include <rtems/iosupp.h> 17 17 #include <rtems/bspIo.h> 18 19 /***************************************************************************/ 20 /** BSP Configuration **/ 21 /* 22 * Uncomment to use instruction/data cache 23 * Leave commented to use instruction-only cache 24 */ 25 /* #define RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE */ 18 26 19 27 /***************************************************************************/ -
c/src/lib/libbsp/m68k/uC5282/network/network.c
r4279a35 rac9bbe7 408 408 int len = rxBd->length - sizeof(uint32_t);; 409 409 410 /*411 * Invalidate the cache and push the packet up.412 * The cache is so small that it's more efficient to just413 * invalidate the whole thing unless the packet is very small.414 */415 410 m = sc->rxMbuf[rxBdIndex]; 411 #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE 412 /* 413 * Invalidate the cache. The cache is so small that it's 414 * more efficient to just invalidate the whole thing unless 415 * the packet is very small. 416 */ 416 417 if (len < 128) 417 418 rtems_cache_invalidate_multiple_data_lines(m->m_data, len); 418 419 else 419 420 rtems_cache_invalidate_entire_data(); 421 #endif 420 422 m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header); 421 423 eh = mtod(m, struct ether_header *); -
c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
r4279a35 rac9bbe7 70 70 * DATECODES AFFECTED: All 71 71 */ 72 #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr ; nop" : : "d" (_cacr)) 72 #define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr)) 73 #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr)) 73 74 #define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0)) 74 75 #define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1)) … … 76 77 /* 77 78 * Read/write copy of cache registers 78 * Split I/D cache79 * Split instruction/data or instruction-only 79 80 * Allow CPUSHL to invalidate a cache line 80 81 * Enable buffered writes … … 83 84 */ 84 85 uint32_t mcf5282_cacr_mode = MCF5XXX_CACR_CENB | 86 #ifndef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE 87 MCF5XXX_CACR_DISD | 88 #endif 85 89 MCF5XXX_CACR_DBWE | 86 90 MCF5XXX_CACR_DCM; … … 123 127 void _CPU_cache_invalidate_entire_instruction(void) 124 128 { 125 m68k_set_cacr (mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);129 m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); 126 130 } 127 131 … … 137 141 void _CPU_cache_enable_data(void) 138 142 { 143 #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE 139 144 rtems_interrupt_level level; 140 145 141 146 rtems_interrupt_disable(level); 142 mcf5282_cacr_mode &= ~MCF5XXX_CACR_ DISD;147 mcf5282_cacr_mode &= ~MCF5XXX_CACR_CENB; 143 148 m68k_set_cacr(mcf5282_cacr_mode); 144 149 rtems_interrupt_enable(level); 150 #endif 145 151 } 146 152 147 153 void _CPU_cache_disable_data(void) 148 154 { 155 #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE 149 156 rtems_interrupt_level level; 150 157 151 158 rtems_interrupt_disable(level); 152 159 rtems_interrupt_disable(level); 153 mcf5282_cacr_mode |= MCF5XXX_CACR_ DISD;160 mcf5282_cacr_mode |= MCF5XXX_CACR_CENB; 154 161 m68k_set_cacr(mcf5282_cacr_mode); 155 162 rtems_interrupt_enable(level); 163 #endif 156 164 } 157 165 158 166 void _CPU_cache_invalidate_entire_data(void) 159 167 { 160 m68k_set_cacr(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); 168 #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE 169 m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); 170 #endif 161 171 } 162 172 163 173 void _CPU_cache_invalidate_1_data_line(const void *addr) 164 174 { 175 #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE 165 176 /* 166 177 * Bottom half of cache is D-space … … 168 179 addr = (void *)((int)addr & ~0x400); 169 180 asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); 181 #endif 170 182 } 171 183 … … 221 233 m68k_set_acr0(mcf5282_acr0_mode); 222 234 m68k_set_acr1(mcf5282_acr1_mode); 223 m68k_set_cacr (MCF5XXX_CACR_CINV);235 m68k_set_cacr_nop(MCF5XXX_CACR_CINV); 224 236 225 237 /*
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