Changeset ac9bbe7 in rtems


Ignore:
Timestamp:
Apr 21, 2005, 12:25:53 AM (15 years ago)
Author:
Eric Norum <WENorum@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
6d4ad17
Parents:
4279a35
Message:

Try insructioin-only cache.

Location:
c/src/lib/libbsp/m68k/uC5282
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/m68k/uC5282/ChangeLog

    r4279a35 rac9bbe7  
     12005-04-20  Eric Norum <norume@aps.anl.gov>
     2
     3        * startup/bspstart.c
     4        * network/network.c: Try instruction-only cache.
     5
    162005-04-19  Eric Norum <norume@aps.anl.gov>
    27
  • c/src/lib/libbsp/m68k/uC5282/include/bsp.h

    r4279a35 rac9bbe7  
    1616#include <rtems/iosupp.h>
    1717#include <rtems/bspIo.h>
     18
     19/***************************************************************************/
     20/**  BSP Configuration                                                    **/
     21/*
     22 * Uncomment to use instruction/data cache
     23 * Leave commented to use instruction-only cache
     24 */
     25/* #define RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE */
    1826
    1927/***************************************************************************/
  • c/src/lib/libbsp/m68k/uC5282/network/network.c

    r4279a35 rac9bbe7  
    408408            int len = rxBd->length - sizeof(uint32_t);;
    409409
    410             /*
    411              * Invalidate the cache and push the packet up.
    412              * The cache is so small that it's more efficient to just
    413              * invalidate the whole thing unless the packet is very small.
    414              */
    415410            m = sc->rxMbuf[rxBdIndex];
     411#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
     412            /*
     413             * Invalidate the cache.  The cache is so small that it's
     414             * more efficient to just invalidate the whole thing unless
     415             * the packet is very small.
     416             */
    416417            if (len < 128)
    417418                rtems_cache_invalidate_multiple_data_lines(m->m_data, len);
    418419            else
    419420                rtems_cache_invalidate_entire_data();
     421#endif
    420422            m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
    421423            eh = mtod(m, struct ether_header *);
  • c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c

    r4279a35 rac9bbe7  
    7070 * DATECODES AFFECTED: All
    7171 */
    72 #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr ; nop" : : "d" (_cacr))
     72#define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
     73#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
    7374#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
    7475#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
     
    7677/*
    7778 * Read/write copy of cache registers
    78  *   Split I/D cache
     79 *   Split instruction/data or instruction-only
    7980 *   Allow CPUSHL to invalidate a cache line
    8081 *   Enable buffered writes
     
    8384 */
    8485uint32_t mcf5282_cacr_mode = MCF5XXX_CACR_CENB |
     86#ifndef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
     87                             MCF5XXX_CACR_DISD |
     88#endif
    8589                             MCF5XXX_CACR_DBWE |
    8690                             MCF5XXX_CACR_DCM;
     
    123127void _CPU_cache_invalidate_entire_instruction(void)
    124128{
    125     m68k_set_cacr(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
     129    m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
    126130}
    127131
     
    137141void _CPU_cache_enable_data(void)
    138142{
     143#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
    139144    rtems_interrupt_level level;
    140145
    141146    rtems_interrupt_disable(level);
    142     mcf5282_cacr_mode &= ~MCF5XXX_CACR_DISD;
     147    mcf5282_cacr_mode &= ~MCF5XXX_CACR_CENB;
    143148    m68k_set_cacr(mcf5282_cacr_mode);
    144149    rtems_interrupt_enable(level);
     150#endif
    145151}
    146152
    147153void _CPU_cache_disable_data(void)
    148154{
     155#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
    149156    rtems_interrupt_level level;
    150157
    151158    rtems_interrupt_disable(level);
    152159    rtems_interrupt_disable(level);
    153     mcf5282_cacr_mode |= MCF5XXX_CACR_DISD;
     160    mcf5282_cacr_mode |= MCF5XXX_CACR_CENB;
    154161    m68k_set_cacr(mcf5282_cacr_mode);
    155162    rtems_interrupt_enable(level);
     163#endif
    156164}
    157165
    158166void _CPU_cache_invalidate_entire_data(void)
    159167{
    160     m68k_set_cacr(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
     168#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
     169    m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
     170#endif
    161171}
    162172
    163173void _CPU_cache_invalidate_1_data_line(const void *addr)
    164174{
     175#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
    165176    /*
    166177     * Bottom half of cache is D-space
     
    168179    addr = (void *)((int)addr & ~0x400);
    169180    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
     181#endif
    170182}
    171183
     
    221233    m68k_set_acr0(mcf5282_acr0_mode);
    222234    m68k_set_acr1(mcf5282_acr1_mode);
    223     m68k_set_cacr(MCF5XXX_CACR_CINV);
     235    m68k_set_cacr_nop(MCF5XXX_CACR_CINV);
    224236
    225237    /*
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