Changeset ac8339a in rtems


Ignore:
Timestamp:
Mar 17, 2015, 10:28:44 AM (4 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
4b7df86
Parents:
8c7eb00
Message:

bsp/mpc55xx: Fix flash settings

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-flash.S

    r8c7eb00 rac8339a  
    88
    99/*
    10  * Copyright (c) 2008-2014 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2008-2015 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
    13  *  Obere Lagerstr. 30
     13 *  Dornierstr. 4
    1414 *  82178 Puchheim
    1515 *  Germany
     
    2626        .section        ".bsp_start_text", "ax"
    2727
    28 .equ FLASH_SETTINGS_RESET, 0xff00
    29 
    3028#if MPC55XX_CHIP_FAMILY == 551
    3129
    3230/* MPC5510 Microcontroller Family Data Sheet, Rev. 3, Table 16, Num 7 */
    33 .equ FLASH_CLOCK_0, 25
    34 .equ FLASH_CLOCK_1, 50
    35 .equ FLASH_CLOCK_2, 80
     31.equ FLASH_CLOCK_0, 25000000
     32.equ FLASH_CLOCK_1, 50000000
     33.equ FLASH_CLOCK_2, 80000000
    3634.equ FLASH_CLOCK_3, FLASH_CLOCK_2
    3735.equ FLASH_SETTINGS_0, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_0 | FLASH_BUICR_RWSC_0 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_1 | FLASH_BUICR_IPFEN_1 | FLASH_BUICR_PFLIM_2 | FLASH_BUICR_BFEN
     
    4341
    4442/* Optimized flash configurations (Table 13-15 [MPC5567 Microcontroller Reference Manual]) */
    45 .equ FLASH_CLOCK_0, 82
    46 .equ FLASH_CLOCK_1, 102
    47 .equ FLASH_CLOCK_2, 132
    48 .equ FLASH_CLOCK_3, 264
     43.equ FLASH_CLOCK_0, 82000000
     44.equ FLASH_CLOCK_1, 102000000
     45.equ FLASH_CLOCK_2, 132000000
     46.equ FLASH_CLOCK_3, 264000000
    4947.equ FLASH_SETTINGS_0, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_1 | FLASH_BUICR_RWSC_1 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_3 | FLASH_BUICR_IPFEN_3 | FLASH_BUICR_PFLIM_6 | FLASH_BUICR_BFEN
    5048.equ FLASH_SETTINGS_1, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_1 | FLASH_BUICR_RWSC_2 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_3 | FLASH_BUICR_IPFEN_3 | FLASH_BUICR_PFLIM_6 | FLASH_BUICR_BFEN
     
    8785        cmpw    r3, r4
    8886        ble     clock_3
    89         LWI     r3, FLASH_SETTINGS_RESET
    90         b       settings_done
     87
     88        /*
     89         * In case we don't have the right flash settings for the system clock
     90         * value, then rely on the BAM settings.
     91         */
     92        blr
     93
    9194clock_0:
    9295        LWI     r3, FLASH_SETTINGS_0
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